1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 1 PPU microcode TITLE.MAC MACRO DEFINITION 2 3 SET LEVELSTRING,25 4 6 7 ***************************************************************************************************** 8 ** This macro is for setting a new title string and starting a new page. * 9 ***************************************************************************************************** 10 11 MACRO ,,PARAMETER 12 NAME TITLE.MAC 13 TITLE PPU3/REV $LEVELSTRING microcode | $PARAMETER 14 EJECT 15 END 16 TITLE.MAC TITLE PAGE 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 2 PPU3/REV 25 microcode | TITLE PAGE 17 18 19 20 21 22 23 * ......... BBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 24 * ................. BBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 25 * ..........##......... BBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 26 * ............##........... BBBBBB BBBBBB TTTTTT TTTTTT TTTTTT IIIIII 27 * .............##............ BBBBBB BBBBBB TTTTT TTTTTT TTTTT IIIIII 28 * .............##............ BBBBBB BBBBBBB TTTT TTTTTT TTTT IIIIII 29 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 30 * ..............##............. BBBBBBBBBBBBBBBBB TTTTTT IIIIII 31 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 32 * .............##.............. BBBBBB BBBBBB TTTTTT IIIIII 33 * ...........##.............. BBBBBB BBBBBB TTTTTT IIIIII 34 * ..........##............... BBBBBB BBBBBB TTTTTT IIIIII 35 * ........##............... BBBBBB BBBBBBB TTTTTT IIIIII 36 * .....##.............. BBBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 37 * ................. BBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 38 * ......... BBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 39 * 40 * 41 * ****** Copyright 1986, 1990, 1991 BTI Computer Systems ****** 42 * 43 * This document and the program it describes are the exclusive property 44 * of and proprietary to BTI Computer Systems. No use, reproduction or 45 * disclosure of this document or its contents, either in full or in part, 46 * by any means whatsoever regardless of purpose may be made without the 47 * prior written consent of BTI Computer Systems. 48 * 49 * BTI Computer Systems 50 * Sunnyvale, California 94086 51 52 53 54 55 56 * PPPPPP PPPPPP UU UU CCCCC OOOOO DDDDDD EEEEEEE 57 * PPPPPPP PPPPPPP UU UU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 58 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 59 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 60 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 61 * PPPPPPP PPPPPPP UU UU UU UU CC OO OO DD DD EEEEEEE 62 * PPPPPP PPPPPP UU UU UU UU ---- CC OO OO DD DD EEEEEEE 63 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 64 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 65 * PP PP UU UU UU UU CC OO OO DD DD EE 66 * PP PP UU UU UU CC OO OO DD DD EE 67 * PP PP UU UU UU CC OO OO DD DD EE 68 * PP PP UUUUUUU UUUU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 69 * PP PP UUUUU UU CCCCC OOOOO DDDDDD EEEEEEE 70 71 72 TITLE.MAC TITLE PAGE 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 3 PPU3/REV 25 microcode | TITLE PAGE 73 74 75 76 77 78 79 * ......... BBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 80 * ................. BBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 81 * ..........##......... BBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 82 * ............##........... BBBBBB BBBBBB TTTTTT TTTTTT TTTTTT IIIIII 83 * .............##............ BBBBBB BBBBBB TTTTT TTTTTT TTTTT IIIIII 84 * .............##............ BBBBBB BBBBBBB TTTT TTTTTT TTTT IIIIII 85 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 86 * ..............##............. BBBBBBBBBBBBBBBBB TTTTTT IIIIII 87 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 88 * .............##.............. BBBBBB BBBBBB TTTTTT IIIIII 89 * ...........##.............. BBBBBB BBBBBB TTTTTT IIIIII 90 * ..........##............... BBBBBB BBBBBB TTTTTT IIIIII 91 * ........##............... BBBBBB BBBBBBB TTTTTT IIIIII 92 * .....##.............. BBBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 93 * ................. BBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 94 * ......... BBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 95 * 96 * 97 * ****** Copyright 1986, 1990, 1991 BTI Computer Systems ****** 98 * 99 * This document and the program it describes are the exclusive property 100 * of and proprietary to BTI Computer Systems. No use, reproduction or 101 * disclosure of this document or its contents, either in full or in part, 102 * by any means whatsoever regardless of purpose may be made without the 103 * prior written consent of BTI Computer Systems. 104 * 105 * BTI Computer Systems 106 * Sunnyvale, California 94086 107 108 109 110 111 112 * PPPPPP PPPPPP UU UU CCCCC OOOOO DDDDDD EEEEEEE 113 * PPPPPPP PPPPPPP UU UU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 114 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 115 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 116 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 117 * PPPPPPP PPPPPPP UU UU UU UU CC OO OO DD DD EEEEEEE 118 * PPPPPP PPPPPP UU UU UU UU ---- CC OO OO DD DD EEEEEEE 119 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 120 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 121 * PP PP UU UU UU UU CC OO OO DD DD EE 122 * PP PP UU UU UU CC OO OO DD DD EE 123 * PP PP UU UU UU CC OO OO DD DD EE 124 * PP PP UUUUUUU UUUU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 125 * PP PP UUUUU UU CCCCC OOOOO DDDDDD EEEEEEE 126 127 128 TITLE.MAC Revision Log 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 4 PPU3/REV 25 microcode | Revision Log 130 131 ***************************************************************************************************** 132 * * 133 * LOG OF CHANGES * 134 * * 135 * Revision 12 March, 1985 ECN 1565 * 136 * -------- -- ------ ---- --- ---- * 137 * * 138 * Note that this ECN includes changes from rev 9 ucode to * 139 * rev 12 ucode. * 140 * * 141 * Interrupts are now enabled on a few more instructions * 142 * in the idle loop * 143 * * 144 * Changed CKBUSACT routine in idle loop so bus RTO timer is * 145 * reset whenever the byte count changes. In the old version, * 146 * SCRB (the bus transfer counter) was incremented by the * 147 * routines that did bus transfers. This causes the CKBUSACT * 148 * routine to reset the RTO timer (since it sees a new value in * 149 * SCRB). Now, the port routines do not touch this counter * 150 * (SCRB) since the CKBUSACT routine routine resets the RTO * 151 * timer when it sees that the byte count has changed. This * 152 * should increase input and output bandwidth slightly. * 153 * * 154 * Internal byte counts are now initialized to zero on * 155 * power up sequence * 156 * * 157 * Miscellaneous speed ups * 158 * * 159 * Fixes to make non-word boundary transfers END correctly * 160 * (start of transfer was not changed). Before, the part of * 161 * the last word that did not get new data was set to zero, * 162 * sometimes the last fractional part of a word was not put in * 163 * memory, and checking for extra input was not done correctly. * 164 * Now, the PPU reads the word from memory and only changes the * 165 * bytes that need to change. Also, extra input checking is * 166 * now done correctly, and the few cases that did not work * 167 * correctly have been corrected. This particular fix closes * 168 * SPR 8840530-006 (BTI code CS0163) and SPR 8840313-001 (BTI * 169 * code CS0129). * 170 * * 171 * Bug fix so WRU 1 reports bad data instead of bad * 172 * pseudo-address when an improper byte count is written. * 173 * * 174 * Miscellaneous minor bug fixes in selftest routine. * 175 * * 176 * Fixed bus error for heavily loaded systems. This bus * 177 * error gave a WRU 1 of either B (PPU bus logic confused) or 1 * 178 * (bus parity error). If the bus error was parity error, WRU * 179 * 1, 2, and 3 looked like the PPU received a dead bus. The * 180 * bus error usually also caused the PPU to do a double word * 181 * read to a memory and NAK the second word of the reply. * 182 * Whenever this bus error occurred, one PPU port would usually * 183 * have status of 8882, and the disk controller PPU port would * 184 * have status of 0815, a small byte count, an odd memory * 185 * address (should be even), and will have just done a byte * 186 * count rollover and started again at an odd address. This * 187 * bus error was caused by a stack overflow condition, so the * 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 5 PPU3/REV 25 microcode | Revision Log 188 * fix was to replace some subroutine calls (particularly in * 189 * the interrupt routines) with different ways of doing things. * 190 * * 191 * * 192 * Revision 15 Dec, 1986 ECN 1644 * 193 * -------- -- ---- ---- --- ---- * 194 * * 195 * Previously, if an output transfer that ended on an even * 196 * address were followed by an address that returned abnormal * 197 * data, a memory parity error might have been erroneously * 198 * reported in the port status. This bug has been fixed in * 199 * this release. * 200 * * 201 * Occasionally, when running in the offline environment * 202 * which polls for interrupts, the 'BCROLL' bit in the port * 203 * status register was missed by the software. This caused * 204 * erroneous byte count not ready errors. This bug has been * 205 * fixed in this release. * 206 * * 207 * A minor enhancement in the CPU read processor section of * 208 * the microcode allows port status read requests to return two * 209 * bus ticks earlier. * 210 * * 211 * * 212 * Revision 17 Feb, 1990 ECN 1715 * 213 * -------- -- ---- ---- --- ---- * 214 * * 215 * Major modifications to the byte count rollover logic. * 216 * Previous versions would set an error and terminate the * 217 * transfer if a primary byte count rolled over and the next * 218 * secondary byte count was not ready yet. This, in general, * 219 * is not needed, since the peripheral controllers will detect * 220 * an overrun/underrun situation. In the case of asyncronous * 221 * controllers, particularly very fast ones, this feature * 222 * caused needless transfer aborts. This has been changed so * 223 * that the port just waits for the secondary count to be * 224 * loaded and then continues the transfer. * 225 * * 226 * Modified CPU command interpreter to ignore store * 227 * command 'set triple word transfer' and the corresponding * 228 * load command. Triple word store is not available on * 229 * PPU3/4, but this ensures compatibility with software * 230 * selecting this option for PPU5s. * 231 * * 232 * Major modifications to the selftest code, including: * 233 * Now uses micro instruction address as the error code, many * 234 * tests discarded and replaced with tests originally written * 235 * for the PPU5, bus transfer/interrupt test now only tests * 236 * bus error for a short period, controllers not released * 237 * until bus error testing done. * 238 * * 239 * Modifications to the idle loop EOR processor and the CPU * 240 * write processor to free up SCR4 to be used in port timing * 241 * functions. Modifications to the timing functions so that * 242 * controllers get about 13 ms to answer a request. The range * 243 * of response times back to the bus is now 14 to 18 Msec. * 244 * * 245 * * 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 6 PPU3/REV 25 microcode | Revision Log 246 * Revision 25 Jul, 1991 ECN 1724 * 247 * -------- -- ---- ---- --- ---- * 248 * * 249 * Revision levels now in decimal in documentation. * 250 * * 251 * Bug fix in secondary byte count loader where interrupts * 252 * were enabled improperly such that a byte count rollover * 253 * interrupt could be lost. * 254 * * 255 * Modifications to the WTFORBUS subroutine to ensure * 256 * that it does not time out if the data channels are continuously * 257 * requesting interrupt. * 258 * * 259 * Changed the I to IP on quite a large number of POP * 260 * instructions. The I...POP construct caused stack overflows * 261 * in rare cases of worst case interrupt timing. * 262 * * 263 * Modified the call back needed processor to skip fetching * 264 * the second bus word on a single word transfer. * 265 * * 266 ***************************************************************************************************** 267 TITLE.MAC MACRO definitions 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 7 PPU3/REV 25 microcode | MACRO definitions 268 269 >>>>>>>>>> 270 > MACRO ,, 271 > NAME SKIPORG, NOLIST DETAIL 272 > IF (* AND 1) EQ 0, EXIT 273 > 274 > NAME WASTE, NOLIST DETAIL 275 > IF P' EQ 0, LIST MACROS 276 >WSTE$WSTECNTR * ****** wasted ****** 277 >WSTECNTR REEQU WSTECNTR+1 278 > END 279 > 0000 280 >WSTECNTR EQU 0 0000 281 >WSTEPNTR EQU 0 282 >>>>>>>>>> 284 >>>>>>>>>> 285 > MACRO ,, 286 > NAME STARTSKP, NOLIST DETAIL 287 > IF (* AND 1) EQ 1, EXIT 288 > IF WSTEPNTR GE WSTECNTR, GOTO IFBLOCK 289 >MEMORY REEQU * 290 > ORG WSTE$WSTEPNTR 291 >WSTEPNTR REEQU WSTEPNTR+1 292 >.READQ RESET Q+ 293 > LIST MACROS 294 >$Q 295 > NOLIST MACROS 296 > ORG MEMORY 297 > EXIT 298 > 299 >.IFBLOCK IF BLOCKON EQ 0, GOTO HERE 300 >MEMORY REEQU * 301 > ORG REMEMBER 302 >REMEMBER REEQU REMEMBER+1 303 > GOTO READQ 304 > 305 >.HERE RESET Q+ 306 > LIST MACROS 307 >$Q 308 > NOLIST MACROS 309 > WASTE 310 > END 311 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 8 PPU3/REV 25 microcode | MACRO definitions 313 314 315 >>>>>>>>>> 316 > MACRO ,,PARAMS 317 > NAME BLOCK, NOLIST MACROS 318 > IF BLOCKON, ENDBLOCK 319 >REMEMBER REEQU * 320 >BLK.SIZE REEQU $PARAMS(1) 321 > IF BLK.SIZE EQ 4, GOTO BLOCK4 322 > IF BLK.SIZE EQ 8, GOTO BLOCK8 323 > IF BLK.SIZE EQ 16, GOTO BLOCK16 324 > Bad Call 325 > GOTO EXIT 326 > 327 >.BLOCK4 IF B4.USED LT 4, GOTO BLOCK4A 328 >B4.USED REEQU 0 329 >B4.ORG REEQU BLOCKORG 330 >BLOCKORG REEQU BLOCKORG-16 331 >.BLOCK4A ORG B4.ORG 332 >B4.ORG REEQU B4.ORG+4 333 >$PARAMS(2) EQU (B4.USED*4) AND #C 334 >B4.USED REEQU B4.USED+1 335 > GOTO EXIT 336 > 337 >.BLOCK8 IF B8.USED LT 2, GOTO BLOCK8A 338 >B8.USED REEQU 0 339 >B8.ORG REEQU BLOCKORG 340 >BLOCKORG REEQU BLOCKORG-16 341 >.BLOCK8A ORG B8.ORG 342 >B8.ORG REEQU B8.ORG+8 343 >$PARAMS(2) EQU (B8.USED*8) AND #8 344 >B8.USED REEQU B8.USED+1 345 > GOTO EXIT 346 > 347 >.BLOCK16 ORG BLOCKORG 348 >BLOCKORG REEQU BLOCKORG-16 349 >.EXIT 350 >BLOCKADD REEQU * 351 >BLOCKON REEQU 1 352 > END 353 > 354 > MACRO 355 > NAME ENDBLOCK, NOLIST MACROS 356 > IF BLOCKADD+BLK.SIZE GE *, GOTO BLK.REP 357 > Size Exceeded 358 > GOTO GO.BACK 359 > 360 >.BLK.REP REP BLOCKADD+BLK.SIZE-*,N 361 > WASTE 362 >.GO.BACK ORG REMEMBER 363 >BLOCKON REEQU 0 364 > END 365 > 07E0 366 >BLOCKORG EQU #7E0 0000 367 >BLOCKON EQU 0 0004 368 >B4.USED EQU 4 0002 369 >B8.USED EQU 2 370 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 9 PPU3/REV 25 microcode | MACRO definitions 372 373 374 >>>>>>>>>> 375 > MACRO ,, 376 > NAME VECTOR, NOLIST MACROS 377 > IF VECTORON, ENDVECTOR 378 >REMEMBER REEQU * 379 > ORG VECTORORG 380 >VECTORORG REEQU VECTORORG+16 381 >VECTORADD REEQU * 382 >VECTORON REEQU 1 383 > END 384 > 385 > MACRO 386 > NAME ENDVECTOR, NOLIST MACROS 387 > IF VECTORADD+16 GE *, GOTO VEC.REP 388 > Size Exceeded 389 > GOTO GO.BACK 390 > 391 >.VEC.REP REP VECTORADD+16-*,N 392 > WASTE 393 >.GO.BACK ORG REMEMBER 394 >VECTORON REEQU 0 395 > END 396 > 0010 397 >VECTORORG EQU #010 0000 398 >VECTORON EQU 0 399 >>>>>>>>>> 401 >>>>>>>>>> 402 > MACRO ,,N 403 > NAME REP, NOLIST MACROS 404 >REP.RPT REEQU $N(1) 405 >REP.LST REEQU A'$N(2)' NE A'N' 406 > RESET N+ 407 >.REP01 IF REP.RPT LE 0, EXIT 408 > IF REP.LST, LIST MACROS 409 >$N 410 > NOLIST MACROS 411 >REP.RPT REEQU REP.RPT-1 412 > GOTO REP01 413 > END 414 >>>>>>>>>> 415 TITLE.MAC RAM allocation 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 10 PPU3/REV 25 microcode | RAM allocation 0000 416 ORG #000 417 * RAM allocation 418 000 419 NEXTPORT BSS 4 number of next port to service 420 004 421 PBITLOW BSS 4 2^(port #) 008 422 PBITHIGH BSS 4 2^(port # + 4) 00C 423 PBITIM BSS 4 port interrupt mask bit 424 010 425 FLAGS BSS 4 command/status I/O control flags 014 426 PRTST BSS 4 port's internal status 427 018 428 EORTIMER BSS 4 timer used by EOR processing 429 01C 430 CLKFIX BSS 4 used by timer correction function 431 020 432 TYPECKSM BSS 4 C/S type/byte count and checksum 024 433 CNTDOWN BSS 4 C/S time-out counter 028 434 ADDRESS BSS 4 C/S address 02C 435 HWORD BSS 4 C/S high order word 030 436 LWORD BSS 4 C/S low order word 034 437 RESPTO BSS 4 slot awaiting response / bus control bits 438 038 439 HSW1 BSS 4 controller's high order status word one 03C 440 LSW1 BSS 4 controller's low order status word one 040 441 HSW2 BSS 4 controller's high order status word two 044 442 LSW2 BSS 4 controller's low order status word two 443 048 444 BCOVERUN BSS 4 byte count overrun detector (pair two loaded) 04C 445 CORBC BSS 4 byte count correction factor, BC=BCNT+LAST+CORBC 446 050 447 SLOT BSS 4 memory slot / bus control flags / pair one 054 448 BCNT BSS 4 DMA byte count as a multiple of four or eight / pair one 058 449 LAST BSS 4 DMA byte count with LAST bit and residual / pair one 05C 450 HADDR BSS 4 high order memory address / bus command / pair one 060 451 LADDR BSS 4 low order memory address / pair one 452 064 453 SLOT2 BSS 4 memory slot / bus control flags / pair two 068 454 BCNT2 BSS 4 DMA byte count as a multiple of four or eight / pair two 06C 455 LAST2 BSS 4 DMA byte count with LAST bit and residual / pair two 070 456 HADDR2 BSS 4 high order memory address / bus command / pair two 074 457 LADDR2 BSS 4 low order memory address / pair two 458 078 459 BIHC BSS 4 bus input data / high order command word 07C 460 BILC BSS 4 bus input data / low order command word 080 461 BIHD BSS 4 bus input data / high order data word 084 462 BILD BSS 4 bus input data / low order data word 088 463 BIFT BSS 4 bus input data / FROM-TO register 08C 464 BIST BSS 4 bus input status 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 11 PPU3/REV 25 microcode | RAM allocation 466 090 467 WRURES1A BSS 4 These 32 locations hold the WRU responses 094 468 WRURES1B BSS 4 098 469 WRURES2A BSS 4 09C 470 WRURES2B BSS 4 0A0 471 WRURES3A BSS 4 0A4 472 WRURES3B BSS 4 0A8 473 WRURES4A BSS 4 0AC 474 WRURES4B BSS 4 475 0B0 476 TEMP BSS 4 may not be used by interrupt routines 0B4 477 TEMP2 BSS 4 may not be used by interrupt routines 478 0B8 479 OLDBCNT BSS 4 used for temp storage-timeout checking 480 0BC 481 IBFCKPE BSS 4 used to check for memory parity errors by IBF routines 482 TITLE.MAC EQU & Register definitions 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 12 PPU3/REV 25 microcode | EQU & Register definitions 0000 483 ORG #000 484 485 EXPAND ON 0019 486 LEVEL EQU 25 microcode revision level 487 * change this constant by changing the LEVELSTRING constant 488 * on page 1 489 EXPAND OFF 490 0004 491 NUMPORTS EQU 4 number of ports connected: numbered 0 to NUMPORTS-1 492 FFFF 493 CM EQU -1 CM-x is read "complement of" x 494 495 ***************************************************************************************************** 496 * * 497 * Time-out Constants * 498 * The timeout constants named TIM* are used to control the * 499 * timer that deadmans the PPU to controller communications. This * 500 * timer is a counter that counts the number of times through the * 501 * IDLE loop, but the counter (SCR4) needs to be incremented by * 502 * any work that significantly slows down the progress through the * 503 * IDLE loop. * 504 * TIMBYTC, TIMBYRD, and TIMBYWR are used to control the * 505 * counter increment that adjusts for the (considerable) overhead * 506 * of actually transferring data to or from a channel. This overhead * 507 * must be allocated approximately as incurred, so the idle loop * 508 * checks for TIMBYTC bytes to be transferred, then uses one of the * 509 * other values to adjust the timeout counter. * 510 * * 511 ***************************************************************************************************** 512 513 * These first constants are counts 'through the idle loop' 514 * (between 10.3 and 11.2 microseconds) 515 053C 516 TIMECNST EQU 1340 time-out counter constant (C/S) = 15 msec 0001 517 TIMIDLE EQU 1 number of counts added each time through idle loop 0004 518 TIMECSIN EQU 4 fudge for each word sent by controller 0001 519 TIMERSPX EQU 1 fudge for each word returned to CPU 0003 520 TIMERW EQU 3 fudge for each word requested by CPU from controller 0006 521 TIMEWW EQU 6 fudge for each word written by CPU to controller 522 0200 523 TIMBYTC EQU 512 bytes of I/O equivalent to TIMBYRD or TIMBYWR counts 0018 524 TIMBYRD EQU 24 counts for read of TIMBYTC bytes 000C 525 TIMBYWR EQU 12 counts for write of TIMBYTC bytes 526 527 * Other timeout values 528 007D 529 CBNTO EQU 125 time-out counter constant (CBN) =.1 msec 000C 530 BUSTO EQU 12 time-out counter constant (Idle Loop monitor) >=.1 msec 007D 531 BUSTO2 EQU 125 time-out counter constant (EOR processor) >=.1msec 532 * WFBTO and WFBTO2 are used in the WaitForBus routine in a loop 533 * consisting of 3 T4 instructions (.8 usec) 0064 534 WFBTO EQU 100 time-out counter constant (Waiting for the BUS) >= 80 usec 04E2 535 WFBTO2 EQU 1250 time-out counter constant (Waiting for the BUS) >= 1 msec 536 * CTMTO is used in the Bus error routine in a loop 537 * consisting of 3 T4 instructions (.8 usec) 007D 538 CTMTO EQU 125 time-out counter constant (Copy to Me) =.1 msec 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 13 PPU3/REV 25 microcode | EQU & Register definitions 540 ***************************************************************************************************** 541 * * 542 * PPU Internal Status Bits Definitions (SCR6) * 543 * * 544 * The low order byte of SCR6 is used as a timer for BUS transfers * 545 * * 546 ***************************************************************************************************** 0100 548 SOPPFW EQU #100 We have seen PFW asserted 0200 549 SOPBTO EQU #200 We are timing a BUS transfer 550 551 552 ***************************************************************************************************** 553 * * 554 * Command/Status byte definitions * 555 * These are definitions for the first byte transmitted * 556 * on the command/status path (between PPU and controller). * 557 * * 558 ***************************************************************************************************** 559 000E 560 ACK EQU #0E C/S acknowledge code 00F8 561 NAK EQU #F8 C/S negative acknowledge code 562 0050 563 INTR EQU #50 C/S interrupt request from controller 0054 564 INTRS EQU #54 C/S interrupt request with status from controller 00C4 565 LS1 EQU #C4 C/S load controller status word one transmission 0034 566 LS2 EQU #34 C/S load controller status word two transmission 0060 567 GO EQU #60 C/S controller request data from PPU 0090 568 EOR EQU #90 C/S end of record code from controller 00A4 569 RESP EQU #A4 C/S response from controller 570 0062 571 CTLRRD EQU #62 C/S read command to controller 0096 572 CTLRWR EQU #96 C/S write command to controller 573 574 ***************************************************************************************************** 575 * * 576 * These values are used to initialize the TYPECKSM * 577 * variable when a transmission on the C/S path is * 578 * initiated. * 579 * * 580 ***************************************************************************************************** 581 8000 582 CRDTEST EQU #8000 used in read/write test 809D 583 CRDSTART EQU (CTLRRD XOR #FF)+CRDTEST controller read start value 0069 584 CWRSTART EQU (CTLRWR XOR #FF) controller write start value 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 14 PPU3/REV 25 microcode | EQU & Register definitions 586 ***************************************************************************************************** 587 * * 588 * Definitions for FLAGS * 589 * also note that the lower 8 bits of FLAGS are used a follows: * 590 * Bits 7-4 number representing the state of the C/S handshake * 591 * BITS 3-0 I/O retry count * 592 * * 593 ***************************************************************************************************** 594 0100 595 DOINGINP EQU #0100 C/S Input transfer in progress 0200 596 DOINGOUT EQU #0200 C/S Output transfer in progress 0400 597 TIMING EQU #0400 C/S Timing on port in progress 0800 598 WAITING EQU #0800 C/S Waiting for response on this port 1000 599 RGOB EQU #1000 C/S GO-byte received on this port 2000 600 REOR EQU #2000 C/S EOR-byte received on this port 4000 601 PORTDEAD EQU #4000 C/S port DEAD 8000 602 TIMEDOUT EQU #8000 C/S port has been timed-out 603 40C0 604 SETDEAD EQU PORTDEAD+#C0 C0D0 605 SETIMED EQU TIMEDOUT+PORTDEAD+#D0 606 FC00 607 CLRFLAGS EQU #FF00-DOINGOUT-DOINGINP F3FF 608 CLRWAIT EQU CM-WAITING-TIMING F4FF 609 CSFREE EQU CM-WAITING-DOINGOUT-DOINGINP 610 0520 611 STARTINP EQU TIMING+DOINGINP+#20 0070 612 SENDRESP EQU #70 613 0080 614 RESTRDWR EQU #80 0681 615 STARTWR EQU TIMING+DOINGOUT+RESTRDWR+1 0E81 616 STARTRD EQU STARTWR+WAITING 00F0 617 RECVRESP EQU #F0 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 15 PPU3/REV 25 microcode | EQU & Register definitions 619 ***************************************************************************************************** 620 * * 621 * Port Status Bits * 622 * These are definitions for the bits that are retrieved * 623 * from the port logic using a PTST op-code. * 624 * * 625 ***************************************************************************************************** 626 4000 627 PRTPON EQU #4000 Controller status: PON+ de-asserted 2000 628 PRTCI EQU #2000 Command path status: Command.In 1000 629 PRTFREE EQU #1000 Command path status: path Free 0800 630 PRTINT EQU #0800 Data path status: no FIFO interrupt pending 0400 631 PRTPE EQU #0400 Data path status: input parity error 0200 632 PRTHIGH EQU #0200 Data path status: FIFO has a high byte 0100 633 PRTLOW EQU #0100 Data path status: FIFO has a low byte FCFF 634 PRTEMPTY EQU CM-PRTHIGH-PRTLOW port empty mask 635 0000 636 BLANKS EQU #0000 odd byte transfer fill characters 638 ***************************************************************************************************** 639 * * 640 * port command bits * 641 * * 642 ***************************************************************************************************** 643 0000 644 DIRINP EQU 0 port direction is INPUT 0001 645 DIROUT EQU 1 port direction is OUTPUT 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 16 PPU3/REV 25 microcode | EQU & Register definitions 647 ***************************************************************************************************** 648 * * 649 * Port & Interrupt Control * 650 * Definitions for the interrupt control, etc. * 651 * * 652 ***************************************************************************************************** 653 0003 654 PRTNUMMASK EQU NUMPORTS-1 used by interrupt routine to mask off port number 655 0001 656 PORTLOW EQU 2^0 port zero low bit 0010 657 PORTHIGH EQU 2^4 port zero high bit 658 0020 659 IBFIM EQU 2^5 input buffer full interrupt mask bit 0010 660 CBNIM EQU 2^4 call back needed interrupt mask 0008 661 PORT3IM EQU 2^3 port three interrupt mask 0004 662 PORT2IM EQU 2^2 0002 663 PORT1IM EQU 2^1 0001 664 PORT0IM EQU 2^0 port zero interrupt mask 665 FFCF 666 INITINTS EQU CM-IBFIM-CBNIM initial interrupt mask - Input Buffer Full & Call Back Needed 667 668 ***************************************************************************************************** 669 * * 670 * Interrupt address pointer definitions. * 671 * These are the values that go into the RAM address field when * 672 * using the IADR destination to set up the interrupt vectors. * 673 * * 674 * Input Buffer Full (IBF) vector handling * 675 * The way this interrupt vector is handled is as follows: * 676 * This interrupt vector is initialized to TWOWORDS and * 677 * stays there except for those few cases (primarily end * 678 * of odd length transfers, etc) where an alternate routine * 679 * is needed. In those cases, right after the read command * 680 * is output to the bus (SBCB op-code), IBFIADR is changed * 681 * to the desired interrupt routine. * 682 * No other channel is allowed to interrupt (hardware disable) * 683 * until the bus is not busy, then the IBF interrupt has the * 684 * priority. This ensures that the channel that set up the * 685 * alternate routine is the only one that uses it. * 686 * This interrupt routine then changes IBFIADR back to TWOWORDS * 687 * before it exits or gets into an interruptable part. * 688 * * 689 ***************************************************************************************************** 690 0020 691 IBFIADR EQU 2*2^4 system bus input buffer full interrupt address pointer 0030 692 CBNIADR EQU 3*2^4 call back needed interrupt address pointer 0040 693 PRT3IADR EQU 4*2^4 port three interrupt address pointer 0050 694 PRT2IADR EQU 5*2^4 0060 695 PRT1IADR EQU 6*2^4 0070 696 PRT0IADR EQU 7*2^4 port zero interrupt address pointer 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 17 PPU3/REV 25 microcode | EQU & Register definitions 698 ***************************************************************************************************** 699 * * 700 * System Bus Status Definitions * 701 * These are the definitions of the bus status retrieved * 702 * with the SBST source. * 703 * * 704 ***************************************************************************************************** 705 8000 706 PFWNOT EQU #8000 system bus status input--power fail warning (active LOW) 4000 707 BPE EQU #4000 system bus status input--BUS parity error 0800 708 RTOIN EQU #0800 system bus status input--request to output 0400 709 CBN EQU #0400 system bus status input--call back needed 0200 710 RFRIN EQU #0200 system bus status input--ready for response 0100 711 RFIIN EQU #0100 system bus status input--ready for input 0080 712 DWTIN EQU #0080 system bus status input--double word transfer 0040 713 IBF EQU #0040 system bus status input--input buffer full F5BF 714 BUSFREE EQU CM-RTOIN-RFRIN-IBF flags for checking if the BUS is free F5FF 715 BUSACTIV EQU CM-RTOIN-RFRIN flags for checking if the BUS has timed-out 716 717 ***************************************************************************************************** 718 * * 719 * System Bus Flag Definitions * 720 * The bus flags appear in various two bit fields in both * 721 * the SBST source and the SBCB destination. These are the * 722 * various definitions for the flag values. * 723 * * 724 ***************************************************************************************************** 725 0000 726 FLAGSAB EQU 0 tags for abnormal data (memory parity error) 0001 727 FLAGSDATA EQU 1 tags for normal data 0002 728 FLAGSCOMM EQU 2 tags for command word 729 7030 730 FLAGMASK EQU BPE+#3030 mask for input flags 1000 731 WORD1DATA EQU FLAGSDATA*#1000 value for data flags for word 1 only 2020 732 COMMCOMM EQU FLAGSCOMM*#1000+FLAGSCOMM*#10 value for single word command 2010 733 COMMDATA EQU FLAGSCOMM*#1000+FLAGSDATA*#10 value for double word command 1010 734 DATADATA EQU FLAGSDATA*#1000+FLAGSDATA*#10 value for single word data 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 18 PPU3/REV 25 microcode | EQU & Register definitions 736 ***************************************************************************************************** 737 * * 738 * System Bus Command & Status Definitions * 739 * These are the definitions for use with the SBCB destination. * 740 * * 741 ***************************************************************************************************** 742 8000 743 HPR EQU #8000 system bus control output--high priority request 2000 744 BSE EQU #2000 system bus control output--bus error 0008 745 RFROUT EQU #0008 system bus control output--ready for response 0004 746 RFR2OUT EQU #0004 system bus control output--ready for response/second word 0004 747 RFIOUT EQU #0004 system bus control output--ready for input 0002 748 DWTOUT EQU #0002 system bus control output--double word transfer 0001 749 RTOOUT EQU #0001 system bus control output--request to output 750 0011 751 RTODATA EQU FLAGSDATA*#10+RTOOUT respond to CPU 0010 752 ADATAXOR EQU (FLAGSDATA XOR FLAGSAB)*#10 XOR to change Good Data to Abnormal 0004 753 XORFF1W EQU RFR2OUT XOR to change Double Read to Single 009B 754 COPYTOME EQU FLAGSCOMM*#40+FLAGSDATA*#10+DWTOUT+RTOOUT+RFROUT copy output to input 755 756 * For use with the SBINT destination. 0001 757 INT EQU #0001 system bus control output--interrupt 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 19 PPU3/REV 25 microcode | EQU & Register definitions 759 ***************************************************************************************************** 760 * * 761 * System Bus Command Definitions * 762 * READBITS, and WRITBITS are composites of a bus command (SBHC) * 763 * and the bus control bits (SBCB). They are set up this way for * 764 * convenience of use in the code. * 765 * * 766 ***************************************************************************************************** 767 2000 768 READ1W EQU #2000 system bus single word read 3000 769 READ2W EQU #3000 system bus double word read 0000 770 WRITE EQU #0000 system bus write 771 B02D 772 READBITS EQU HPR+READ2W+FLAGSCOMM*#10+RFROUT+RFR2OUT+RTOOUT read from memory 8063 773 WRITBITS EQU HPR+WRITE+FLAGSDATA*#40+FLAGSCOMM*#10+DWTOUT+RTOOUT write into memory 774 1000 775 XORCF1W EQU READ1W XOR READ2W XOR to change Double Read to Single 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 20 PPU3/REV 25 microcode | EQU & Register definitions 777 ***************************************************************************************************** 778 * * 779 * Internal Port Status (PRTST) Bit Definitions * 780 * * 781 ***************************************************************************************************** 782 0001 783 DMADIR EQU #0001 DMA direction, 1=write, 0=read (CPU perspective) 0002 784 PPUINTR EQU #0002 PPU requests CPU to interrupt 0004 785 DMAOE EQU #0004 DMA output to controller enabled 0008 786 CTLRINTR EQU #0008 controller requests CPU to interrupt 0010 787 BCROLL EQU #0010 byte count rollover 0020 788 BCLAST EQU #0020 last byte count processed 0040 789 BCNRDY EQU #0040 waiting for next byte count 0080 790 DMANBZ EQU #0080 DMA not busy 0100 791 MPECODE EQU #0100 memory parity error 0200 792 BCINT EQU #0200 cause PPUINTR on BCROLL 0400 793 COCKPIT EQU #0400 PPU is in strange state / must do an ABORT 0800 794 CTLRINTE EQU #0800 controller allowed to interrupt CPU 1000 795 PPUINTE EQU #1000 PPU allowed to interrupt CPU 2000 796 DPPE EQU #2000 data path parity error 4000 797 EXTRA EQU #4000 unexpected input received on data path 8000 798 BTWREC EQU #8000 between records (set by EOR from controller) 800 ***************************************************************************************************** 801 * * 802 * PSEUDO ADDRESS DEFINITIONS * 803 * * 804 ***************************************************************************************************** 805 3000 806 PPUTYPE EQU #3000 type code for a PPU 807 0200 808 CBIT EQU #0200 command word bit that says "to controller" 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 21 PPU3/REV 25 microcode | EQU & Register definitions 810 ***************************************************************************************************** 811 * * 812 * Combined status bits: * 813 * LASTBC bits set by last byte count being completed * 814 * BCRATEOR bits set when BC rollover occurs at EOR * 815 * EORINTR bits set when EOR processing is completed * 816 * OVRRUN bits set when next byte count isn't ready on time * 817 * CONFUSED bits set when something is wrong * 818 * CTLRINT if all these bits are on then do interrupt * 819 * PPUINT if all these bits are on then do interrupt * 820 * INTCLR bits cleared when WRU gets interrupting port number * 821 * PRTINIT initial status of port on power-up * 822 * ENDWRITE bits set when EOR terminates write * 823 * GOODBITS bits that may be changed by CPU * 824 * STSCLBTS bits cleared by reading status * 825 * BC1CLR bits cleared by loading byte count one * 826 * ABTCLR bits cleared by ABORT * 827 * ABTSET bits set by ABORT * 828 * * 829 ***************************************************************************************************** 830 00B2 831 LASTBC EQU BCLAST+DMANBZ+BCROLL+PPUINTR 0092 832 BCRATEOR EQU DMANBZ+PPUINTR+BCROLL 0082 833 EORINTR EQU DMANBZ+PPUINTR 0050 834 OVRRUN EQU BCNRDY+BCROLL 0402 835 CONFUSED EQU COCKPIT+PPUINTR 0808 836 CTLRINT EQU CTLRINTE+CTLRINTR 1002 837 PPUINT EQU PPUINTE+PPUINTR E7FF 838 INTCLR EQU CM-PPUINTE-CTLRINTE 8080 839 PRTINIT EQU DMANBZ+BTWREC 7FFB 840 BTWRECOE EQU CM-BTWREC-DMAOE 8082 841 ENDWRITE EQU BTWREC+DMANBZ+PPUINTR 1A01 842 GOODBITS EQU PPUINTE+CTLRINTE+BCINT+DMADIR FFE5 843 STSCLBTS EQU CM-BCROLL-CTLRINTR-PPUINTR 1E0B 844 BC1CLR EQU CM-EXTRA-BTWREC-DPPE-MPECODE-DMANBZ-BCNRDY-BCLAST-BCROLL-DMAOE 9A89 845 ABTCLR EQU CM-EXTRA-COCKPIT-DMAOE-PPUINTR-BCROLL-BCLAST-BCNRDY-MPECODE-DPPE 8080 846 ABTSET EQU BTWREC+DMANBZ 847 8000 848 LASTBIT EQU #8000 bit in a byte count that says it is the last one 849 TITLE.MAC Scratch Register usage 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 22 PPU3/REV 25 microcode | Scratch Register usage 851 ***************************************************************************************************** 852 * * 853 * Scratch Register Usage: * 854 * * 855 * SCR n USE * 856 * ----- ------------------------------------------------------ * 857 * 0 IDLE loop scratch * 858 * 1 IDLE loop scratch * 859 * 2 IDLE loop scratch * 860 * 3 IDLE loop scratch * 861 * * 862 * 4 timer. Ticks about every 155 bus clocks. * 863 * 5 current idle loop port number * 864 * 6 PPU Internal Status & BUS RTO timer (low byte) * 865 * 7 the current Interrupt Poll response - high bytes * 866 * * 867 * 8 interrupt mask * 868 * 9 FIFO output enable flags * 869 * A BUS transfer timer scratch (used to store last value of SCRB that * 870 * caused RTO timer to be reset) * 871 * B BUS transfer counter (incremented by routines that do bus transfers) * 872 * (also used for BUS errors) * 873 * * 874 * C FIFO & IBF (CBN) interrupt scratch * 875 * D the number of IBF's to process * 876 * E index for the next empty IBF (input to ring) * 877 * F index for the next available IBF (ring output) * 878 * * 879 ***************************************************************************************************** 880 TITLE.MAC Power-up initialization 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 23 PPU3/REV 25 microcode | Power-up initialization 881 ***************************************************************************************************** 882 * * 883 * INITIALIZE * 884 * * 885 * The PPU performs the following tasks upon initialization. * 886 * - It first waits for the PFW signal to become inactive before continuing. * 887 * - The BUSER signal is then cleared. * 888 * - PPU internal status (SCR6) is cleared. * 889 * - Assert that the self-test hasn't been run yet. * 890 * - Clear data output enables, and enable flags (SCR9). * 891 * - WRU 0 is set up. This is the device type and micro-code level. * 892 * - RFI, INT, all bus control bits, and the interrupt poll response, are * 893 * cleared. * 894 * - The interrupt mask is loaded with an initial value of 11001111. * 895 * - Load the memory fetch interrupt address in the interrupt vector buffer at * 896 * memory location 111. * 897 * - The interrupt address for CBN's is loaded into the interrupt vector buffer * 898 * at memory location 011. * 899 * - The following tasks are performed on each PPU port starting with port 0. * 900 * 1) The port flags are cleared * 901 * 2) Both the initial port status and status2 are set to their initial * 902 * condition * 903 * 3) PBITLOW, and PBITHIGH are set. They are used to mask out three of * 904 * the four ports during either a disable handshake, or a controller * 905 * reset respectively. * 906 * 4) Set up the interrupt masks for each port. * 907 * 5) initialize the port priority scheme with the following order. 3,0,1,2 * 908 * - The idle loop is invoked at this point. * 909 * * 910 ***************************************************************************************************** 911 0000 912 ORG #000 913 000 C2CC002B37C0000090 914 NOP START wait for things to settle 915 0090 916 ORG #90 917 090 42CC002B37C0000091 918 START NOP 091 42CC002B37C0000092 919 NOP 092 C2CC002B37C0000093 920 NOP 093 42CC002B37C0000094 921 NOP 094 C2CC002B37C0000096 922 PFWCHECK 923 STARTSKP 095 C0CBC06AFFC8000096 924 PFWSTILL SCR0 AND LIT PFWNOT SKIP PFWCHECK Wait for PFW to go away 925 >>>>>>>>>> 096 C2CC006D3140000095 926 >PFWCHECK SBST SCR0 PFWSTILL 097 C2CC006B31C0000098 927 > T4 SBRST clear BUS 928 >>>>>>>>>> 098 D8CC006B7140000099 929 ZERO SCR6 clear PPU Internal Status 099 C2CC002B54C000309A 930 LIT INDX1 3 and setup WRU #15 09A C0CC156B706000009B 931 X1 ZERO RAM WRURES4A 09B 40CCF5EB706000009C 932 X1 ONES RAM WRURES4B =>SELF-TEST not run yet 933 09C 40CC000B748000009D 934 ZERO DPOE clear the data output enables 09D 64CC006B714000009E 935 ZERO SCR9 and the data enable flags 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 24 PPU3/REV 25 microcode | Power-up initialization 09E C2CC002B54C000009F 937 RESTART LIT INDX1 0 setup WRU #0 09F C2CC126B50630000A0 938 X1 LIT RAM WRURES1A PPUTYPE PPU Type 0A0 42CC12EB50600190A1 939 X1 LIT RAM WRURES1B LEVEL and Micro-code Level 0A1 40CC000B72800000A2 941 ZERO SBRFI clear RFI, 0A2 C0CC000B71800000A3 942 ZERO SBINT and INT, 0A3 C0CC000B75400000A4 943 ZERO SBCB clear all bus control, 0A4 5CCC006B71400000A5 944 ZERO SCR7 the Interrupt Poll response, 0A5 62CC006B514FFCF0A6 945 LIT SCR8 INITINTS and the interrupt mask 946 0A6 C2CC046B52400600A7 947 LIT IADR IBFIADR TWOWORDS set the memory fetch interrup 948 0A7 F4CC006B71400000A8 949 ZERO SCRD initialize IBF parameters, 0A8 78CC006B71400000A9 950 ZERO SCRE 0A9 FCCC006B71400000AA 951 ZERO SCRF 0AA C2CC066B52400200AB 952 LIT IADR CBNIADR CBNINT and set interrupt address 953 954 0AB D4CC006B71400000AC 955 ZERO SCR5 initialize port zero 0AC 46CC006B51400010AD 956 LIT SCR1 PORTLOW 0AD 4ACC006B51400100AE 957 LIT SCR2 PORTHIGH 0AE CECC006B51400030AF 958 LIT SCR3 NUMPORTS-1 INITLOOP next port index 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 25 PPU3/REV 25 microcode | Power-up initialization 960 0AF D6C8002AD4C00000B0 962 INITLOOP SCR5 INDX1 address the port 0B0 42CC002B55A00000B1 963 X1 LIT DPDIR DIRINP set direction to INPUT 0B1 C2CC002B30E00000B2 964 X1 DPRST reset the Data port 0B2 C0CC026B70600000B3 965 X1,T4 ZERO RAM FLAGS clear the port flags 0B3 C2CC02EB50680800B4 966 X1 LIT RAM PRTST PRTINIT set the initial port status 0B4 C6C800EAD0600000B5 967 X1 SCR1 RAM PBITLOW setup the 'port bit' arrays 0B5 C4C860EAE1600000B6 968 X1 SCR1 ADD RAM SCR1 PBITLOW (shift left 1) 0B6 C2CC002B30E00000B7 969 X1 DPRST (reset the Data port again!) 0B7 4AC8016AD0600000B8 970 X1,T4 SCR2 RAM PBITHIGH 0B8 C8C8616AE9700B97E0 971 X1 SCR2 ADD RAM SCR2 PBITHIGH *+1,PUSH INDX SETPRTIM and 'interrupt mask' array 972 973 BLOCK 4,SETIMIOR 974 >>>>>>>>>> 7E0 42CF01FB50600017F0 975 >SETPRTIM X1 LIT RAM PBITIM PORT0IM POP DIDNTPOP 7E1 42CF01FB50600027F0 976 > X1 LIT RAM PBITIM PORT1IM POP DIDNTPOP 7E2 42CF01FB50600047F0 977 > X1 LIT RAM PBITIM PORT2IM POP DIDNTPOP 7E3 42CF01FB50600087F0 978 > X1 LIT RAM PBITIM PORT3IM POP DIDNTPOP 979 >>>>>>>>>> 980 ENDBLOCK 981 0B9 CEC8006AD0600000BA 982 X1 SCR3 RAM NEXTPORT set the 'next port' array 0BA CCC8606AF1400010BB 983 SCR3 ADD LIT SCR3 1 increment 'next port' 0BB CCC8C06AF1400030BC 984 SCR3 AND LIT SCR3 NUMPORTS-1 and make wrap back to 0 985 0BC 40CC076B70600000BD 986 X1 ZERO RAM HSW1 clear the saved port status 0BD C0CC07EB70600000BE 987 X1 ZERO RAM LSW1 0BE C0CC086B70600000BF 988 X1 ZERO RAM HSW2 0BF C0CC08EB70600000C0 989 X1 ZERO RAM LSW2 990 0C0 40CC096B70600000C1 991 X1 ZERO RAM BCOVERUN set the overrun detector 992 0C1 C0CC0AEB70600000C2 993 X1 ZERO RAM BCNT initialize BCNT 0C2 C0CC176B70600000C3 994 X1 ZERO RAM OLDBCNT initialize old BCNT (=) 0C3 C2CC03EB506FFFF0C4 995 X1 LIT RAM CLKFIX #FFFF deactivate the clock fixer 996 0C4 54CBC06AFFC00030C6 997 SCR5 AND LIT NUMPORTS-1 SKIP NOTDONE done all the ports? 998 SKIPORG 999 >>>>>>>>>> 0C6 D4C8606AF1400010AF 1000 >NOTDONE SCR5 ADD LIT SCR5 1 INITLOOP no, inc index and continue 0C7 E2C8002AD5C00000C8 1001 > SCR8 IMR yes, allow interrupts 1002 >>>>>>>>>> 0C8 D6CC006B51400030C9 1003 LIT SCR5 NUMPORTS-1 IDLE setup the index & go IDLE 1004 TITLE.MAC IDLE loop 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 26 PPU3/REV 25 microcode | IDLE loop 1005 1006 ***************************************************************************************************** 1007 * The IDLE loop * 1008 * The PPU spends all of its time here in the idle loop * 1009 * looking for things to do. All processing routines are * 1010 * called from here except for the interrupt routines which * 1011 * interrupt the idle loop to service the request. * 1012 ***************************************************************************************************** 1013 0C9 D0C8606AF1400018CA 1014 IDLE I SCR4 ADD LIT SCR4 TIMIDLE make the clock tick 0CA 56C8000AD4D00CB8F9 1015 I SCR5 INDX1 *+1,PUSH DOPORT process C/S port 0CB 40CFA26B6FEFBFF8CC 1016 I,X1 LIT IOR RAM FLAGS CM-TIMING SKIP ISTMNG timing this port? 1017 SKIPORG 1018 >>>>>>>>>> 0CC 42CC000B37D00CD95F 1019 >ISTMNG I *+1,PUSH CKTIMOUT yes, check if time-out 0CD C0CFA26B6FEEFFF8CE 1020 > I,X1 LIT IOR RAM FLAGS CM-RGOB SKIP GO-byte received this port? 1021 >>>>>>>>>> 0CE C2CC000B37D00CF96F 1022 > I *+1,PUSH CKFIFOBZ yes, check for FIFO busy 0CF C0CFA26B6FEDFFF8D0 1023 > I,X1 LIT IOR RAM FLAGS CM-REOR SKIP EOR received this port? 1024 >>>>>>>>>> 0D0 C2CC000B37D00D1977 1025 > I *+1,PUSH CKRUNING yes, check if FIFO running 0D1 C2CC0AE361600008D2 1026 > I,X1 RAM SCR0 BCNT get current byte count 1027 >>>>>>>>>> 0D2 40C843EAE1600008D3 1028 > I,X1 SCR0 SUB RAM SCR0 CLKFIX less clock fix value 0D3 40CBA06AFFC7FFF8D4 1029 > I SCR0 IOR LIT #7FFF SKIP check for fixin' needed 1030 >>>>>>>>>> 0D4 40CFC2EB6FE00018D6 1031 > I,X1 LIT AND RAM PRTST DMADIR SKIP CLKDIRT test direction for fixer 0D5 C2CC0068B1600008D9 1032 >CLKLFX I,X1 PTST SCR0 CKFORDPE no clk fix, get data port sta 1033 >>>>>>>>>> 0D6 50C8606AF1400188D8 1034 >CLKDIRT I SCR4 ADD LIT SCR4 TIMBYRD CLKQFX overhead count for read 0D7 50C8606AF14000C8D8 1035 > I SCR4 ADD LIT SCR4 TIMBYWR CLKQFX overhead count for write 1036 >>>>>>>>>> 0D8 C0CC23EB60602008D5 1037 CLKQFX I,X1 LIT RSUB RAM RAM CLKFIX TIMBYTC CLKLFX bytes accounted for 1038 STARTSKP 0D9 C0CBA06AFFCFBFF8DA 1039 CKFORDPE I SCR0 IOR LIT CM-PRTPE SKIP ISDPE port Parity Error? 1040 >>>>>>>>>> 0DA 40CCA2EB60620008DB 1041 >ISDPE I,X1 LIT IOR RAM RAM PRTST DPPE yes, record it 0DB 5CCBA06AFFC00008DD 1042 > I SCR7 IOR LIT 0 SKIP *+2 is interrupt already set? 1043 >>>>>>>>>> 0DC 42CC000B37D00DD9C7 1044 > I *+1,PUSH CKBCINT no, check for INT 0DD 74CBA06AFFC00008DE 1045 > I SCRD IOR LIT 0 SKIP BUS input ready? 1046 >>>>>>>>>> 0DE 7EC8000AD4D00DF9E0 1047 > I SCRF INDX1 *+1,PUSH CKLEGAL yes, go process 0DF 42CC006D31400000E0 1048 > SBST SCR0 CKBUSACT get the S-BUS status 1049 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 27 PPU3/REV 25 microcode | IDLE loop 1051 1052 ***************************************************************************************************** 1053 * This routine checks out bus activity. If SCRB (the bus transfer * 1054 * counter) value is different than the value saved in SCRA the last time * 1055 * the subroutine ran, then the RTO timer is reset. Also, if the byte * 1056 * count (BCNT) for the current port is different than the value copied * 1057 * into OLDBCNT the last time this subroutine ran, then the RTO timer will * 1058 * be reset. If all the BUSACTIV bits (RTO and RFR) are clear, then this * 1059 * subroutine will exit immediately after turning off the RTO timer. If * 1060 * the RTO timer times out, then this subroutine will jump to the proper * 1061 * error routine. If the RTO timer is active, it will be decremented by * 1062 * this subroutine once for each time this subroutine runs until it is * 1063 * either turned off, reset, or timed out. * 1064 ***************************************************************************************************** 1065 1066 >>>>>>>>>> 0E0 EEC8166AD0600008E1 1067 >CKBUSACT I,X1 SCRB RAM TEMP save the current BUS counter 0E1 40CBA06AFFCF5FF8E3 1068 > I SCR0 IOR LIT BUSACTIV SKIP ISBUSACT is the BUS active? 1069 >>>>>>>>>> 0E2 D8C8C06AF14FD008F2 1070 > I SCR6 AND LIT SCR6 #FF00-SOPBTO GETBSTAT no, clear any timer 0E3 58DBC06AFFC02000E4 1071 >ISBUSACT STC SCR6 AND LIT SOPBTO SKIP NOTIMING yes, are we timing yet? 1072 >>>>>>>>>> 0E4 58C8A06AF14020C8EE 1073 >NOTIMING I SCR6 IOR LIT SCR6 SOPBTO+BUSTO NOBUSTO no, start one and exit 0E5 E8EB566AEFE00008E6 1074 > I,TWC,X1 SCRA SUB RAM TEMP #0000 SKIP NEWTRANS new transfer yet? 1075 >>>>>>>>>> 0E6 5A4C006B514000C8F2 1076 >NEWTRANS I LIT SCR6,L BUSTO GETBSTAT yes, reset the time-out 0E7 40CFC2EB6FE80008E9 1077 > I,X1 LIT AND RAM PRTST BTWREC SKIP CKBCACTV is port active ? 1078 >>>>>>>>>> 0E8 D848606AF14FFFF8EC 1079 > I SCR6 ADD LIT SCR6,L -1 CKBUSTO no, check time-out 0E9 46DC0AE361600000C5 1080 >CKBCACTV X1,STC RAM SCR1 BCNT CHKBC yes, what about BC ? 1081 >>>>>>>>>> 1082 STARTSKP 0C5 44EB576AEFE00008EB 1083$ CHKBC I,TWC,X1 SCR1 SUB RAM OLDBCNT #0000 SKIP BCACTIV any BC changes ? 1084 >>>>>>>>>> 0EA D848606AF14FFFF8EC 1085 > I SCR6 ADD LIT SCR6,L -1 CKBUSTO no, check timeout 0EB C6C8176AD0600008E6 1086 >BCACTIV I,X1 SCR1 RAM OLDBCNT NEWTRANS yes, save BC 'state' 1087 >>>>>>>>>> 1088 STARTSKP 0EC D8CBC06AFFC00FF8EE 1089$ CKBUSTO I SCR6 AND LIT #FF SKIP NOBUSTO time-out? 1090 >>>>>>>>>> 0EE 6ACC166361600008F2 1091 >NOBUSTO I,X1 RAM SCRA TEMP GETBSTAT save the current counter 0EF C0CBC06AFFC08000F0 1092 > SCR0 AND LIT RTOIN SKIP yes, RTO? 1093 >>>>>>>>>> 0F0 42CC006D31507FB2F4 1094 > SBST SCR0 RESERR,P RESGODIE Response time-out, go DIE! 0F1 42CC006D31507FA2F3 1095 > SBST SCR0 RTOERR,P RTOGODIE Response time-out, go DIE! 1096 >>>>>>>>>> 1097 0F2 42CC006D31400008F3 1098 GETBSTAT I SBST SCR0 CKFORPFW get the S-BUS status again 1100 STARTSKP 0F3 C0CBC06AFFC80008F4 1101 CKFORPFW I SCR0 AND LIT PFWNOT SKIP ISPFW and check for PFW 1102 >>>>>>>>>> 0F4 58C8A06AF1401008F6 1103 >ISPFW I SCR6 IOR LIT SCR6 SOPPFW *+2 yes, note it 0F5 58CBC06AFFC01008F6 1104 > I SCR6 AND LIT SOPPFW SKIP has it happened already? 1105 >>>>>>>>>> 0F6 56CC006361600008C9 1106 > I,X1 RAM SCR5 NEXTPORT IDLE no, get next port & loop 0F7 42CC006D31400000F8 1107 > SBST SCR0 yes, get status & go die! 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 28 PPU3/REV 25 microcode | IDLE loop 1108 >>>>>>>>>> 0F8 ECCC006B71507FF325 1109 ZERO SCRB PFWWAIT,P SAVEIBF signal no error 1110 TITLE.MAC Command/Status Port processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 29 PPU3/REV 25 microcode | Command/Status Port processor 1111 1112 ***************************************************************************************************** 1113 * The timer in SCR1 has the effect of limiting the number of times * 1114 * this subroutine will loop before returning back to the idle loop. * 1115 * This subroutine is responsible for (amongst other things) timing * 1116 * how long before the CBN interrupts will be turned back on. * 1117 ***************************************************************************************************** 1118 0F9 C6CC006B51400058FA 1119 DOPORT I LIT SCR1 5 counter for fast C/S Port 0FA C2CC0068B1600008FB 1120 DOPORT1 I,X1 PTST SCR0 get the port status 0FB CECC026361600008FC 1121 I,X1 RAM SCR3 FLAGS and the C/S state 0FC 4EC9006ADFC0000FD0 1122 I SCR3 DB4 DOPORTAB then branch 1124 BLOCK 16 1125 >>>>>>>>>> 7D0 40CBC06AFFE20008FE 1126 >DOPORTAB I,X1 SCR0 AND LIT PRTCI SKIP NEWNOTCI got a byte coming in? 7D1 C0CBC06AFFE2000901 1127 > I,X1 SCR0 AND LIT PRTCI SKIP NEWISCI new byte input completed? 7D2 C0CBC06AFFE2000902 1128 > I,X1 SCR0 AND LIT PRTCI SKIP NOTCI next byte starting? 7D3 40CBC06AFFE2000905 1129 > I,X1 SCR0 AND LIT PRTCI SKIP ISCI next byte input completed? 7D4 4ECC006B51400017F1 1130 > LIT SCR3 #01 NOBRANCH 7D5 4ECC006B51400027F1 1131 > LIT SCR3 #02 NOBRANCH 7D6 CECC006B51400037F1 1132 > LIT SCR3 #03 NOBRANCH 7D7 40CBC06AFFE1000906 1133 > I,X1 SCR0 AND LIT PRTFREE SKIP RESBUSY response completed? 7D8 C0CBC06AFFE1000908 1134 > I,X1 SCR0 AND LIT PRTFREE SKIP BUSY ready to output another byte? 7D9 4ECC006B51400047F1 1135 > LIT SCR3 #04 NOBRANCH 7DA CECC006B51400057F1 1136 > LIT SCR3 #05 NOBRANCH 7DB CECC006B51400067F1 1137 > LIT SCR3 #06 NOBRANCH 7DC C2CC002B37C000090F 1138 > I DOPEXIT1 port DEAD 7DD C2CC002B37C000090F 1139 > I DOPEXIT1 port TIMED-OUT 7DE C0CBC06AFFE200090B 1140 > I,X1 SCR0 AND LIT PRTCI SKIP RESISCI response input completed? 7DF 40CBC06AFFE200090C 1141 > I,X1 SCR0 AND LIT PRTCI SKIP RESNOTCI response coming in? 1142 >>>>>>>>>> 1143 ENDBLOCK 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 30 PPU3/REV 25 microcode | Command/Status Port processor 1145 1146 ***************************************************************************************************** 1147 * * 1148 * Input States * 1149 * * 1150 ***************************************************************************************************** 1152 SKIPORG 1153 >>>>>>>>>> 0FE C2CC002B37C000090F 1154 >NEWNOTCI I DOPEXIT1 not yet, wait 0FF 42CC002B3020000111 1155 > X1 CSSFO NXTSTATE set FLAG OUT & inc state 1156 >>>>>>>>>> 1158 >>>>>>>>>> 100 C4CB606AF94FFFF90E 1159 > I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wait 101 C0CC826B6060010912 1160 >NEWISCI I,X1 LIT XOR RAM RAM FLAGS #10 CSINPRDY completed, go process data 1161 >>>>>>>>>> 1163 >>>>>>>>>> 102 C4CB606AF94FFFF90E 1164 >NOTCI I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not yet, wait 103 42CC002B3020000111 1165 > X1 CSSFO NXTSTATE set FLAG OUT & inc state 1166 >>>>>>>>>> 1168 >>>>>>>>>> 104 C4CB606AF94FFFF90E 1169 > I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wait 105 C0CC826B6060010924 1170 >ISCI I,X1 LIT XOR RAM RAM FLAGS #10 INPISRDY completed, go process data 1171 >>>>>>>>>> 1173 >>>>>>>>>> 106 C4CB606AF94FFFF90E 1174 >RESBUSY I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wait 107 42CC002B37C0000929 1175 > I ENDINP completed, go clean up 1176 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 31 PPU3/REV 25 microcode | Command/Status Port processor 1178 1179 ***************************************************************************************************** 1180 * * 1181 * Output States * 1182 * * 1183 ***************************************************************************************************** 1185 >>>>>>>>>> 108 C4CB606AF94FFFF90E 1186 >BUSY I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wait 109 42CC002B37C0000949 1187 > I CKCREAD controller read or write? 1188 >>>>>>>>>> 1190 >>>>>>>>>> 10A C4CB606AF94FFFF90E 1191 > I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wait 10B 42CC002B37C0000951 1192 >RESISCI I ENDOUT completed, go check response 1193 >>>>>>>>>> 1195 >>>>>>>>>> 10C C4CB606AF94FFFF90E 1196 >RESNOTCI I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not yet, wait 10D 42CC002B3020000111 1197 > X1 CSSFO NXTSTATE set FLAG OUT & inc state 1198 >>>>>>>>>> 1200 >>>>>>>>>> 10E 62C8002AD5C00000FA 1201 >DOPEXIT SCR8 IMR DOPORT1 update CBN int mask-try again 10F 62C8002AD5C0000110 1202 >DOPEXIT1 SCR8 IMR C/S port too slow - try anoth 1203 >>>>>>>>>> 110 42CF001B37C00007F0 1204 POP DIDNTPOP insure no ints after IMR chan 1205 111 40CC826B60600108F9 1206 NXTSTATE I,X1 LIT XOR RAM RAM FLAGS #10 DOPORT increment C/S state & try aga 1207 TITLE.MAC Command/Status Input processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 32 PPU3/REV 25 microcode | Command/Status Input processor 1208 1209 ***************************************************************************************************** 1210 * A new byte is available on the CS path. Read it in * 1211 * and set up the state to indicate that we are inputting. * 1212 ***************************************************************************************************** 1213 112 C2CC00693160000113 1214 CSINPRDY X1 CSIN SCR0 read byte into scratch 113 C1C8C06AF1600FF8ED 1215 I,X1 SCR0 AND,X LIT SCR0 #FF CKTIMER 1216 STARTSKP 0ED C0CFC26B6FE0400914 1217$ CKTIMER I,X1 LIT AND RAM FLAGS TIMING SKIP TIMEROFF Now timing? 1218 >>>>>>>>>> 114 50C864EAF06053C915 1219 >TIMEROFF I,X1 SCR4 ADD LIT RAM CNTDOWN TIMECNST no, set one up 115 408CA26B6060520916 1220 > I,X1 LIT IOR RAM RAM,H FLAGS STARTINP set C/S state and DOINGINP 1221 >>>>>>>>>> 116 424C026B5060520917 1222 I,X1 LIT RAM,L FLAGS STARTINP 117 41C8B66AF060000918 1223 I,X1 SCR0 IOR,X LIT RAM TEMP 0 & check for legal 1st byte 118 CECC16636160000919 1224 I,X1 RAM SCR3 TEMP 119 D0C8606AF14000491A 1225 I SCR4 ADD LIT SCR4 TIMECSIN bump clock for overhead 11A CEC9006ADFC0000FC0 1226 I SCR3 DB4 CK1STBYT 1228 BLOCK 16 1229 >>>>>>>>>> 7C0 42CC002B37C0000920 1230 >CK1STBYT I SENDNAK illegal: send NAK 7C1 42CC002B37C0000920 1231 > I SENDNAK illegal: send NAK 7C2 42CC002B37C0000920 1232 > I SENDNAK illegal: send NAK 7C3 4088646AF06010091F 1233 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: load status two 7C4 42CC002B37C0000920 1234 > I SENDNAK illegal: send NAK 7C5 C088646AF06010091B 1235 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INTREQ legal: interrupt request 7C6 4088646AF06010091F 1236 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: start data transfer 7C7 42CC002B37C0000920 1237 > I SENDNAK illegal: send NAK 7C8 42CC002B37C0000920 1238 > I SENDNAK illegal: send NAK 7C9 4088646AF06010091F 1239 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: end of record 7CA 4088646AF06010091F 1240 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: response to us 7CB 42CC002B37C0000920 1241 > I SENDNAK illegal: send NAK 7CC 4088646AF06010091F 1242 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: load status one 7CD 42CC002B37C0000920 1243 > I SENDNAK illegal: send NAK 7CE 42CC002B37C0000920 1244 > I SENDNAK illegal: send NAK 7CF 42CC002B37C0000920 1245 > I SENDNAK illegal: send NAK 1246 >>>>>>>>>> 1247 ENDBLOCK 1248 11B 4ACC0763616000091C 1249 INTREQ I,X1 RAM SCR2 HSW1 fix up for INTR (no status) 11C 4AC805EAD06000091D 1250 I,X1 SCR2 RAM HWORD 11D 4ACC07E3616000091E 1251 I,X1 RAM SCR2 LSW1 11E 4AC8066AD06000091F 1252 I,X1 SCR2 RAM LWORD 11F 4148C46AF06FF008F9 1253 INPISLEG I,X1 SCR0 AND,X LIT RAM,L TYPECKSM #FF00 DOPORT set count & start checksum 1254 1255 SKIPORG 1256 >>>>>>>>>> 120 424C046B50600F8922 1257 >SENDNAK I,X1 LIT RAM,L TYPECKSM NAK SACKNAK 121 424C046B506000E922 1258 > I,X1 LIT RAM,L TYPECKSM ACK SACKNAK 1259 >>>>>>>>>> 1260 122 C0CCC40B60A00FF123 1261 SACKNAK X1 LIT AND RAM CSOUT TYPECKSM #FF send response, 123 C0CCA26B60600708F9 1262 I,X1 LIT IOR RAM RAM FLAGS SENDRESP DOPORT change I/O state & return 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 33 PPU3/REV 25 microcode | Command/Status Input processor 1264 1265 ***************************************************************************************************** 1266 * An input character has become available on the C/S path. * 1267 ***************************************************************************************************** 1268 124 C2CC00693160000125 1269 INPISRDY X1 CSIN SCR0 read input byte, 125 C048846AE060000926 1270 I,X1 SCR0 XOR RAM RAM,L TYPECKSM fix checksum, 126 408C646B606FF00927 1271 I,X1 LIT ADD RAM RAM,H TYPECKSM #FF00 decrement byte count & 127 CDCCA46B6160000928 1272 I,X1 LIT IOR,X RAM SCR3 TYPECKSM IBIOR*2^8 branch 128 4ECA006ADFC0000FB0 1273 I SCR3 DB0 CSIBYTE 1275 BLOCK 8,IBIOR 1276 >>>>>>>>>> 7B0 C0CFC46B6FE00FF920 1277 >CSIBYTE I,X1 LIT AND RAM TYPECKSM #FF SKIP SENDNAK done, checksum OK? 7B1 4248066AD0600008F9 1278 > I,X1 SCR0 RAM,L LWORD DOPORT store 4th byte & exit 7B2 C188C66AF06FFFF8F9 1279 > I,X1 SCR0 AND,X LIT RAM,H LWORD #FFFF DOPORT store 3rd byte & exit 7B3 C24805EAD0600008F9 1280 > I,X1 SCR0 RAM,L HWORD DOPORT store 2nd byte & exit 7B4 4188C5EAF06FFFF8F9 1281 > I,X1 SCR0 AND,X LIT RAM,H HWORD #FFFF DOPORT store 1st byte & exit 7B5 4ECC006B51400077F1 1282 > LIT SCR3 #07 NOBRANCH 7B6 4ECC006B51400087F1 1283 > LIT SCR3 #08 NOBRANCH 7B7 CECC006B51400097F1 1284 > LIT SCR3 #09 NOBRANCH 1285 >>>>>>>>>> 1286 ENDBLOCK 129 40CCC26B606FC0092A 1288 ENDINP I,X1 LIT AND RAM RAM FLAGS CLRFLAGS signal no activity this port 12A 40CCC46B61600FF92B 1289 I,X1 LIT AND RAM SCR0 TYPECKSM #FF get the response we sent 12B 40C8766AF06FFF28FD 1290 I,X1 SCR0 ADD LIT RAM TEMP -ACK CKACKNAK & check it 1291 1292 STARTSKP 0FD 40CFB66B6FE000092D 1293$ CKACKNAK I,X1 LIT IOR RAM TEMP 0 SKIP CKWAIT did we send ACK or NAK? 1294 >>>>>>>>>> 12C CDCCC46B616FF00930 1295 > I,X1 LIT AND,X RAM SCR3 TYPECKSM #FF00 GOCKRESP ACK, good transfer-process 12D C0CFC26B6FE080092E 1296 >CKWAIT I,X1 LIT AND RAM FLAGS WAITING SKIP NOWAIT NAK, bad transfer-waiting? 1297 >>>>>>>>>> 12E 40CFC25B606FBFFFF0 1298 >NOWAIT IP,X1 LIT AND RAM RAM FLAGS CM-TIMING POP DIDNTPOP no, clear time-out & exit 12F 42CF005B37C0000FF0 1299 > IP POP DIDNTPOP yes, just exit 1300 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 34 PPU3/REV 25 microcode | Command/Status Input processor 1302 130 CEC9006ADFD012DFA0 1303 GOCKRESP I SCR3 CKWAIT,P DB4 CKRESP ACK, good transfer-process 1305 BLOCK 16 1306 >>>>>>>>>> 7A0 CECC006B514000A7F1 1307 >CKRESP LIT SCR3 #0A NOBRANCH 7A1 4ECC006B514000B7F1 1308 > LIT SCR3 #0B NOBRANCH 7A2 CECC006B514000C7F1 1309 > LIT SCR3 #0C NOBRANCH 7A3 C2CC05E36160000934 1310 > I,X1 RAM SCR0 HWORD RLSW2 load status word #2 7A4 4ECC006B514000D7F1 1311 > LIT SCR3 #0D NOBRANCH 7A5 C0CCA2EB6060008FAC 1312 > I,X1 LIT IOR RAM RAM PRTST CTLRINTR LDSTATUS controller int, load status 7A6 40CFA2EB6FE7FFB938 1313 > I,X1 LIT IOR RAM PRTST BTWRECOE SKIP ISBTWREC GO-byte, OK? 7A7 4ECC006B514000E7F1 1314 > LIT SCR3 #0E NOBRANCH 7A8 CECC006B514000F7F1 1315 > LIT SCR3 #0F NOBRANCH 7A9 40CFA2EB6FE7FFF93C 1316 > I,X1 LIT IOR RAM PRTST CM-BTWREC SKIP NOTBTREC EOR, OK? 7AA C0CFC26B6FE0800944 1317 > I,X1 LIT AND RAM FLAGS WAITING SKIP RESPONSE response, waiting for one? 7AB 4ECC006B51400107F1 1318 > LIT SCR3 #10 NOBRANCH 7AC C2CC05E36160000931 1319 >LDSTATUS I,X1 RAM SCR0 HWORD RLSW1 load status word #1 7AD CECC006B51400117F1 1320 > LIT SCR3 #11 NOBRANCH 7AE CECC006B51400127F1 1321 > LIT SCR3 #12 NOBRANCH 7AF 4ECC006B51400137F1 1322 > LIT SCR3 #13 NOBRANCH 1323 >>>>>>>>>> 1324 ENDBLOCK 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 35 PPU3/REV 25 microcode | Command/Status Input processor 1326 131 42C8076AD060000932 1327 RLSW1 I,X1 SCR0 RAM HSW1 132 C2CC06636160000933 1328 I,X1 RAM SCR0 LWORD 133 42CB07DAD060000FF0 1329 I,X1 SCR0 RAM LSW1 POP DIDNTPOP 134 C2C8086AD060000935 1331 RLSW2 I,X1 SCR0 RAM HSW2 135 C2CC06636160000936 1332 I,X1 RAM SCR0 LWORD 136 42CB08DAD060000FF0 1333 I,X1 SCR0 RAM LSW2 POP DIDNTPOP 1335 SKIPORG 1336 >>>>>>>>>> 138 40CFA2DB6060402FF0 1337 >ISBTWREC I,X1 LIT IOR RAM RAM PRTST CONFUSED POP DIDNTPOP no, cockpit error 139 40CFC2EB6FE000193A 1338 > I,X1 LIT AND RAM PRTST DMADIR SKIP yes, is read or write? 1339 >>>>>>>>>> 13A 40CFA2DB6060402FF0 1340 > I,X1 LIT IOR RAM RAM PRTST CONFUSED POP DIDNTPOP read, cockpit error 13B 40CFA25B6061000FF0 1341 > I,X1 LIT IOR RAM RAM FLAGS RGOB POP DIDNTPOP set for processing & return 1342 >>>>>>>>>> 1344 SKIPORG 1345 >>>>>>>>>> 13C 40CFA2DB6060402FF0 1346 >NOTBTREC I,X1 LIT IOR RAM RAM PRTST CONFUSED POP DIDNTPOP no, cockpit error 13D C0CFC2EB6FE000193E 1347 > I,X1 LIT AND RAM PRTST DMADIR SKIP ISEOREAD OK, end of read? 1348 >>>>>>>>>> 13E 40CCA2EB6068000943 1349 >ISEOREAD I,X1 LIT IOR RAM RAM PRTST BTWREC SETREOR yes, set status 13F C0CFC2EB6FE0080940 1350 > I,X1 LIT AND RAM PRTST DMANBZ SKIP STILLBZ write, is DMA still busy? 1351 >>>>>>>>>> 140 C0CCA2EB6068082942 1352 >STILLBZ I,X1 LIT IOR RAM RAM PRTST ENDWRITE *+2 yes, DMA was busy 141 C0CCA2EB6068000942 1353 > I,X1 LIT IOR RAM RAM PRTST BTWREC no, DMA wasn't busy 1354 >>>>>>>>>> 142 40CCC2EB606FFFBA67 1355 I,X1 LIT AND RAM RAM PRTST CM-DMAOE ABORTPRT clear output enable status 143 40CFA25B6062000FF0 1357 SETREOR I,X1 LIT IOR RAM RAM FLAGS REOR POP DIDNTPOP set for EOR processing 1359 SKIPORG 1360 >>>>>>>>>> 144 42CF005B37C0000FF0 1361 >RESPONSE IP POP DIDNTPOP no, ignore response 145 42CC05E361701469EF 1362 > I,X1 RAM SCR0 HWORD *+1,PUSH WTFORBUS yes, wait for BUS & 1363 >>>>>>>>>> 146 42CC06036460000147 1364 X1 RAM SBLC LWORD respond to CPU 147 C2CC06A36560000148 1365 X1 RAM SBCB RESPTO 148 C0CFC27B606F3FF7F0 1366 X1 LIT AND RAM RAM FLAGS CLRWAIT POP DIDNTPOP signal not waiting & exit 1367 TITLE.MAC Command/Status output 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 36 PPU3/REV 25 microcode | Command/Status output 1368 1369 STARTSKP 149 40CFC46B6FE800094A 1370 CKCREAD I,X1 LIT AND RAM TYPECKSM CRDTEST SKIP NOTCREAD controller read or write? 1371 >>>>>>>>>> 14A CDCCA46B616080094C 1372 >NOTCREAD I,X1 LIT IOR,X RAM SCR3 TYPECKSM CWIOR*2^8 *+2 Write 14B 4DCCA46B616040094D 1373 > I,X1 LIT IOR,X RAM SCR3 TYPECKSM CRIOR*2^8 *+2 Read 1374 >>>>>>>>>> 14C CECA006ADFC0000FB8 1375 I SCR3 DB0 CWRTAB 14D CECA006ADFC0000FE4 1376 I SCR3 DB0 CRDTAB 1378 BLOCK 8,CWIOR 1379 >>>>>>>>>> 7B8 C0CCC56B61600FF94E 1380 >CWRTAB I,X1 LIT AND RAM SCR0 ADDRESS #FF INCSTATE transmit address 7B9 C1CCC5EB616FF0094E 1381 > I,X1 LIT AND,X RAM SCR0 HWORD #FF00 INCSTATE transmit byte 0 7BA 40CCC5EB61600FF94E 1382 > I,X1 LIT AND RAM SCR0 HWORD #FF INCSTATE transmit byte 1 7BB 41CCC66B616FF0094E 1383 > I,X1 LIT AND,X RAM SCR0 LWORD #FF00 INCSTATE transmit byte 2 7BC C0CCC66B61600FF94E 1384 > I,X1 LIT AND RAM SCR0 LWORD #FF INCSTATE transmit byte 3 7BD C0CC006B714000094E 1385 > I ZERO SCR0 INCSTATE transmit zero 7BE 40CCC46B61600FF94E 1386 > I,X1 LIT AND RAM SCR0 TYPECKSM #FF INCSTATE transmit checksum 7BF 40CCA26B60600F08F9 1387 > I,X1 LIT IOR RAM RAM FLAGS RECVRESP DOPORT change state to accept respon 1388 >>>>>>>>>> 1390 BLOCK 4,CRIOR 1391 >>>>>>>>>> 7E4 C0CCC56B61600FF94E 1392 >CRDTAB I,X1 LIT AND RAM SCR0 ADDRESS #FF INCSTATE transmit address 7E5 C0CC006B714000094E 1393 > I ZERO SCR0 INCSTATE transmit zero 7E6 40CCC46B61600FF94E 1394 > I,X1 LIT AND RAM SCR0 TYPECKSM #FF INCSTATE transmit checksum 7E7 40CCA26B60600F08F9 1395 > I,X1 LIT IOR RAM RAM FLAGS RECVRESP DOPORT change state to accept respon 1396 >>>>>>>>>> 1397 ENDBLOCK 14E C2C8002AD0A000014F 1399 INCSTATE X1 SCR0 CSOUT send byte, 14F 4048846AE060000950 1400 I,X1 SCR0 XOR RAM RAM,L TYPECKSM fix checksum, 150 408C646B60601008F9 1401 I,X1 LIT ADD RAM RAM,H TYPECKSM #100 DOPORT inc output state & return 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 37 PPU3/REV 25 microcode | Command/Status output 1403 151 C2CC00693160000152 1404 ENDOUT X1 CSIN SCR0 get response 152 C0C8C06AF1600FF953 1405 I,X1 SCR0 AND LIT SCR0 #FF (need to hold X1 for 1 inst.) 153 C0C8766AF06FFF2937 1406 I,X1 SCR0 ADD LIT RAM TEMP -ACK CKWASNAK & check for ACK 1407 STARTSKP 137 40CFB66B6FE0000955 1408$ CKWASNAK I,X1 LIT IOR RAM TEMP 0 SKIP WASNAK ACK or NAK? 1409 >>>>>>>>>> 154 C0CCC26B606FC0092D 1410 > I,X1 LIT AND RAM RAM FLAGS CLRFLAGS CKWAIT ACK, clear activity this port 155 C0CFA26B6FEFFF0957 1411 >WASNAK I,X1 LIT IOR RAM FLAGS #FFF0 SKIP YESRETRY NAK, any retries left? 1412 >>>>>>>>>> 156 C2CC0263616000095E 1413 > I,X1 RAM SCR0 FLAGS SETPDEAD no, port DEAD- save FLAGS 157 40CFC46B6FE8000958 1414 >YESRETRY I,X1 LIT AND RAM TYPECKSM CRDTEST SKIP ISWRITE yes, read? 1415 >>>>>>>>>> 158 C2CC002B50A009615A 1416 >ISWRITE X1 LIT CSOUT CTLRWR *+2 no, restart write 159 C2CC002B50A006215B 1417 > X1 LIT CSOUT CTLRRD *+2 yes, restart read 1418 >>>>>>>>>> 15A 42CC046B506006995C 1419 I,X1 LIT RAM TYPECKSM CWRSTART *+2 15B 42CC046B506809D95C 1420 I,X1 LIT RAM TYPECKSM CRDSTART 15C C0CCC26B616000F95D 1421 I,X1 LIT AND RAM SCR0 FLAGS #F decrement the retry count & 15D C04B625AF06007FFF0 1422 I,X1 SCR0 ADD LIT RAM,L FLAGS RESTRDWR-1 POP DIDNTPOP setup the handshake state 1423 15E 42CC026B50640C0967 1424 SETPDEAD I,X1 LIT RAM FLAGS SETDEAD CKINPTO set DEAD & check for WAITING 1425 TITLE.MAC Timer processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 38 PPU3/REV 25 microcode | Timer processor 1426 1427 ***************************************************************************************************** 1428 * * 1429 * Check Time Out routine. * 1430 * This routine checks the timeout count for the indexed port. * 1431 * We set up to return abnormal data if the bus timed out, except for * 1432 * the device ID entry which just returns a zero to indicate no * 1433 * device. * 1434 * * 1435 ***************************************************************************************************** 1436 15F D0C8966AF06FFFF960 1437 CKTIMOUT I,X1 SCR4 XOR LIT RAM TEMP -1 make one comp of current time 160 C2CC16636160000961 1438 I,X1 RAM SCR0 TEMP and copy to scratch register 161 C0C864EAE160000962 1439 I,X1 SCR0 ADD RAM SCR0 CNTDOWN compare to time out value 162 40CBC06AFFC8000964 1440 I SCR0 AND LIT #8000 SKIP NOTIMOUT now check sign of result 1441 SKIPORG 1442 >>>>>>>>>> 164 42CF005B37C0000FF0 1443 >NOTIMOUT IP POP DIDNTPOP okay, return 165 42CC02636160000966 1444 > I,X1 RAM SCR0 FLAGS timed out, save flags, 1445 >>>>>>>>>> 166 42CC026B506C0D0967 1446 > I,X1 LIT RAM FLAGS SETIMED clear I/O & set timed-out 167 40CBC06AFFC0800968 1447 >CKINPTO I SCR0 AND LIT WAITING SKIP NOTINPTO were we doing a read? 1448 >>>>>>>>>> 168 42CF005B37C0000FF0 1449 >NOTINPTO IP POP DIDNTPOP no, return 169 40CC006B715016A9EF 1450 > I ZERO SCR0 *+1,PUSH WTFORBUS yes, clear response & 1451 >>>>>>>>>> 16A C0CC006B744000016B 1452 > ZERO SBLC send to the CPU 16B 40CFA56B6FE000016C 1453 > X1 LIT IOR RAM ADDRESS 0 SKIP PPU's "Read Device ID"? 1454 >>>>>>>>>> 16C C0CC868B656001016E 1455 > X1 LIT XOR RAM SBCB RESPTO ADATAXOR RTODELAY no, send Abnormal Data 16D 42CC06A3656000016E 1456 > X1 RAM SBCB RESPTO yes, send Good Data 1457 >>>>>>>>>> 16E 42CF001B37C00007F0 1458 RTODELAY POP DIDNTPOP wait for RTO and exit 1459 TITLE.MAC GO-byte processing 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 39 PPU3/REV 25 microcode | GO-byte processing 1460 1461 ***************************************************************************************************** 1462 * * 1463 * Check go-byte processing * 1464 * This routine looks to see if the FIFO is busy. This code * 1465 * looks like we wait until the FIFO is full then start the * 1466 * data going out to the controller. * 1467 * * 1468 ***************************************************************************************************** 1469 1470 STARTSKP 16F C0CFA2EB6FEFF7F970 1471 CKFIFOBZ I,X1 LIT IOR RAM PRTST CM-DMANBZ SKIP FIFONBZ is FIFO busy? 1472 >>>>>>>>>> 170 40CCC26B606EFFF974 1473 >FIFONBZ I,X1 LIT AND RAM RAM FLAGS CM-RGOB LETGO no, let output go 171 C2CC0068B160000963 1474 > I,X1 PTST SCR0 CKFULL yes, get the data port status 1475 >>>>>>>>>> 1476 STARTSKP 163 C0CBC06AFFC0800972 1477$ CKFULL I SCR0 AND LIT PRTINT SKIP NOTFULL FIFO full yet? 1478 >>>>>>>>>> 172 42CF005B37C0000FF0 1479 >NOTFULL IP POP DIDNTPOP no, return 173 40CCC26B606EFFF974 1480 > I,X1 LIT AND RAM RAM FLAGS CM-RGOB LETGO yes, let output go 1481 >>>>>>>>>> 1482 174 40CCA2EB6060004975 1483 LETGO I,X1 LIT IOR RAM RAM PRTST DMAOE set output enabled status 175 64C8A0EAE160000976 1484 I,X1 SCR9 IOR RAM SCR9 PBITLOW enable data output 176 66CB001AD4800007F0 1485 SCR9 DPOE POP DIDNTPOP & return 1486 TITLE.MAC End-Of-Record processing 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 40 PPU3/REV 25 microcode | End-Of-Record processing 1487 1488 ***************************************************************************************************** 1489 * The PPU comes here from the idle loop after an * 1490 * End-Of-Record character is received from the port currently * 1491 * being checked by the idle loop. The REOR (received end of * 1492 * record) flag is only set for a port doing input (from * 1493 * controller to memory). * 1494 ***************************************************************************************************** 1495 1496 STARTSKP 177 40CFC2EB6FE0080978 1497 CKRUNING I,X1 LIT AND RAM PRTST DMANBZ SKIP ISRUNING is FIFO running? 1498 >>>>>>>>>> 178 42CC0068B16000097C 1499 >ISRUNING I,X1 PTST SCR0 CKGOING yes, get the port status 179 40CFC2EB6FE004097B 1500 > I,X1 LIT AND RAM PRTST BCNRDY SKIP *+2 no, waiting for BCNT? 1501 >>>>>>>>>> 17A 42CF005B37C0000FF0 1502 > IP POP DIDNTPOP yes,exit to wait for it 17B C4CC6B6B6168000983 1503 > I,X1 LIT ADD RAM SCR1 LAST -LASTBIT CUCKDONE no,do cleanup 1504 >>>>>>>>>> 1505 STARTSKP 17C C0CBC06AFFC080097E 1506$ CKGOING I SCR0 AND LIT PRTINT SKIP ISGOING still interrupting? 1507 >>>>>>>>>> 17E 42CF005B37C0000FF0 1508 >ISGOING IP POP DIDNTPOP yes, wait till it finishes 17F E0C8A1EAE160000180 1509 > X1 SCR8 IOR RAM SCR8 PBITIM no,disallow interrupts 1510 >>>>>>>>>> 180 E2C8002AD5C0000181 1511 SCR8 IMR 1512 ***************************************************************************************************** 1513 * If we get to here, the byte count was not exhausted, * 1514 * otherwise the FIFO input processor would have set DMANBZ (in * 1515 * PRTST) and turned off the interrupts itself. * 1516 * If we get to here, the transfer is over (EOR received) * 1517 * and there is less than a whole 32 bit word in the FIFO. * 1518 ***************************************************************************************************** 181 40CC6AEB606FFFC182 1519 X1 LIT ADD RAM RAM BCNT -4 make sure byte count 182 40CC6B6B6060004185 1520 X1 LIT ADD RAM RAM LAST 4 CUNDONE residue >=4 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 41 PPU3/REV 25 microcode | End-Of-Record processing 1522 1523 ***************************************************************************************************** 1524 * The PPU gets here when End-Of-Record has been received on * 1525 * this port AND there is no byte count overrun on this port AND * 1526 * FIFO not running status (DMANBZ) has been set in PRTST (i.e. * 1527 * bit 7 = 1). * 1528 ***************************************************************************************************** 1529 1530 STARTSKP 183 44CBA06AFFC0000985 1531 CUCKDONE I SCR1 IOR LIT 0 SKIP CUNDONE already done? 1532 >>>>>>>>>> 184 40CCA2EB60600B29C5 1533 > I,X1 LIT IOR RAM RAM PRTST LASTBC CUCKEXT yes, check for extra input 185 C2CC0068B16000097D 1534 >CUNDONE I,X1 PTST SCR0 CUCKMT no, get the port status 1535 >>>>>>>>>> 1536 STARTSKP 17D 40CBA06AFFCFCFF987 1537$ CUCKMT I SCR0 IOR LIT PRTEMPTY SKIP CUNOTMT and check for FIFO empty? 1538 >>>>>>>>>> 186 40CCA2EB60600829C9 1539 > I,X1 LIT IOR RAM RAM PRTST EORINTR CUEXIT yes,set interrupt&exit 187 44CCCA6B6160F00988 1540 >CUNOTMT I,X1 LIT AND RAM SCR1 SLOT #0F00 not MT,need to fetch 1541 >>>>>>>>>> 188 44C8A06AF148029989 1542 I SCR1 IOR LIT SCR1 (#80FB AND READBITS) SCR1<-SBCB read command 189 C0CCABEB616200098A 1543 I,X1 LIT IOR RAM SCR0 HADDR READ1W SCR0 will go into SBHC 18A C2CC000B37D018B9EF 1544 I CUNOTMTA,P WTFORBUS wait for bus free 18B 82CC0C23646000018C 1545 CUNOTMTA X1,P RAM SBLC LADDR 18C C6C8002AD56000018D 1546 X1 SCR1 SBCB initiate transfer 18D 42CC046B524001018E 1547 LIT IADR IBFIADR EORIBF set IBF intrpt addr 18E 4CCCAB6B616000018F 1548 X1 LIT IOR RAM SCR3 LAST EORIOR set up for branch 18F 4ECA006ADFC0000790 1549 SCR3 DB0 EORBLOCK on bytes remaining 1551 ***************************************************************************************************** 1552 * At this point, SCR0 <> 0 (until bus transfer completes), * 1553 * SCR1 and SCR2 are the high and low input data buffer, EORTIMER * 1554 * is the bus timer, SCR3 will be port status. The >3 byte * 1555 * branches are used when "EOR is received and no more input" * 1556 * before the byte count is exhausted (i.e. we ran through * 1557 * address ISGOING+1). * 1558 ***************************************************************************************************** 1559 1560 BLOCK 8,EORIOR 1561 >>>>>>>>>> 790 4ECC006B51400167F1 1562 >EORBLOCK LIT SCR3 #16 NOBRANCH 0 bytes,bad branch 791 C2CC036B506007D990 1563 > I,X1 LIT RAM EORTIMER BUSTO2 EOR1MORE 1 bytes,set up timer 792 C2CC036B506007D999 1564 > I,X1 LIT RAM EORTIMER BUSTO2 EOR2MORE 2 bytes,set up timer 793 42CC036B506007D9A7 1565 > I,X1 LIT RAM EORTIMER BUSTO2 EOR3MORE 3 bytes,set up timer 794 42CC036B506007D9A7 1566 > I,X1 LIT RAM EORTIMER BUSTO2 EOR3MORE >3 bytes,set up timer 795 42CC036B506007D9A7 1567 > I,X1 LIT RAM EORTIMER BUSTO2 EOR3MORE >3 bytes,set up timer 796 42CC036B506007D9A7 1568 > I,X1 LIT RAM EORTIMER BUSTO2 EOR3MORE >3 bytes,set up timer 797 42CC036B506007D9A7 1569 > I,X1 LIT RAM EORTIMER BUSTO2 EOR3MORE >3 bytes,set up timer 1570 >>>>>>>>>> 1571 ENDBLOCK 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 42 PPU3/REV 25 microcode | End-Of-Record processing 1573 190 4ECC0068B160000991 1574 EOR1MORE I,X1 PTST SCR3 EOR1M1 get port status 1575 STARTSKP 191 4CCBA06AFFCFEFF992 1576 EOR1M1 I SCR3 IOR LIT CM-PRTLOW SKIP EOR1M2 at least 2 bytes? 1577 >>>>>>>>>> 192 C0CCA2EB6064000993 1578 >EOR1M2 I,X1 LIT IOR RAM RAM PRTST EXTRA >=2 bytes,set extra input 193 C0CF636B686FFFF995 1579 >EOR1M3 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 1580 >>>>>>>>>> 194 42CC006D31507FB2F4 1581 > SBST SCR0 RESERR,P RESGODIE yes, go die 195 40CBA06AFFC0000996 1582 >EOR1M4 I,T4 SCR0 IOR LIT #0 SKIP EOR1M5 no,input yet? 1583 >>>>>>>>>> 196 42CC006B37C0000993 1584 >EOR1M5 I,T4 EOR1M3 no,continue timing 197 42CC166B5060001998 1585 > I,X1 LIT RAM TEMP 1 indicate 1 byte 1586 >>>>>>>>>> 198 468C006871600001B8 1587 X1 DPIN SCR1,H CUNOTMT3 get byte,go do write 199 CECC0068B16000099A 1589 EOR2MORE I,X1 PTST SCR3 EOR2M1 get port status 1590 STARTSKP 19A 4CCBA06AFFCFEFF99D 1591$ EOR2M1 I SCR3 IOR LIT CM-PRTLOW SKIP EOR2M2 at least 2 bytes? 1592 >>>>>>>>>> 19C C0CF636B686FFFF995 1593 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 19D C2CC1668706000019E 1594 >EOR2M2 X1 DPIN RAM TEMP >=2 bytes,read 2 bytes 1595 >>>>>>>>>> 19E 42CC002B37E000099F 1596 I,X1 wait 1 instr b4 PTST 19F CECC0068B16000019B 1597 X1 PTST SCR3 EOR2M7 get port status 1598 STARTSKP 19B 4CCBA06AFFCFCFF9A0 1599$ EOR2M7 I SCR3 IOR LIT PRTEMPTY SKIP EOR2M8 FIFO empty? 1600 >>>>>>>>>> 1A0 40CCA2EB60640009A1 1601 >EOR2M8 I,X1 LIT IOR RAM RAM PRTST EXTRA no,set extra input 1A1 C0CF636B686FFFF9A3 1602 >EOR2M3 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR2M4 yes,time out? 1603 >>>>>>>>>> 1A2 42CC006D31507FB2F4 1604 > SBST SCR0 RESERR,P RESGODIE yes, go die 1A3 C0CBA06AFFC00009A4 1605 >EOR2M4 I,T4 SCR0 IOR LIT #0 SKIP EOR2M5 no,input yet? 1606 >>>>>>>>>> 1A4 C2CC006B37C00009A1 1607 >EOR2M5 I,T4 EOR2M3 no,continue timing 1A5 C6CC166361600009A6 1608 > I,X1 RAM SCR1 TEMP yes,2 bytes for output 1609 >>>>>>>>>> 1A6 C2CC166B50600029B8 1610 I,X1 LIT RAM TEMP 2 CUNOTMT3 indicate 2 byte,go do write 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 43 PPU3/REV 25 microcode | End-Of-Record processing 1612 1A7 4ECC0068B1600009A8 1613 EOR3MORE I,X1 PTST SCR3 EOR3M1 get port status 1614 STARTSKP 1A8 4CCBA06AFFCFEFF9AB 1615$ EOR3M1 I SCR3 IOR LIT CM-PRTLOW SKIP EOR3M2 at least 2 bytes? 1616 >>>>>>>>>> 1AA C0CF636B686FFFF995 1617 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 1AB 42CC166870600001AC 1618 >EOR3M2 X1 DPIN RAM TEMP >=2 bytes,read 2 bytes 1619 >>>>>>>>>> 1AC C2CC002B37E00009AD 1620 I,X1 wait 1 instr b4 PTST 1AD 4ECC0068B1600001A9 1621 X1 PTST SCR3 EOR3M7 get port status 1622 STARTSKP 1A9 4CCBA06AFFCFCFF9AF 1623$ EOR3M7 I SCR3 IOR LIT PRTEMPTY SKIP EOR3M8 FIFO empty? 1624 >>>>>>>>>> 1AE C0CF636B686FFFF9A3 1625 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR2M4 yes,time out? 1AF 4CCBA06AFFCFEFF9B0 1626 >EOR3M8 I SCR3 IOR LIT CM-PRTLOW SKIP EOR3M3 no,at least 2 bytes? 1627 >>>>>>>>>> 1B0 C0CCA2EB60640009B1 1628 >EOR3M3 I,X1 LIT IOR RAM RAM PRTST EXTRA 2 bytes,set extra input 1B1 40CF636B686FFFF9B3 1629 >EOR3M6 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR3M4 1 byte,time out? 1630 >>>>>>>>>> 1B2 42CC006D31507FB2F4 1631 > SBST SCR0 RESERR,P RESGODIE yes, go die 1B3 40CBA06AFFC00009B4 1632 >EOR3M4 I,T4 SCR0 IOR LIT #0 SKIP EOR3M5 no,input yet? 1633 >>>>>>>>>> 1B4 42CC006B37C00009B1 1634 >EOR3M5 I,T4 EOR3M6 no,continue timing 1B5 46CC166361600009B6 1635 > I,X1 RAM SCR1 TEMP yes,2 bytes for output 1636 >>>>>>>>>> 1B6 4A8C006871600001B7 1637 X1 DPIN SCR2,H 3rd byte for output 1B7 42CC166B50600039B8 1638 I,X1 LIT RAM TEMP 3 CUNOTMT3 indicate 3 byte,go do write 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 44 PPU3/REV 25 microcode | End-Of-Record processing 1640 1B8 C2CC0BE361701B99EF 1641 CUNOTMT3 I,X1 RAM SCR0 HADDR *+1,PUSH WTFORBUS wait for BUS to be free 1B9 82CC0C2364600001BA 1642 X1,P RAM SBLC LADDR 1BA C6C8000AD3800001BB 1643 SCR1 SBHD 1BB CAC8000AD3C00001BC 1644 SCR2 SBLD 1BC 42CC0A2365600001BD 1645 X1 RAM SBCB SLOT 1BD 80CC6C6B60600011BE 1646 X1,P LIT ADD RAM RAM LADDR 1 make sure the address is righ 1648 ***************************************************************************************************** 1649 * At this point, TEMP contains the number of bytes that must be * 1650 * subtracted from the bytecount to get the correct byte count. * 1651 ***************************************************************************************************** 1652 1BE 4CDCCB6B6167FFF1BF 1653 STC,X1 LIT AND RAM SCR3 LAST CM-LASTBIT CUCKBCEQ get byte count and 1654 STARTSKP 1BF CCEB566AE9600001C0 1655 CUCKBCEQ TWC,X1 SCR3 SUB RAM SCR3 TEMP 0 SKIP CUBCNEQ compare it to FIFO count 1656 >>>>>>>>>> 1C0 CE480B6AD0600009C4 1657 >CUBCNEQ I,X1 SCR3 RAM,L LAST CUSETINT not equal,save right byte cou 1C1 C0CFCB6B68680009C3 1658 > I,X1 LIT AND RAM RAM LAST LASTBIT SKIP CUBCNLAS equal, was LAST? 1659 >>>>>>>>>> 1C2 40CCA2EB60600B29C9 1660 > I,X1 LIT IOR RAM RAM PRTST LASTBC CUEXIT yes, say so & exit 1C3 C0CCA2EB60600929C9 1661 >CUBCNLAS I,X1 LIT IOR RAM RAM PRTST BCRATEOR CUEXIT no, set PPU interrupt 1662 >>>>>>>>>> 1C4 40CCA2EB60600829C9 1664 CUSETINT I,X1 LIT IOR RAM RAM PRTST EORINTR CUEXIT set interrupt & exit 1C5 C2CC0068B1600009C6 1666 CUCKEXT I,X1 PTST SCR0 CUCKEXT1 get the port status 1667 STARTSKP 1C6 C0CBA06AFFCFCFF9C8 1668$ CUCKEXT1 I SCR0 IOR LIT PRTEMPTY SKIP CUEXTRA extra input? 1669 >>>>>>>>>> 1C8 C0CCA2EB60640009C9 1670 >CUEXTRA I,X1 LIT IOR RAM RAM PRTST EXTRA yes, say so 1C9 C0CC096B70600009CA 1671 >CUEXIT I,X1 ZERO RAM BCOVERUN set overrun detector & exit 1672 >>>>>>>>>> 1CA 42CC0068B1600009CB 1674 CKPORTPE I,X1 PTST SCR0 get port status 1CB C2CC002B55A00001CC 1675 CKPORTE2 X1 LIT DPDIR DIRINP reset data path, 1CC C2CC002B30E00001CD 1676 X1 DPRST CKPORTE1 reset Data port 1677 STARTSKP 1CD C0CBC06AFFE04001CF 1678 CKPORTE1 X1,T4 SCR0 AND LIT PRTPE SKIP EORNPE port parity error? 1679 >>>>>>>>>> 1CE C0CCA2EB60620009CF 1680 > I,X1 LIT IOR RAM RAM PRTST DPPE yes, set error 1CF C2CC000B37C00009D0 1681 >EORNPE I,T3 1682 >>>>>>>>>> 1D0 42CC000B37C00009D1 1683 I,T3 1D1 42CC002B30E00001D2 1684 X1 DPRST (reset Data port again!) 1D2 40CFC25B606DFFFFF0 1685 IP,X1 LIT AND RAM RAM FLAGS CM-REOR POP DIDNTPOP clear REOR & exit 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 45 PPU3/REV 25 microcode | End-Of-Record processing 1687 1688 ***************************************************************************************************** 1689 * * 1690 * End-Of-Record processor IBF interrupt vector. * 1691 * * 1692 ***************************************************************************************************** 1693 VECTOR 1694 >>>>>>>>>> 010 C0CCA2EB6060100011 1695 >EORIBF X1 LIT IOR RAM RAM PRTST MPECODE BPE*, RTO* but Abnormal Data 011 C6CC006DF1600001D3 1696 > X1 SBHC SCR1 EORIBF1 BPE*, RTO* and Normal Data 012 42CC006D31507FD2F2 1697 > SBST SCR0 MEM3ERR,P BFGODIE BPE*, RTO* but Command Flags 013 42CC006D31507FD2F2 1698 > SBST SCR0 MEM3ERR,P BFGODIE BPE*, RTO* but Illegal Flags 014 C2CC006D31507FD2F5 1699 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go DIE! 015 C2CC006D31507FD2F5 1700 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go DIE! 016 C2CC006D31507FD2F5 1701 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go DIE! 017 C2CC006D31507FD2F5 1702 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go DIE! 018 42CC006D31507FD2F1 1703 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 019 42CC006D31507FD2F1 1704 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 01A 42CC006D31507FD2F1 1705 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 01B 42CC006D31507FD2F1 1706 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 01C 42CC006D31507FD2F1 1707 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 01D 42CC006D31507FD2F1 1708 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 01E 42CC006D31507FD2F1 1709 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 01F 42CC006D31507FD2F1 1710 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go DIE! 1711 >>>>>>>>>> 1712 ENDVECTOR 1713 1D3 4ACC006E71400001D4 1714 EORIBF1 SBLC SCR2 1D4 42CC046B52400601D5 1715 LIT IADR IBFIADR TWOWORDS restore IBFIADR 1D5 C0CF005B7140000FF0 1716 I ZERO SCR0 POP DIDNTPOP signal xfer done&exit 1717 TITLE.MAC CPU Check Interrupt processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 46 PPU3/REV 25 microcode | CPU Check Interrupt processor 1718 1719 ***************************************************************************************************** 1720 * This routine is called from the IDLE loop and it tests * 1721 * for any of the reasons that PPUs interrupt. If any such * 1722 * condition exists, we generate the IPOLL response and set * 1723 * up the interrupt condition on the superbus. * 1724 ***************************************************************************************************** 1725 1726 STARTSKP 1C7 C0CFC2EB6FE02009D6 1727$ CKBCINT I,X1 LIT AND RAM PRTST BCINT SKIP NOTBCINT should BCROLL cause INT? 1728 >>>>>>>>>> 1D6 40CFC2EB6FE10029DA 1729 >NOTBCINT I,X1 LIT AND RAM PRTST PPUINT SKIP NOTPPUIN no, check interrupts 1D7 C0CFC2EB6FE00109D9 1730 > I,X1 LIT AND RAM PRTST BCROLL SKIP CKINT yes, rollover? 1731 >>>>>>>>>> 1D8 40CCA2EB60600029D9 1732 > I,X1 LIT IOR RAM RAM PRTST PPUINTR yes, set int request 1D9 40CFC2EB6FE10029DA 1733 >CKINT I,X1 LIT AND RAM PRTST PPUINT SKIP NOTPPUIN PPU to interrupt? 1734 >>>>>>>>>> 1DA 40CFC2EB6FE08089DC 1735 >NOTPPUIN I,X1 LIT AND RAM PRTST CTLRINT SKIP NOTCTRIN no, controller? 1DB D4C8D66AF0600039DE 1736 > I,X1 SCR5 AND LIT RAM TEMP PRTNUMMASK SETINT yes, set INT (save port #) 1737 >>>>>>>>>> 1DC 42CF005B37C0000FF0 1738 >NOTCTRIN IP POP DIDNTPOP no, return 1DD D4C8D66AF0600039DE 1739 > I,X1 SCR5 AND LIT RAM TEMP PRTNUMMASK SETINT yes, set INT (save port #) 1740 >>>>>>>>>> 1741 1DE DCCCB66B61680009DF 1742 SETINT I,X1 LIT IOR RAM SCR7 TEMP #8000 construct the INT POLL respon 1DF 42CF005B5180001FF0 1743 IP LIT SBINT INT POP DIDNTPOP set INT bit 1744 TITLE.MAC CPU Request processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 47 PPU3/REV 25 microcode | CPU Request processor 1745 1746 ***************************************************************************************************** 1747 * We come here if there is bus input ready to process. * 1748 * The idle loop code will have loaded SCRF (the counter for * 1749 * bus input store locations) into INDX1. * 1750 ***************************************************************************************************** 1751 1752 STARTSKP 1E0 40CFAF6B6FE7FFF9E2 1753$ CKLEGAL I,X1 LIT IOR RAM BIHC #7FFF SKIP NOTLEGAL assigned command? 1754 >>>>>>>>>> 1E2 6ECC006B51430001E5 1755 >NOTLEGAL LIT SCRB #3000 BADCOMM no, assert BE & die! 1E3 CDCCAF6B61680009E4 1756 > I,X1 LIT IOR,X RAM SCR3 BIHC IRIOR*2^12 yes, go process 1757 >>>>>>>>>> 1E4 4EC9006ADFC0000F98 1758 I SCR3 DB4 BIRTAB 1E5 7EC8000AD4D07F932C 1760 BADCOMM SCRF INDX1 BADINP,P WTFORPON bad command or bad data 1762 BLOCK 8,IRIOR 1763 >>>>>>>>>> 798 40CCCF6B616003F248 1764 >BIRTAB X1 LIT AND RAM SCR0 BIHC #003F BIWRITE was WRITE- known port? 799 6ECC006B51430001E5 1765 > LIT SCRB #3000 BADCOMM Read-Modify-Write: error 79A C1CCD16B616000FA1C 1766 > I,X1 LIT AND,X RAM SCR0 BIFT #000F BIREAD was READ - get FROM slot # 79B 6ECC006B51430001E5 1767 > LIT SCRB #3000 BADCOMM Double-Word-Read: error 79C 40CFAFEB6FE000FA00 1768 > I,X1 LIT IOR RAM BILC #000F SKIP WRULEGAL was WRU - legal address? 79D C2CC002B37C00003D8 1769 > SELFTEST Self-Test 79E EECC006B51440001E5 1770 > LIT SCRB #4000 BADCOMM bad address on INT POLL 79F 6ECC006B51430001E5 1771 > LIT SCRB #3000 BADCOMM unassigned command 1772 >>>>>>>>>> 1773 ENDBLOCK 1774 1775 ***************************************************************************************************** 1776 * We come here with a response set up in SCR0 (high) * 1777 * and SCR1 (low) and the bus control bits in SCR2. * 1778 ***************************************************************************************************** 1779 1E6 C2CC000B37D01E79EF 1780 RESPEXIT I *+1,PUSH WTFORBUS wait for BUS to be free 1E7 46C8000AD4400001E8 1781 SCR1 SBLC and do output 1E8 CAC8002AD5400001E9 1782 SCR2 SBCB 1E9 50C8606AF1400011EA 1783 SCR4 ADD LIT SCR4 TIMERSPX DECIBF bump timer, delay for RTO and 1784 1785 ***************************************************************************************************** 1786 * We come here when one of the words in the input * 1787 * buffer (the PPU can buffer up to four communications * 1788 * from CPUs) has been read. We advance the pointers and * 1789 * exit. * 1790 ***************************************************************************************************** 1791 1EA FCC8606AF1400019EB 1792 DECIBF I SCRF ADD LIT SCRF 1 increment the IBF pointer, 1EB F4C8606AF14FFFF1EC 1793 SCRD ADD LIT SCRD -1 decrement the count, 1EC E0C8C06AF14FFEF1ED 1794 SCR8 AND LIT SCR8 CM-CBNIM and turn on RFI 1ED E2C8002AD5C00001EE 1795 SCR8 IMR (ie alllow CBN interrupts) 1EE D6CB005AD4C0000FF0 1796 IP SCR5 INDX1 POP DIDNTPOP restore index & continue 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 48 PPU3/REV 25 microcode | CPU Request processor 1798 ***************************************************************************************************** 1799 * This subroutine waits for the bus logic to become free * 1800 * (i.e. NOT rto AND NOT rfr AND NOT ibf). When the bus logic * 1801 * gets free, SCR0 is stored into SBHC, so the caller of this * 1802 * subroutine must put what he wants in SBHC into SCR0 before * 1803 * calling this subroutine. This subroutine also times the wait. * 1804 * This subroutine checks immediately to see if the bus is * 1805 * free for a minimum delay path through the code. If the bus * 1806 * is busy when first entered, a time out timer is set up and * 1807 * a loop waits for a short while (80 usec) to see if the bus * 1808 * will become available even with the data channel interrupts * 1809 * enabled. This is to protect any syncronous devices that * 1810 * are present by ensuring that no such device has a request * 1811 * outstanding. If the bus doesn't become free before the * 1812 * timeout, then we assume that the load is caused by asyncronous * 1813 * data channel devices that can swamp the PPU to memory channel. * 1814 * We disable data channel interrupts (but we must still allow * 1815 * IBF interrupts) and wait again for the bus to become free. * 1816 * This, if effect, forces the data channels to give up a * 1817 * transfer slot. It is possible for a syncronous device to * 1818 * be hurt badly if a lower priority asyncronous device steals * 1819 * any remaining cycles and forces the code here to steal one. * 1820 * If the bus doesn't become free before this time-out, then * 1821 * the PPU is in a confused state with respect to its bus logic. * 1822 ***************************************************************************************************** 1823 1EF 6CC8606AF1400019F0 1824 WTFORBUS I SCRB ADD LIT SCRB 1 indicate 'New BUS Transfer' 1F0 4ECC006D31400009F1 1825 I SBST SCR3 load current bus status 1F1 CCCBA06AFFCF5BF1F7 1826 SCR3 IOR LIT BUSFREE SKIP WFBNAVAL skip if available immediately 1827 1828 STARTSKP 1E1 CCCBA06AFFCF5BF1F2 1829$ WFBCKFRE SCR3 IOR LIT BUSFREE SKIP WFBAV check bus available 1830 >>>>>>>>>> 1F2 40CF76EB686FFFF9F4 1831 >WFBAV I,X1 LIT ADD RAM RAM TEMP2 -1 SKIP WFBGSTAT bus busy, time-out? 1F3 C2CB001AD4000007F0 1832 > SCR0 SBHC POP DIDNTPOP yes, start output and return 1833 >>>>>>>>>> 1834 >>>>>>>>>> 1F4 CECC006D31400009E1 1835 >WFBGSTAT I SBST SCR3 WFBCKFRE no, wait for bus 1F5 E0C8B6EAF06001F9F8 1836 > I,X1 SCR8 IOR LIT RAM TEMP2 #001F WFBSTG2 copy int mask, no chan its 1837 >>>>>>>>>> 1838 >>>>>>>>>> 1F6 C2CB001AD4000007F0 1839 >WFBOUTS SCR0 SBHC POP DIDNTPOP yes, start output and return 1F7 C2CC16EB50600649F4 1840 >WFBNAVAL I,X1 LIT RAM TEMP2 WFBTO WFBGSTAT busy, set up a time-out 1841 >>>>>>>>>> 1842 1843 * Bus logic has remained busy for at least 80 usec. Turn off data 1844 * channel interrupts to force us to get a bus transfer. 1845 1F8 4ECC16E361600001F9 1846 WFBSTG2 X1 RAM SCR3 TEMP2 copy altered imr to register 1F9 4EC8002AD5C00001FA 1847 SCR3 IMR dis-allow any channel interru 1FA 42CC16EB50604E21FE 1848 X1 LIT RAM TEMP2 WFBTO2 WFBSTG2Y set up a time-out 1849 1850 STARTSKP 1FB 4CCBA06AFFCF5BF1FC 1851 WFBSTG2Q SCR3 IOR LIT BUSFREE SKIP WFB2AV check bus available 1852 >>>>>>>>>> 1FC 40CF76EB686FFFF9FE 1853 >WFB2AV I,X1 LIT ADD RAM RAM TEMP2 -1 SKIP WFBSTG2Y bus busy, time-out? 1FD E2C8002AD5C00001F6 1854 > SCR8 IMR WFBOUTS restore channel interrupts 1855 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 49 PPU3/REV 25 microcode | CPU Request processor 1856 >>>>>>>>>> 1FE 4ECC006D31400009FB 1857 >WFBSTG2Y I SBST SCR3 WFBSTG2Q no, wait for bus 1FF 42CC006D31507FC2F5 1858 > SBST SCR0 WFBERR,P CONGODIE timeout, go DIE! 1859 >>>>>>>>>> 1860 TITLE.MAC CPU WRU processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 50 PPU3/REV 25 microcode | CPU WRU processor 1861 1862 SKIPORG 1863 >>>>>>>>>> 200 EECC006B51440001E5 1864 >WRULEGAL LIT SCRB #4000 BADCOMM illegal address, assert BE 201 C1CCD16B616000FA02 1865 > I,X1 LIT AND,X RAM SCR0 BIFT #000F get FROM slot # 1866 >>>>>>>>>> 202 C0C8B66AF060011A03 1867 I,X1 SCR0 IOR LIT RAM TEMP RTODATA 203 4ACC16636160000A04 1868 I,X1 RAM SCR2 TEMP CKWRUIS0 (save RESPTO data) 1869 STARTSKP 204 C0CFAFEB6960000A06 1870$ CKWRUIS0 I,X1 LIT IOR RAM SCR0 BILC 0 SKIP WRUNOT0 WRU #0? 1871 >>>>>>>>>> 206 C2C8166AD07020BA15 1872 >WRUNOT0 I,X1 SCR0 RAM TEMP DOWRU,P SHIFTL4 no, shift address left by 6 207 DCCBA06AFFC0000A09 1873 > I SCR7 IOR LIT 0 SKIP *+2 yes, are we interrupting? 1874 >>>>>>>>>> 208 C2C8166AD07020BA15 1875 > I,X1 SCR0 RAM TEMP DOWRU,P SHIFTL4 no, shift address left by 6 209 C2CC002B54C0000A0A 1876 > I LIT INDX1 0 yes, say so. 1877 >>>>>>>>>> 20A 40CCB26B6160400A11 1878 I,X1 LIT IOR RAM SCR0 WRURES1A #400 DOWRU1 set the interrupt bit 20B 42C8166AD07020CA19 1880 DOWRU I,X1 SCR0 RAM TEMP *+1,PUSH SHIFTL2 20C CCCCCFEB6160003A0D 1881 I,X1 LIT AND RAM SCR3 BILC #0003 use the 2 LSB's for branching 20D 41C8C06AF140300A0E 1882 I SCR0 AND,X LIT SCR0 #0300 and the 2 MSB's for indexing 20E 42C8002AD4C0000A0F 1883 I SCR0 INDX1 20F 4CC8A06AF140008A10 1884 I SCR3 IOR LIT SCR3 WRUIOR 210 CECA006ADFC0000FE8 1885 I SCR3 DB0 WRUTABLE 1887 BLOCK 4,WRUIOR 1888 >>>>>>>>>> 7E8 C2CC12636160000A11 1889 >WRUTABLE I,X1 RAM SCR0 WRURES1A DOWRU1 7E9 42CC13636160000A12 1890 > I,X1 RAM SCR0 WRURES2A DOWRU2 7EA 42CC14636160000A13 1891 > I,X1 RAM SCR0 WRURES3A DOWRU3 7EB 42CC15636160000A14 1892 > I,X1 RAM SCR0 WRURES4A DOWRU4 1893 >>>>>>>>>> 1894 ENDBLOCK 1895 211 46CC12E361600009E6 1896 DOWRU1 I,X1 RAM SCR1 WRURES1B RESPEXIT 212 C6CC13E361600009E6 1897 DOWRU2 I,X1 RAM SCR1 WRURES2B RESPEXIT 213 46CC14E361600009E6 1898 DOWRU3 I,X1 RAM SCR1 WRURES3B RESPEXIT 214 C6CC15E361600009E6 1899 DOWRU4 I,X1 RAM SCR1 WRURES4B RESPEXIT 215 C0C8766AE160000216 1901 SHIFTL4 X1 SCR0 ADD RAM SCR0 TEMP 216 42C8166AD060000217 1902 X1 SCR0 RAM TEMP 217 40C8766AE160000218 1903 SHIFTL3 X1 SCR0 ADD RAM SCR0 TEMP 218 C2C8166AD060000219 1904 X1 SCR0 RAM TEMP 219 C0C8766AE16000021A 1905 SHIFTL2 X1 SCR0 ADD RAM SCR0 TEMP 21A 42C8166AD06000021B 1906 X1 SCR0 RAM TEMP 21B C0CB767AE1600007F0 1907 X1 SCR0 ADD RAM SCR0 TEMP POP DIDNTPOP 1908 TITLE.MAC CPU Read processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 51 PPU3/REV 25 microcode | CPU Read processor 1909 21C C0C8B66AF060011A1D 1910 BIREAD I,X1 SCR0 IOR LIT RAM TEMP RTODATA 21D CACC16636160000A1E 1911 I,X1 RAM SCR2 TEMP (save RESPTO data) 21E CECC0FE36160000A1F 1912 I,X1 RAM SCR3 BILC get the request for later 21F C4CCCF6B6160003A20 1913 I,X1 LIT AND RAM SCR1 BIHC PRTNUMMASK (save the port #) 220 40CCCF6B616003F221 1914 X1 LIT AND RAM SCR0 BIHC #003F RCKWNPRT put port # in scratch 1915 STARTSKP 221 C0CBA06AFFC0003A23 1916 RCKWNPRT I SCR0 IOR LIT PRTNUMMASK SKIP RPTNOTKN is it a good port? 1917 >>>>>>>>>> 222 42C8002AD4C0000A05 1918 > I SCR0 INDX1 RDCKWHO1 223 EECC006B51440001E5 1919 >RPTNOTKN LIT SCRB #4000 BADCOMM no, assert BE & die! 1920 >>>>>>>>>> 1922 STARTSKP 205 CCCBC06AFFC0200A24 1923$ RDCKWHO1 I SCR3 AND LIT CBIT SKIP RDISUS to us or to controller? 1924 >>>>>>>>>> 224 CCCBA06AFFC000FA32 1925 >RDISUS I SCR3 IOR LIT #000F SKIP RDNOTLEG to us. known address? 225 C0CFC26B6FE4000A27 1926 > I,X1 LIT AND RAM FLAGS PORTDEAD SKIP RNOTDEAD to controller. port DEAD? 1927 >>>>>>>>>> 226 C0CC006B7140000A30 1928 > I ZERO SCR0 SENDLZ yes, respond with zero 227 C0CFA26B6FEF4FFA28 1929 >RNOTDEAD I,X1 LIT IOR RAM FLAGS CSFREE SKIP RNOTFREE no, is the C/S port free? 1930 >>>>>>>>>> 228 D6CB005AD4C0000FF0 1931 >RNOTFREE IP SCR5 INDX1 POP DIDNTPOP no, wait 'til complete 229 C2CC002B50A006222A 1932 > X1 LIT CSOUT CTLRRD yes, start read 1933 >>>>>>>>>> 22A C2CC026B5060E81A2B 1934 I,X1 LIT RAM FLAGS STARTRD set flag & retry count 22B C2CC046B506809DA2C 1935 I,X1 LIT RAM TYPECKSM CRDSTART set type, count & checksum 22C D0C864EAF06053CA2D 1936 I,X1 SCR4 ADD LIT RAM CNTDOWN TIMECNST start timer 22D 4AC806EAD060000A2E 1937 I,X1 SCR2 RAM RESPTO set where to respond 22E 50C8606AF140003A2F 1938 I SCR4 ADD LIT SCR4 TIMERW bump clock for overhead 22F CEC8056AD0600009EA 1939 I,X1 SCR3 RAM ADDRESS DECIBF set address to send 230 C4CC006B7140000A31 1941 SENDLZ I ZERO SCR1 set lower half to zero 231 48C8806AF1400109E6 1942 I SCR2 XOR LIT SCR2 ADATAXOR RESPEXIT & send Abnormal Data 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 52 PPU3/REV 25 microcode | CPU Read processor 1944 1945 SKIPORG 1946 >>>>>>>>>> 232 EECC006B51440001E5 1947 >RDNOTLEG LIT SCRB #4000 BADCOMM unknown add, assert BE & die! 233 4ECA006ADFC0000F80 1948 > I SCR3 DB0 RDTAB yes, process request 1949 >>>>>>>>>> 1950 1951 BLOCK 16 1952 >>>>>>>>>> 780 CCCC006B7140000A27 1953 >RDTAB I ZERO SCR3 RNOTDEAD device ID, give to controller 781 5CCBA06AFFC000023F 1954 > SCR7 IOR LIT 0 SKIP RDSTS internal status, INT on? 782 C2CC07636160000A34 1955 > I,X1 RAM SCR0 HSW1 RDSW1 controller status one 783 42CC08636160000A35 1956 > I,X1 RAM SCR0 HSW2 RDSW2 controller status two 784 C2CC0A636160000A36 1957 > I,X1 RAM SCR0 SLOT RDBCNT current byte count 785 42CC0BE36160000A37 1958 > I,X1 RAM SCR0 HADDR RDMA1 current memory address 786 C2CC0CE36160000A38 1959 > I,X1 RAM SCR0 SLOT2 RDBCNT2 next byte count 787 42CC0E636160000A39 1960 > I,X1 RAM SCR0 HADDR2 RDMA2 next memory address 788 C0CC006B7140000A47 1961 > I ZERO SCR0 RDMODEDW double word read status (neve 789 EECC006B51440001E5 1962 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 78A EECC006B51440001E5 1963 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 78B EECC006B51440001E5 1964 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 78C EECC006B51440001E5 1965 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 78D EECC006B51440001E5 1966 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 78E EECC006B51440001E5 1967 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 78F EECC006B51440001E5 1968 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 1969 >>>>>>>>>> 1970 ENDBLOCK 234 C6CC07E361600009E6 1972 RDSW1 I,X1 RAM SCR1 LSW1 RESPEXIT 235 C6CC08E361600009E6 1973 RDSW2 I,X1 RAM SCR1 LSW2 RESPEXIT 236 46CC0AE3616000023A 1974 RDBCNT X1 RAM SCR1 BCNT CORRBC 237 46CC0C6361600001E6 1975 RDMA1 X1 RAM SCR1 LADDR RESPEXIT 238 C6CC0D63616000023B 1976 RDBCNT2 X1 RAM SCR1 BCNT2 CORRBC2 239 C6CC0EE361600009E6 1977 RDMA2 I,X1 RAM SCR1 LADDR2 RESPEXIT 23A C4C86B6AE16000023C 1979 CORRBC X1 SCR1 ADD RAM SCR1 LAST CORRBC3 recombine BC with LAST 1980 23B 44C86DEAE16000023C 1981 CORRBC2 X1 SCR1 ADD RAM SCR1 LAST2 recombine BC with LAST 23C 44C869EAE1600001E6 1982 CORRBC3 X1 SCR1 ADD RAM SCR1 CORBC RESPEXIT and the correction count 1983 1984 SKIPORG 1985 >>>>>>>>>> 23E C6CC02E36160000A45 1986 > I,X1 RAM SCR1 PRTST RDSTEXIT no, process read status 23F DCD8D66AF06000323D 1987 >RDSTS STC,X1 SCR7 AND LIT RAM TEMP PRTNUMMASK CKINTUS yes, get port # of INT 1988 >>>>>>>>>> 1989 STARTSKP 23D 44EB566AEFE0000240 1990$ CKINTUS TWC,X1 SCR1 SUB RAM TEMP 0 SKIP INTNOTUS is it us? 1991 >>>>>>>>>> 240 C6CC02E36160000A45 1992 >INTNOTUS I,X1 RAM SCR1 PRTST RDSTEXIT 241 C6CC02E36160000242 1993 > X1 RAM SCR1 PRTST INTISUS 1994 >>>>>>>>>> 1995 242 C0CC000B7180000243 1996 INTISUS ZERO SBINT yes, clear INT 243 DCCC006B7140000244 1997 ZERO SCR7 & INT POLL response 244 40CCC2EB606E7FF245 1998 X1 LIT AND RAM RAM PRTST INTCLR clear interrupt, 245 42CC02636160000246 1999 RDSTEXIT X1 RAM SCR0 FLAGS setup for output 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 53 PPU3/REV 25 microcode | CPU Read processor 246 C0CCC2EB606FFE51E6 2000 X1 LIT AND RAM RAM PRTST STSCLBTS RESPEXIT clear status & exit 2001 247 C4CC006B71400009E6 2002 RDMODEDW I ZERO SCR1 RESPEXIT double word read status (neve 2003 TITLE.MAC CPU Write processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 54 PPU3/REV 25 microcode | CPU Write processor 2004 2005 STARTSKP 248 40CBA06AF940003A4A 2006$ BIWRITE I SCR0 IOR LIT SCR0 PRTNUMMASK SKIP WPTNOTKN is legal port #? 2007 >>>>>>>>>> 24A EECC006B51440001E5 2008 >WPTNOTKN LIT SCRB #4000 BADCOMM unknown port, assert BE & die 24B CECC0FE36160000A4C 2009 > I,X1 RAM SCR3 BILC known port, save command & da 2010 >>>>>>>>>> 24C C6CC10636160000A4D 2011 I,X1 RAM SCR1 BIHD 24D 4ACC10E36160000A4E 2012 I,X1 RAM SCR2 BILD 24E 40CCCF6B6160003A4F 2013 I,X1 LIT AND RAM SCR0 BIHC PRTNUMMASK set index 24F C2C8002AD4C0000A49 2014 I SCR0 INDX1 WRCKWHO 2015 STARTSKP 249 CCCBC06AFFC0200A50 2016$ WRCKWHO I SCR3 AND LIT CBIT SKIP WRISUS to us or controller? 2017 >>>>>>>>>> 250 CCCBA06AFFC000FA5E 2018 >WRISUS I SCR3 IOR LIT #000F SKIP WRNOTLEG to us. known address? 251 C0CFC26B6FE4000A53 2019 > I,X1 LIT AND RAM FLAGS PORTDEAD SKIP WNOTDEAD to controller. port DEAD? 2020 >>>>>>>>>> 252 42CC002B37C00009EA 2021 > I DECIBF yes, just ignore it 253 40CFA26B6FEF4FFA54 2022 >WNOTDEAD I,X1 LIT IOR RAM FLAGS CSFREE SKIP WNOTFREE no, is the C/S port free 2023 >>>>>>>>>> 254 D6CB005AD4C0000FF0 2024 >WNOTFREE IP SCR5 INDX1 POP DIDNTPOP no, wait 'til complete 255 C2CC002B50A0096256 2025 > X1 LIT CSOUT CTLRWR yes, start write 2026 >>>>>>>>>> 256 C2CC026B5060681A57 2027 I,X1 LIT RAM FLAGS STARTWR set flag & retry count 257 C2CC046B5060069A58 2028 I,X1 LIT RAM TYPECKSM CWRSTART set type, count & checksum 258 D0C864EAF06053CA59 2029 I,X1 SCR4 ADD LIT RAM CNTDOWN TIMECNST start timer 259 4EC8056AD060000A5A 2030 I,X1 SCR3 RAM ADDRESS setup bytes for output 25A C6C805EAD060000A5B 2031 I,X1 SCR1 RAM HWORD 25B D0C8606AF140006A5C 2032 I SCR4 ADD LIT SCR4 TIMEWW bump clock for overhead 25C 4AC8066AD0600009EA 2033 I,X1 SCR2 RAM LWORD DECIBF exit 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 55 PPU3/REV 25 microcode | CPU Write processor 2035 2036 SKIPORG 2037 >>>>>>>>>> 25E EECC006B51440001E5 2038 >WRNOTLEG LIT SCRB #4000 BADCOMM unknown address, assert BE & 25F 4ECA006ADFC0000F70 2039 > I SCR3 DB0 WRTAB 2040 >>>>>>>>>> 2041 2042 BLOCK 16 2043 >>>>>>>>>> 770 64C8A16AE160000260 2044 >WRTAB X1 SCR9 IOR RAM SCR9 PBITHIGH RESCONT reset a controller 771 40CCC2EB6069A89265 2045 >WRTABABT X1 LIT AND RAM RAM PRTST ABTCLR ABORT abort FIFO operation 772 C8C8C06AF141A01A71 2046 > I SCR2 AND LIT SCR2 GOODBITS SSSTS selective set status 773 C8C8C06AF141A01A72 2047 > I SCR2 AND LIT SCR2 GOODBITS SCSTS selective clear status 774 40CFC2EB6FE8000A74 2048 > I,X1 LIT AND RAM PRTST BTWREC SKIP LDBC1 set 1st byte count 775 46C8166AD0702E8AE4 2049 > I,X1 SCR1 RAM TEMP LDMA1,PUSH ADDIR set 1st memory address 776 C8CBA06AFFC8000AAD 2050 > I SCR2 IOR LIT LASTBIT SKIP LDBC2 set next byte count 777 C6C8166AD0702ECAE4 2051 > I,X1 SCR1 RAM TEMP LDMA2,PUSH ADDIR set next memory address 778 42CC002B37C00009EA 2052 > I DECIBF enable triple word, ignore 779 EECC006B51440001E5 2053 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 77A EECC006B51440001E5 2054 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 77B EECC006B51440001E5 2055 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 77C EECC006B51440001E5 2056 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 77D EECC006B51440001E5 2057 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 77E EECC006B51440001E5 2058 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 77F EECC006B51440001E5 2059 > LIT SCRB #4000 BADCOMM unknown address, assert BE & 2060 >>>>>>>>>> 2061 ENDBLOCK 260 64C8816AE160000261 2063 RESCONT X1 SCR9 XOR RAM SCR9 PBITHIGH 261 E6C8002AD48000025D 2064 SCR9 DPOE RESCONT1 assert MCLR (master clear) 2065 STARTSKP 25D C2CC006B51400C8A62 2066$ RESCONT1 I LIT SCR0 200 RESCONT2 set a timer 2067 >>>>>>>>>> 262 40CB606AF94FFFFA62 2068 >RESCONT2 I SCR0 ADD LIT SCR0 -1 SKIP RESCONT2 wait 50 u-seconds 263 42CC000B37D0264A67 2069 > I *+1,PUSH ABORTPRT then do an abort 2070 >>>>>>>>>> 264 64C8816AE160000F71 2071 I,X1 SCR9 XOR RAM SCR9 PBITHIGH WRTABABT release MCLR and cleanup 265 C0CCA2EB6068080266 2073 ABORT X1 LIT IOR RAM RAM PRTST ABTSET clear & set selected status 266 C0CC026B70701EA267 2074 X1 ZERO RAM FLAGS DECIBF,P ABORTPRT clear I/O & cleanup this port 2075 267 E4C8A0EAE160000268 2076 ABORTPRT X1 SCR9 IOR RAM SCR9 PBITLOW clear output enable 268 E4C880EAE160000269 2077 X1 SCR9 XOR RAM SCR9 PBITLOW 269 66C8002AD48000026A 2078 SCR9 DPOE 26A 42CC002B55A000026B 2079 X1 LIT DPDIR DIRINP set direction to read 26B 42CC002B30E000026C 2080 X1 DPRST reset Data port 26C E0C8A1EAE16000026D 2081 X1,T4 SCR8 IOR RAM SCR8 PBITIM disallow interrupts this port 26D 62C8002AD5C000026E 2082 SCR8 IMR 26E C2CC000B37C000026F 2083 T3 26F C2CC002B30E0000270 2084 X1 DPRST (reset the Data port again!) 270 C0CF095B7060000FF0 2085 IP,X1 ZERO RAM BCOVERUN POP DIDNTPOP set overrun detector & exit 271 C8C8A2EAE0600009EA 2087 SSSTS I,X1 SCR2 IOR RAM RAM PRTST DECIBF set selected bits & exit 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 56 PPU3/REV 25 microcode | CPU Write processor 272 48C8A2EAE060000273 2089 SCSTS X1 SCR2 IOR RAM RAM PRTST set the selected bits 273 48C882EAE0600009EA 2090 I,X1 SCR2 XOR RAM RAM PRTST DECIBF then clear them & exit 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 57 PPU3/REV 25 microcode | CPU Write processor 2092 2093 ***************************************************************************************************** 2094 * The first part of this routine -- down to TESTDIR -- * 2095 * checks to ensure that we have valid data. This includes: * 2096 * -we must be between records or the port gets confused. * 2097 * -if not last BC, BC must be a multiple of 4 and not zero else BUS ERROR * 2098 * This part also handles the special case of BC=0 so the * 2099 * following routines know that the byte count will always be * 2100 * greater than zero. * 2101 ***************************************************************************************************** 2102 2103 SKIPORG 2104 >>>>>>>>>> 274 C0CCA2EB60604029EA 2105 >LDBC1 I,X1 LIT IOR RAM RAM PRTST CONFUSED DECIBF no, confusing. 275 48CBA06AFFC8000A77 2106 > I SCR2 IOR LIT LASTBIT SKIP *+2 yes, byte count equal zero? 2107 >>>>>>>>>> 276 48CBC06AFFE8000A7C 2108 > I,X1 SCR2 AND LIT LASTBIT SKIP BCNLAST yes, last BC? 277 C8CBC06AFFC8000A79 2109 > I SCR2 AND LIT LASTBIT SKIP *+2 not zero, last BC? 2110 >>>>>>>>>> 278 4AC80B6AD060000A7E 2111 > I,X1 SCR2 RAM LAST TESTDIR yes, anything else is OK 279 48CBA06AFFCFFFCA7A 2112 > I SCR2 IOR LIT #FFFC SKIP no, a multiple of 4? 2113 >>>>>>>>>> 27A 40CCA2EB6060402AF0 2114 > I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA no, unacceptable data 27B 4AC80B6AD060000A7E 2115 > I,X1 SCR2 RAM LAST TESTDIR yes, OK 2116 >>>>>>>>>> 2118 SKIPORG 2119 >>>>>>>>>> 27C 40CCA2EB6060402AF0 2120 >BCNLAST I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA no, cockpit error 27D 40CCC2EB6067FFF9EA 2121 > I,X1 LIT AND RAM RAM PRTST CM-BTWREC DECIBF yes, just wait for the EOR 2122 >>>>>>>>>> 2124 ***************************************************************************************************** 2125 * * 2126 * The next few lines determine what the direction is. They * 2127 * jump to the appropriate initialization routine to initialize * 2128 * the BCNT, LAST, and CORBC variables. These few lines also do * 2129 * the first part of the data port reset (I.E. they set the * 2130 * direction and do the first DPRST). * 2131 * * 2132 ***************************************************************************************************** 2133 2134 STARTSKP 27E 40CFC2EB6DA0001280 2135$ TESTDIR X1 LIT AND RAM DPDIR PRTST DMADIR SKIP DIRISIN test/set DMA direction 2136 >>>>>>>>>> 280 42CC006B38F0291764 2137 >DIRISIN X1 DPRST READBC,P INDX FISETINT set IADR for read (N.I. must 281 40CFCC6B68E0001282 2138 > X1 LIT AND RAM DPRST LADDR 1 SKIP is start address odd? 2139 >>>>>>>>>> 282 C0CC6B6B696FFFF7EC 2140 > X1,T4 LIT ADD RAM SCR0 LAST -1 INDX FOSETIN1 no, set for double fetch 283 C2CC006B3FF0284750 2141 > X1,T4 *+1,PUSH INDX FOSETI1W yes, set for single fetch 2142 >>>>>>>>>> 284 C0CC6B6B616FFFFA85 2143 > I,X1 LIT ADD RAM SCR0 LAST -1 285 C0CBA06AFFC8003A87 2144 > I SCR0 IOR LIT #8003 SKIP *+2 BC>4? 2145 >>>>>>>>>> 286 C0CC006B7140000A8B 2146 > I ZERO SCR0 WRITEBC1 no, setup for one word fetch 287 C0CC6B6B616FFFBA88 2147 > I,X1 LIT ADD RAM SCR0 LAST -5 yes, process 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 58 PPU3/REV 25 microcode | CPU Write processor 2148 >>>>>>>>>> 2149 288 C0C8C06AF147FF8A89 2150 I SCR0 AND LIT SCR0 #7FF8 289 C0C8606AF140004A8B 2151 I SCR0 ADD LIT SCR0 4 WRITEBC1 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 59 PPU3/REV 25 microcode | CPU Write processor 2153 2154 BLOCK 4,OUTIOR1 2155 >>>>>>>>>> 7EC 42CC0E6B524005028A 2156 >FOSETIN1 LIT IADR PRT0IADR FOUTINT WRITEBC set output- port 0 7ED C2CC0C6B524005028A 2157 > LIT IADR PRT1IADR FOUTINT WRITEBC 7EE C2CC0A6B524005028A 2158 > LIT IADR PRT2IADR FOUTINT WRITEBC 7EF 42CC086B524005028A 2159 > LIT IADR PRT3IADR FOUTINT WRITEBC set output- port 3 2160 >>>>>>>>>> 2161 ENDBLOCK 28A 40C8C06AF147FF8A8B 2163 WRITEBC I SCR0 AND LIT SCR0 #7FF8 28B C0DC09EB706000028C 2164 WRITEBC1 STC,X1 ZERO RAM CORBC set the BC correction count 28C C0E82B6AE06000028D 2165 TWC,X1 SCR0 RSUB RAM RAM LAST adjust LAST to remainder 28D C2C80AEAD060000A8E 2166 I,X1 SCR0 RAM BCNT save whole word part of byte 28E 42C803EAD060000A8F 2167 I,X1 SCR0 RAM CLKFIX save for clock correction 28F C0CCC2EB6061E0BA90 2168 I,X1 LIT AND RAM RAM PRTST BC1CLR 290 42CC002B30E0000299 2169 X1 DPRST ALLOWINT (reset the Data port again!) 291 42CC09EB5060004A92 2171 READBC I,X1 LIT RAM CORBC 4 set the BC correction count 292 C0DCCB6B6167FFC293 2172 STC,X1 LIT AND RAM SCR0 LAST #7FFC 293 40E82B6AE060000294 2173 TWC,X1 SCR0 RSUB RAM RAM LAST remove partial word count 294 C0C86AEAF06FFFCA95 2174 I,X1 SCR0 ADD LIT RAM BCNT -4 295 C0CCC2EB6061E0BA96 2175 I,X1 LIT AND RAM RAM PRTST BC1CLR 296 C2CC002B30E0000297 2176 X1 DPRST CKIFINT (reset the Data port again!) 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 60 PPU3/REV 25 microcode | CPU Write processor 2178 ***************************************************************************************************** 2179 * This part enables interrupts if they should be enabled and pre-fills * 2180 * the FIFO if the direction is output. * 2181 * The FIFO pre-fill is accomplished by alternately allowing interrupts * 2182 * on this port and dis-allowing interrupts on this port. This prevents this * 2183 * port from starving other ports during the initial loading of the FIFO. * 2184 * We use a PUSH and the interruptable POP in turn because this allows * 2185 * this loop to ensure progress even with interrupts happening. * 2186 ***************************************************************************************************** 2187 2188 STARTSKP 297 40CFCAEB6FE8000299 2189 CKIFINT X1,T4 LIT AND RAM BCNT #8000 SKIP ALLOWINT no int's if INPUT & BC<4 2190 >>>>>>>>>> 298 40CCA2EB60600809EA 2191 > I,X1 LIT IOR RAM RAM PRTST DMANBZ DECIBF signal FIFO not running 299 E0C8A1EAE1701EA29A 2192 >ALLOWINT X1,T4 SCR8 IOR RAM SCR8 PBITIM DECIBF,P DO1FETCH allow at least 1 interrupt 2193 >>>>>>>>>> 29A 60C881EAE16000029B 2195 DO1FETCH X1 SCR8 XOR RAM SCR8 PBITIM allow interrupts this port 29B 62C8002AD5C000027F 2196 SCR8 IMR DO1FCK 2197 STARTSKP 27F C0CFC2EB6FE000129C 2198$ DO1FCK X1 LIT AND RAM PRTST DMADIR SKIP DO1FEXIT write? 2199 >>>>>>>>>> 29C 42CF005B37C0000FF0 2200 >DO1FEXIT IP POP DIDNTPOP no, just exit 29D C2CC006B514000A29E 2201 > LIT SCR0 10 DO1FLOOP yes, do pre-fill of FIFO 2202 >>>>>>>>>> 2203 STARTSKP 29E 40CFC2EB6FE00202A1 2204$ DO1FLOOP X1 LIT AND RAM PRTST BCLAST SKIP DO1FNEND BC exhasted? 2205 >>>>>>>>>> 2A0 42CF005B37C0000FF0 2206 > IP POP DIDNTPOP yes, that's it 2A1 40CB606AF94FFFF2A3 2207 >DO1FNEND SCR0 ADD LIT SCR0 -1 SKIP *+2 no, done enough? 2208 >>>>>>>>>> 2A2 42CF005B37C0000FF0 2209 > IP POP DIDNTPOP yes, exit 2A3 60C881EAE1702A52A4 2210 > X1 SCR8 XOR RAM SCR8 PBITIM *+2,PUSH *+1 no, allow only 1 interrupt 2211 >>>>>>>>>> 2A4 E2CB005AD5C0000FF0 2212 IP SCR8 IMR POP DIDNTPOP 2A5 42CC000B37D02A72A6 2213 *+2,PUSH *+1 wait for it and 2A6 42CF005B37C0000FF0 2214 IP POP DIDNTPOP 2A7 42CC000B37D02A92A8 2215 *+2,PUSH *+1 2A8 42CF005B37C0000FF0 2216 IP POP DIDNTPOP 2A9 42CC000B37D029E2AA 2217 DO1FLOOP,P *+1 then allow the IBF interrupt 2AA 42CF005B37C0000FF0 2218 IP POP DIDNTPOP 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 61 PPU3/REV 25 microcode | CPU Write processor 2220 2221 ***************************************************************************************************** 2222 * The first part of this routine (down to TESTDIR2) ensures * 2223 * that the input data is okay. The byte count that was written * 2224 * must not be zero, and if the LAST bit is not set, it must be a * 2225 * multiple of 4. If these conditions are not met, we will do a * 2226 * bad data to a pseudo address bus error. * 2227 ***************************************************************************************************** 2228 2229 SKIPORG 2230 >>>>>>>>>> 2AC 40CCA2EB6060402AF0 2231 > I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA BC zero, cockpit error 2AD 48CBC06AFFC8000AAF 2232 >LDBC2 I SCR2 AND LIT LASTBIT SKIP *+2 not zero, last BC? 2233 >>>>>>>>>> 2AE CAC80DEAD060000A9F 2234 > I,X1 SCR2 RAM LAST2 TESTDIR2 yes, anything else is OK 2AF 48CBA06AFFCFFFCAB0 2235 > I SCR2 IOR LIT #FFFC SKIP no, a multiple of 4? 2236 >>>>>>>>>> 2B0 40CCA2EB6060402AF0 2237 > I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA no, unacceptable data 2B1 CAC80DEAD060000A9F 2238 > I,X1 SCR2 RAM LAST2 TESTDIR2 yes, go test DMA direction 2239 >>>>>>>>>> 2240 STARTSKP 29F 40CFC2EB6FE0001AB2 2241$ TESTDIR2 I,X1 LIT AND RAM PRTST DMADIR SKIP DIRISIN2 test DMA direction 2242 >>>>>>>>>> 2B2 40DCCDEB6167FFC2CF 2243 >DIRISIN2 STC,X1 LIT AND RAM SCR0 LAST2 #7FFC READBC2 read, go process 2B3 40CC6DEB616FFFFAAB 2244 > I,X1 LIT ADD RAM SCR0 LAST2 -1 TESTODD2 write 2245 >>>>>>>>>> 2247 ***************************************************************************************************** 2248 *DIRECTION IS OUTPUT * 2249 ***************************************************************************************************** 2250 STARTSKP 2AB 40CFCEEB6FE0001AB4 2251$ TESTODD2 I,X1 LIT AND RAM LADDR2 1 SKIP NOTODD2 need to fetch odd address? 2252 >>>>>>>>>> 2B4 C0D8C06AF147FF82BA 2253 >NOTODD2 STC SCR0 AND LIT SCR0 #7FF8 WRITEBC2 no, go process 2B5 C0CBA06AFFC8003AB7 2254 > I SCR0 IOR LIT #8003 SKIP *+2 yes, BC>4? 2255 >>>>>>>>>> 2B6 40CC0D6B7060000ABD 2256 > I,X1 ZERO RAM BCNT2 WRITEB2A no, setup for single word tr 2B7 40CC6DEB616FFFBAB8 2257 > I,X1 LIT ADD RAM SCR0 LAST2 -5 yes, process 2258 >>>>>>>>>> 2259 2B8 C0C8C06AF147FF8AB9 2260 I SCR0 AND LIT SCR0 #7FF8 2B9 40D8606AF1400042BA 2261 STC SCR0 ADD LIT SCR0 4 2BA 40E82DEAE0600002BB 2262 WRITEBC2 TWC,X1 SCR0 RSUB RAM RAM LAST2 adjust LAST for remainder 2BB 42C80D6AD060000ABC 2263 I,X1 SCR0 RAM BCNT2 2BC 40CC09EB7060000ABD 2264 I,X1 ZERO RAM CORBC set the BC correction count 2BD 40CFC2EB6FE0040ABE 2265 WRITEB2A I,X1 LIT AND RAM PRTST BCNRDY SKIP WRITEB2B waiting for BCNT? 2266 SKIPORG 2267 >>>>>>>>>> 2BE 40CCE96B70600001EA 2268 >WRITEB2B X1 ONES RAM BCOVERUN DECIBF no, we now have the next BC 2BF 40CC82EB6060040AC0 2269 > I,X1 LIT XOR RAM RAM PRTST BCNRDY yes, indicate it's here 2270 >>>>>>>>>> 2271 2C0 C2CC0D636160000AC1 2272 I,X1 RAM SCR0 BCNT2 and move the rest of 2C1 42C80AEAD060000AC2 2273 I,X1 SCR0 RAM BCNT the parameters over 2C2 C2C803EAD060000AC3 2274 I,X1 SCR0 RAM CLKFIX save for clock fixing 2C3 C2CC0E636160000AC4 2275 I,X1 RAM SCR0 HADDR2 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 62 PPU3/REV 25 microcode | CPU Write processor 2C4 82C80BEAD060000AC5 2276 I,X1,P SCR0 RAM HADDR 2C5 42CC0CE36160000AC6 2277 I,X1 RAM SCR0 SLOT2 2C6 C2C80A6AD060000AC7 2278 I,X1 SCR0 RAM SLOT 2C7 42CC0DE36160000AC8 2279 I,X1 RAM SCR0 LAST2 2C8 C2C80B6AD060000AC9 2280 I,X1 SCR0 RAM LAST 2C9 C2CC0EE36160000ACA 2281 I,X1 RAM SCR0 LADDR2 2CA 40CFCEEB6FE0001ACC 2282 I,X1 LIT AND RAM LADDR2 1 SKIP WB2NOT1W need to do a single fetch? 2283 SKIPORG 2284 >>>>>>>>>> 2CC 02C80C6AD060000ACE 2285 >WB2NOT1W I,X1,P SCR0 RAM LADDR WB2INTSON no, exit 2CD 82C80C6AD860000760 2286 > X1,P SCR0 RAM LADDR INDX WB2O1WIP yes, set vector & exit 2287 >>>>>>>>>> 2289 BLOCK 4,WB2O1WIOR 2290 >>>>>>>>>> 760 42CC0E6B52600402CE 2291 >WB2O1WIP X1 LIT IADR PRT0IADR FOUTI1W WB2INTSON set output- port 0 761 C2CC0C6B52600402CE 2292 > X1 LIT IADR PRT1IADR FOUTI1W WB2INTSON 762 C2CC0A6B52600402CE 2293 > X1 LIT IADR PRT2IADR FOUTI1W WB2INTSON 763 42CC086B52600402CE 2294 > X1 LIT IADR PRT3IADR FOUTI1W WB2INTSON set output- port 3 2295 >>>>>>>>>> 2296 ENDBLOCK 2297 2CE E0C881EAE1600009EA 2298 WB2INTSON I,X1 SCR8 XOR RAM SCR8 PBITIM DECIBF allow interrupts (load in DEC 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 63 PPU3/REV 25 microcode | CPU Write processor 2300 2301 ***************************************************************************************************** 2302 *DIRECTION IS INPUT * 2303 ***************************************************************************************************** 2304 2305 2CF C0E82DEAE0600002D0 2306 READBC2 TWC,X1 SCR0 RSUB RAM RAM LAST2 adjust LAST2 for remainder 2D0 C0C86D6AF06FFFCAD1 2307 I,X1 SCR0 ADD LIT RAM BCNT2 -4 2D1 C2CC09EB5060004AD2 2308 I,X1 LIT RAM CORBC 4 set the BC correction count 2D2 40CFC2EB6FE0040AD4 2309 I,X1 LIT AND RAM PRTST BCNRDY SKIP READB2B waiting for BCNT? 2310 SKIPORG 2311 >>>>>>>>>> 2D4 40CCE96B70600001EA 2312 >READB2B X1 ONES RAM BCOVERUN DECIBF no, we now have the next BC 2D5 C0CC82EB6060040AD6 2313 > I,X1 LIT XOR RAM RAM PRTST BCNRDY yes, indicate it's here 2314 >>>>>>>>>> 2D6 42CC0E636160000AD7 2315 I,X1 RAM SCR0 HADDR2 and move the rest of 2D7 82C80BEAD060000AD8 2316 I,X1,P SCR0 RAM HADDR the parameters over 2D8 42CC0EE36160000AD9 2317 I,X1 RAM SCR0 LADDR2 2D9 02C80C6AD060000ADA 2318 I,X1,P SCR0 RAM LADDR 2DA 42CC0CE36160000ADB 2319 I,X1 RAM SCR0 SLOT2 2DB C2C80A6AD060000ADC 2320 I,X1 SCR0 RAM SLOT 2DC C2CC0DE36160000ADD 2321 I,X1 RAM SCR0 LAST2 2DD C2C80B6AD060000ADE 2322 I,X1 SCR0 RAM LAST 2DE C2CC0D636160000ADF 2323 I,X1 RAM SCR0 BCNT2 2DF 42C80AEAD060000AE0 2324 I,X1 SCR0 RAM BCNT 2E0 C2C803EAD060000AE1 2325 I,X1 SCR0 RAM CLKFIX save for timer fixing 2E1 40CFCD6B6FE8000AE3 2326 I,X1 LIT AND RAM BCNT2 #8000 SKIP B2LISBIG if BC < 4, then 2327 >>>>>>>>> 2328 SKIPORG 2329 >>>>>>>>>> 2E2 40CCA2EB60600809EA 2330 > I,X1 LIT IOR RAM RAM PRTST DMANBZ DECIBF indicate FIFO done 2E3 E0C881EAE1600009EA 2331 >B2LISBIG I,X1 SCR8 XOR RAM SCR8 PBITIM DECIBF allow interrupts 2332 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 64 PPU3/REV 25 microcode | CPU Write processor 2334 2335 ***************************************************************************************************** 2336 * * 2337 * This part sets up the SLOT, HADDR, and LADDR variables. * 2338 * These variables are stored into SBCB, SBHC, and SBLC * 2339 * (respectively) when the PPU does transfers. They are set up * 2340 * for double word reads for the output direction and for single * 2341 * data word writes for the input direction. XOR constants are * 2342 * used to change these values to single word reads when needed. * 2343 * * 2344 ***************************************************************************************************** 2345 2346 2E4 C0CCD66B6160F00AE5 2347 ADDIR I,X1 LIT AND RAM SCR0 TEMP #0F00 CKDIR get slot number 2348 STARTSKP 2E5 C0CFC2EB6FE0001AE6 2349 CKDIR I,X1 LIT AND RAM PRTST DMADIR SKIP DIRISRD figure direction 2350 >>>>>>>>>> 2E6 C0CBA05AF148063FF0 2351 >DIRISRD I SCR0 IOR LIT SCR0 WRITBITS POP DIDNTPOP write into memory 2E7 C0CBA05AF14B02DFF0 2352 > I SCR0 IOR LIT SCR0 READBITS POP DIDNTPOP read from memory 2353 >>>>>>>>>> 2E8 40C8CA6AF068FFFAE9 2355 LDMA1 I,X1 SCR0 AND LIT RAM SLOT #8FFF set bus control 2E9 424C16636160000AEA 2356 I,X1 RAM SCR0,L TEMP 2EA 80C8CBEAF0630FFAEB 2357 I,X1,P SCR0 AND LIT RAM HADDR #30FF set command word 2EB 8AC80C6AD0600009EA 2358 I,X1,P SCR2 RAM LADDR DECIBF 2359 2360 2EC 40C8CCEAF068FFFAED 2361 LDMA2 I,X1 SCR0 AND LIT RAM SLOT2 #8FFF set destination 2ED C24C16636160000AEE 2362 I,X1 RAM SCR0,L TEMP fix up command word 2EE 40C8CE6AF0630FFAEF 2363 I,X1 SCR0 AND LIT RAM HADDR2 #30FF 2EF 4AC80EEAD0600009EA 2364 I,X1 SCR2 RAM LADDR2 DECIBF 2365 2F0 EECC006B514D0001E5 2366 BADDATA LIT SCRB #D000 BADCOMM illegal data, assert BE 2367 TITLE.MAC Call Back Needed Interrupt processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 65 PPU3/REV 25 microcode | Call Back Needed Interrupt processor 2368 ***************************************************************************************************** 2369 * * 2370 * Call Back Needed interrupt routine. * 2371 * * 2372 ***************************************************************************************************** 2374 VECTOR 2375 >>>>>>>>>> 020 42CC002B52800042F6 2376 >CBNINT LIT SBRFI RFIOUT CBNINT1 RTO cleared, start call back 021 42CC002B52800042F6 2377 > LIT SBRFI RFIOUT CBNINT1 RTO cleared, start call back 022 42CC002B52800042F6 2378 > LIT SBRFI RFIOUT CBNINT1 RTO cleared, start call back 023 42CC002B52800042F6 2379 > LIT SBRFI RFIOUT CBNINT1 RTO cleared, start call back 024 42CC002B52800042F6 2380 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back anyway 025 42CC002B52800042F6 2381 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back anyway 026 42CC002B52800042F6 2382 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back anyway 027 42CC002B52800042F6 2383 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back anyway 028 42CC006D31507F32F5 2384 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 029 42CC006D31507F32F5 2385 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 02A 42CC006D31507F32F5 2386 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 02B 42CC006D31507F32F5 2387 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 02C 42CC006D31507F32F5 2388 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 02D 42CC006D31507F32F5 2389 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 02E 42CC006D31507F32F5 2390 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 02F 42CC006D31507F32F5 2391 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go DIE! 2392 >>>>>>>>>> 2393 ENDVECTOR 2F1 6ECC006B5141000325 2395 PEGODIE LIT SCRB #1000 SAVEIBF 2F2 6ECC006B5142000325 2396 BFGODIE LIT SCRB #2000 SAVEIBF 2F3 EECC006B5145000325 2397 RTOGODIE LIT SCRB #5000 SAVEIBF 2F4 EECC006B5146000325 2398 RESGODIE LIT SCRB #6000 SAVEIBF 2F5 6ECC006B514B000325 2399 CONGODIE LIT SCRB #B000 SAVEIBF 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 66 PPU3/REV 25 microcode | Call Back Needed Interrupt processor 2401 2402 ***************************************************************************************************** 2403 * We come here when someone has attempted to send us * 2404 * something on the bus and we are accepting CBN interrupts. * 2405 * We will set RFI then wait for the data to show up. * 2406 * We will place it into a circular buffer of such requests * 2407 * unless it is an interrupt poll, which we will service * 2408 * directly. * 2409 ***************************************************************************************************** 2410 2F6 FAC8002AD3400002F7 2411 CBNINT1 SCRE INDX2 address RAM 2F7 60C8A06AF1400102F8 2412 SCR8 IOR LIT SCR8 CBNIM temp. mask off CBN intr 2F8 E2C8002AD5C00002F9 2413 SCR8 IMR (since it must come from sour 2F9 60C8806AF1400102FA 2414 SCR8 XOR LIT SCR8 CBNIM and restore scr8 2FA 6CC8606AF1400012FB 2415 SCRB ADD LIT SCRB 1 set 'New BUS Transfer' 2FB C2CC11EB504007D2FE 2416 X2 LIT RAM BIST CBNTO CINOTIBF and setup a CBN time-out 2417 STARTSKP 2CB C0CF71EB684FFFF2FD 2418$ CICKTO X2 LIT ADD RAM RAM BIST -1 SKIP CINOTTO time-out? 2419 >>>>>>>>>> 2FC 42CC006D31507F22F4 2420 > SBST SCR0 CIRESERR,P RESGODIE yes, go DIE! 2FD F0CBC06AFFC00402FE 2421 >CINOTTO SCRC AND LIT IBF SKIP CINOTIBF no, IBF? 2422 >>>>>>>>>> 2FE F2CC006D31400002CB 2423 >CINOTIBF SBST SCRC CICKTO get S-BUS status again 2FF C2CC11ED3040000300 2424 > X2 SBST RAM BIST yes, save input data 2425 >>>>>>>>>> 300 C2CC0F6DF040000301 2426 X2 SBHC RAM BIHC fetch the first word 301 C2CC0FEE7040000302 2427 X2 SBLC RAM BILC ...into the current buffer 302 42CC116FB040000303 2428 X2 SBFT RAM BIFT ...and slot info too 2429 303 70CCD1EB61470302D3 2430 X2 LIT AND RAM SCRC BIST FLAGMASK CICKDWT isolate flags for test 2431 STARTSKP 2D3 C0CFD1EB6FC0080304 2432$ CICKDWT X2 LIT AND RAM BIST DWTIN SKIP CINOTDWT Double Word Transfer? 2433 >>>>>>>>>> 304 70C8606AF14DFE0309 2434 >CINOTDWT SCRC ADD LIT SCRC -COMMCOMM CIPROCSW (single word) 305 F0C8606AF14DFF0306 2435 > SCRC ADD LIT SCRC -COMMDATA (double word) 2436 >>>>>>>>>> 306 42CC106EF040000307 2437 > X2 SBHD RAM BIHD this is double word, so 307 C2CC10EF7040000308 2438 > X2 SBLD RAM BILD ...get the second word 308 70CBA06AFFC000030A 2439 > SCRC IOR LIT 0 SKIP CINOTDAT DWT, good Command & Data? 2440 > 309 70CBA06AFFC000030C 2441 >CIPROCSW SCRC IOR LIT 0 SKIP CINOTCOM single, good Command? 2442 > SKIPORG 2443 >>>>>>>>>> 30A 40CFD1EB6FC400031E 2444 >CINOTDAT X2 LIT AND RAM BIST BPE SKIP CINOTBPE no, die! 30B F4CBC06AFFC0003322 2445 > SCRD AND LIT 3 SKIP CIEXIT clear RFI? 2446 >>>>>>>>>> 30C 40CFD1EB6FC400031E 2447 >CINOTCOM X2 LIT AND RAM BIST BPE SKIP CINOTBPE no, die! 30D 70CC8F6B614600030E 2448 > X2 LIT XOR RAM SCRC BIHC #6000 CICKPOL check for Interrupt Poll 2449 >>>>>>>>>> 2450 STARTSKP 30E F0CBA06AFFC0000310 2451$ CICKPOL SCRC IOR LIT 0 SKIP CINOTPOL 2452 >>>>>>>>>> 310 F4CBC06AFFC0003322 2453 >CINOTPOL SCRD AND LIT 3 SKIP CIEXIT not a Poll- clear RFI? 311 F1CCD16B614000F312 2454 > X2 LIT AND,X RAM SCRC BIFT #000F get FROM slot # 2455 >>>>>>>>>> 312 F0C8A06AF140011313 2456 SCRC IOR LIT SCRC RTODATA CICKUS output Poll response 2457 STARTSKP 313 DCCBA06AFFC0000314 2458 CICKUS SCR7 IOR LIT 0 SKIP CIISUS are we interrupting? 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 67 PPU3/REV 25 microcode | Call Back Needed Interrupt processor 2459 >>>>>>>>>> 314 5EC8000AD400000318 2460 >CIISUS SCR7 SBHC CIOURPOL say it's us, send the port # 315 C2CC000B5400000316 2461 > LIT SBHC 0 no, give negative response 2462 >>>>>>>>>> 316 C2CC000B5440000317 2463 LIT SBLC 0 317 72C8002AD54000016E 2464 SCRC SBCB RTODELAY & exit 2465 318 5EC8002AD340000319 2466 CIOURPOL SCR7 INDX2 and send the current 319 C2CC0283644000031A 2467 X2 RAM SBLC PRTST port status 31A 72C8002AD54000031B 2468 SCRC SBCB 31B 40CCC2EB604E7FF31C 2469 X2 LIT AND RAM RAM PRTST INTCLR clear everything up 31C 42CC002B518000031D 2470 LIT SBINT 0 31D 5ECF005B5140000FF0 2471 I LIT SCR7 0 POP DIDNTPOP & exit 2472 2473 SKIPORG 2474 >>>>>>>>>> 31E 6ECC006B5142000320 2475 >CINOTBPE LIT SCRB #2000 *+2 other bus error (wrong flags) 31F 6ECC006B5141000320 2476 > LIT SCRB #1000 bus parity error 2477 >>>>>>>>>> 320 7AC8000AD4D07F432C 2478 SCRE INDX1 CIINPERR,P WTFORPON 2480 SKIPORG 2481 >>>>>>>>>> 322 74C8606AF140001324 2482 >CIEXIT SCRD ADD LIT SCRD 1 CIEXIT1 allow more inputs 323 60C8A06AF140010322 2483 > SCR8 IOR LIT SCR8 CBNIM CIEXIT all filled up, clear RFI 2484 >>>>>>>>>> 324 78CB605AF140001FF0 2485 CIEXIT1 I SCRE ADD LIT SCRE 1 POP DIDNTPOP 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 68 PPU3/REV 25 microcode | Call Back Needed Interrupt processor 2487 2488 ***************************************************************************************************** 2489 * * 2490 * Bus error garbage * 2491 * * 2492 ***************************************************************************************************** 2493 325 7AC8002AD4C0000326 2494 SAVEIBF SCRE INDX1 address the RAM 326 C2C811EAD060000327 2495 X1 SCR0 RAM BIST save input data 327 C2CC0F6DF060000328 2496 X1 SBHC RAM BIHC 328 42CC0FEE7060000329 2497 X1 SBLC RAM BILC 329 C2CC106EF06000032A 2498 X1 SBHD RAM BIHD 32A C2CC10EF706000032B 2499 X1 SBLD RAM BILD 32B 42CC116FB06000032C 2500 X1 SBFT RAM BIFT WTFORPON 2501 32C C2CC002B534000032D 2502 WTFORPON LIT INDX2 0 move the BUS Inputs to the 32D ECC8D36AF04F00032E 2503 X2 SCRB AND LIT RAM WRURES2A #F000 WRU responses. 32E C0CCD1EB6160F0032F 2504 X1 LIT AND RAM SCR0 BIST #0F00 32F C0C8B36AE040000330 2505 X2 SCR0 IOR RAM RAM WRURES2A 330 40CCD16B61600FF331 2506 X1 LIT AND RAM SCR0 BIFT #00FF 331 40C8B36AE040000332 2507 X2 SCR0 IOR RAM RAM WRURES2A 332 C0CCD1EB61630BF333 2508 X1 LIT AND RAM SCR0 BIST #30BF 333 42C813EAD040000334 2509 X2 SCR0 RAM WRURES2B 334 C0CCD16B6160F00335 2510 X1 LIT AND RAM SCR0 BIFT #0F00 335 40C8B3EAE040000336 2511 X2 SCR0 IOR RAM RAM WRURES2B 336 42CC0F636160000337 2512 X1 RAM SCR0 BIHC 337 42C8146AD040000338 2513 X2 SCR0 RAM WRURES3A 338 42CC0FE36160000339 2514 X1 RAM SCR0 BILC 339 42C814EAD04000033A 2515 X2 SCR0 RAM WRURES3B 33A C2CC1063616000033B 2516 X1 RAM SCR0 BIHD 33B 42C8156AD04000033C 2517 X2 SCR0 RAM WRURES4A 33C 42CC10E3616000033D 2518 X1 RAM SCR0 BILD 33D 42C815EAD04000033E 2519 X2 SCR0 RAM WRURES4B 33E 42CC006B31C000033F 2520 T4 SBRST then save the output register 33F C2CC002B5340001340 2521 LIT INDX2 1 340 C2CC006FB140000341 2522 SBFT SCR0 get our slot number 341 C1C8C06AF14F000342 2523 SCR0 AND,X LIT SCR0 #F000 342 C2C8166AD070343215 2524 X1 SCR0 RAM TEMP *+1,PUSH SHIFTL4 343 C0C8A06AF14009B344 2525 SCR0 IOR LIT SCR0 COPYTOME 344 C2C8002AD540000345 2526 SCR0 SBCB start the transfer 345 C2CC006B514007D348 2527 X2 LIT SCR0 CTMTO CTMNIBF and setup a time-out 2528 STARTSKP 30F C0CB606AF94FFFF347 2529$ CTMCKTO SCR0 ADD LIT SCR0 -1 SKIP CTMNOTTO time-out? 2530 >>>>>>>>>> 346 C2CC002B37C000034D 2531 > CKBSE yes, skip it! 347 F0CBC06AFFC0040348 2532 >CTMNOTTO SCRC AND LIT IBF SKIP CTMNIBF no, IBF? 2533 >>>>>>>>>> 348 F2CC006D314000030F 2534 >CTMNIBF SBST SCRC CTMCKTO get S-BUS status again 349 C2CC126DF04000034A 2535 > X2 SBHC RAM WRURES1A yes, save input data 2536 >>>>>>>>>> 34A 42CC12EE704000034B 2537 X2 SBLC RAM WRURES1B 34B 42CC136EF04000034C 2538 X2 SBHD RAM WRURES2A 34C 42CC13EF704000034D 2539 X2 SBLD RAM WRURES2B CKBSE 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 69 PPU3/REV 25 microcode | Call Back Needed Interrupt processor 2541 2542 STARTSKP 34D ECCBA06AFFC000034E 2543 CKBSE SCRB IOR LIT 0 SKIP ISBSE should we pull on BSE 2544 >>>>>>>>>> 34E C2CC002B554200034F 2545 >ISBSE LIT SBCB BSE yes, assert BUS ERROR 34F C2CC002B37C0000350 2546 > NOP 2547 >>>>>>>>>> 2548 350 42CC002B54C0000351 2549 LIT INDX1 0 now save all the Byte 351 C2CC002B5340001352 2550 LIT INDX2 1 Counts and Addresses 352 42CC000B37D035336B 2551 *+1,PUSH GETFLAGS 353 42C8146AD040000354 2552 X2 SCR0 RAM WRURES3A 354 C6C814EAD040000355 2553 X2 SCR1 RAM WRURES3B 355 CAC8156AD040000356 2554 X2 SCR2 RAM WRURES4A 356 4EC815EAD040000357 2555 X2 SCR3 RAM WRURES4B 2556 357 C2CC002B54C0001358 2557 LIT INDX1 1 358 42CC002B5340002359 2558 LIT INDX2 2 359 42CC000B37D035A36B 2559 *+1,PUSH GETFLAGS 35A 42C8126AD04000035B 2560 X2 SCR0 RAM WRURES1A 35B C6C812EAD04000035C 2561 X2 SCR1 RAM WRURES1B 35C 4AC8136AD04000035D 2562 X2 SCR2 RAM WRURES2A 35D 4EC813EAD04000035E 2563 X2 SCR3 RAM WRURES2B 2564 35E 42CC002B54C000235F 2565 LIT INDX1 2 35F 42CC000B37D036036B 2566 *+1,PUSH GETFLAGS 360 42C8146AD040000361 2567 X2 SCR0 RAM WRURES3A 361 46C814EAD040000362 2568 X2 SCR1 RAM WRURES3B 362 CAC8156AD040000363 2569 X2 SCR2 RAM WRURES4A 363 4EC815EAD040000364 2570 X2 SCR3 RAM WRURES4B 2571 364 C2CC002B54C0003365 2572 LIT INDX1 3 365 C2CC002B5340003366 2573 LIT INDX2 3 366 C2CC000B37D036736B 2574 *+1,PUSH GETFLAGS 367 42C8126AD040000368 2575 X2 SCR0 RAM WRURES1A 368 C6C812EAD040000369 2576 X2 SCR1 RAM WRURES1B 369 CAC8136AD04000036A 2577 X2 SCR2 RAM WRURES2A 36A 4ECB13FAD04000036A 2578 X2 SCR3 RAM WRURES2B POP * That's it! Go die!!! 36B 41CCCA6B6160F0036C 2580 GETFLAGS X1 LIT AND,X RAM SCR0 SLOT #0F00 get the slot number, 36C C2C8166AD07036D215 2581 X1 SCR0 RAM TEMP *+1,PUSH SHIFTL4 36D C4CCCBEB616000F36E 2582 X1 LIT AND RAM SCR1 HADDR #000F some of the high address 36E 46C8166AD06000036F 2583 X1 SCR1 RAM TEMP 36F 40C8B66AE160000370 2584 X1 SCR0 IOR RAM SCR0 TEMP 370 C28C02636160000371 2585 X1 RAM SCR0,H FLAGS and the flags 2586 371 46CC0C636160000372 2587 X1 RAM SCR1 LADDR 372 CACC02E36160000373 2588 X1 RAM SCR2 PRTST 373 4ECF0AF361600007F0 2589 X1 RAM SCR3 BCNT POP DIDNTPOP 2590 TITLE.MAC FIFO Input processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 70 PPU3/REV 25 microcode | FIFO Input processor 2591 2592 ***************************************************************************************************** 2593 * * 2594 * FIFO input interrupt processor * 2595 * * 2596 ***************************************************************************************************** 2598 BLOCK 4,INPIOR 2599 >>>>>>>>>> 764 C2CF0E7B52600307F0 2600 >FISETINT X1 LIT IADR PRT0IADR FINPINT POP DIDNTPOP set input- port 0 765 42CF0C7B52600307F0 2601 > X1 LIT IADR PRT1IADR FINPINT POP DIDNTPOP 766 42CF0A7B52600307F0 2602 > X1 LIT IADR PRT2IADR FINPINT POP DIDNTPOP 767 C2CF087B52600307F0 2603 > X1 LIT IADR PRT3IADR FINPINT POP DIDNTPOP set input- port 3 2604 >>>>>>>>>> 2605 ENDBLOCK 2607 ***************************************************************************************************** 2608 * * 2609 * If the POP's in the FIFO interrupt tables prove to be a problem (at * 2610 * least one interruptable instruction must be executed before the * 2611 * interrupt will take place again), the POP's may be made interruptable. * 2612 * This will cause the POP to be executed repeatedly until RTO goes away. * 2613 * The short path to take one word of data from the controller * 2614 * and write it to memory takes 18 ticks (1.2 usec) for one word. * 2615 * * 2616 ***************************************************************************************************** 2618 VECTOR 2619 >>>>>>>>>> 030 02C40BA36400000374 2620 >FINPINT X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WRITE 031 02C40BA36400000374 2621 > X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WRITE 032 02C40BA36400000374 2622 > X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WRITE 033 02C40BA36400000374 2623 > X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WRITE 034 42CF005B37C0000FF0 2624 > IP POP DIDNTPOP RTO set, wait for it 035 42CF005B37C0000FF0 2625 > IP POP DIDNTPOP RTO set, wait for it 036 42CF005B37C0000FF0 2626 > IP POP DIDNTPOP RTO set, wait for it 037 42CF005B37C0000FF0 2627 > IP POP DIDNTPOP RTO set, wait for it 038 42CC006D31507F52F5 2628 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 039 42CC006D31507F52F5 2629 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 03A 42CC006D31507F52F5 2630 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 03B 42CC006D31507F52F5 2631 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 03C 42CC006D31507F52F5 2632 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 03D 42CC006D31507F52F5 2633 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 03E 42CC006D31507F52F5 2634 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 03F 42CC006D31507F52F5 2635 > SBST SCR0 FINPERR,P CONGODIE BUS Parity Error, go DIE! 2636 >>>>>>>>>> 2637 ENDVECTOR 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 71 PPU3/REV 25 microcode | FIFO Input processor 2639 2640 374 82CC0C236440000375 2641 FIWRITE X2,P RAM SBLC LADDR complete the WRITE 375 C2CC00287380000376 2642 X2,T2 DPIN SBHD 376 42CC0A236540000377 2643 X2 RAM SBCB SLOT 377 C2CC002873C0000321 2644 X2,T2 DPIN SBLD FICKEND 2645 STARTSKP 321 C0CF6AEB684FFFC378 2646$ FICKEND X2 LIT ADD RAM RAM BCNT -4 SKIP FIEXIT decrement BC & check for end 2647 >>>>>>>>>> 378 80CF6C5B6040001FF0 2648 >FIEXIT I,X2,P LIT ADD RAM RAM LADDR 1 POP DIDNTPOP not end, inc address and exit 379 00CC6C6B604000137A 2649 > X2,P LIT ADD RAM RAM LADDR 1 FICKLAST make sure the address is righ 2650 >>>>>>>>>> 2651 STARTSKP 37A C0CFCB6B6FC800037C 2652$ FICKLAST X2 LIT AND RAM LAST LASTBIT SKIP FINOTEND end, last BC? 2653 >>>>>>>>>> 37C C0CFA96B6FC0000383 2654 >FINOTEND X2 LIT IOR RAM BCOVERUN 0 SKIP FINEXTBC no, overrun? 37D 60C8A1EAE14000037E 2655 >FIEND X2 SCR8 IOR RAM SCR8 PBITIM yes,disallow interrupts 2656 >>>>>>>>>> 37E E2C8002AD5C000037F 2657 SCR8 IMR 37F 40CFA2DB6040080FF0 2658 IP,X2 LIT IOR RAM RAM PRTST DMANBZ POP DIDNTPOP set FIFO not busy 380 62C8002AD5C0000381 2660 FIORUN SCR8 IMR 381 C0CFA2DB6040050FF0 2661 IP,X2 LIT IOR RAM RAM PRTST OVRRUN POP DIDNTPOP say waiting & exit 2662 2663 SKIPORG 2664 >>>>>>>>>> 382 E0C8A1EAE140000380 2665 > X2 SCR8 IOR RAM SCR8 PBITIM FIORUN byte count not ready, ints of 383 40CCA2EB6040010384 2666 >FINEXTBC X2 LIT IOR RAM RAM PRTST BCROLL no, signal BC rollover 2667 >>>>>>>>>> 384 C0CC096B7040000385 2668 X2 ZERO RAM BCOVERUN set overrun detector, 385 72CC0E636140000386 2669 X2 RAM SCRC HADDR2 and move the rest of 386 32C80BEAD040000387 2670 X2,P SCRC RAM HADDR the parameters over 387 72CC0EE36140000388 2671 X2 RAM SCRC LADDR2 388 B2C80C6AD040000389 2672 X2,P SCRC RAM LADDR 389 72CC0CE3614000038A 2673 X2 RAM SCRC SLOT2 38A F2C80A6AD04000038B 2674 X2 SCRC RAM SLOT 38B F2CC0DE3614000038C 2675 X2 RAM SCRC LAST2 38C 72C80B6AD04000038D 2676 X2 SCRC RAM LAST 38D F2CC0D63614000038E 2677 X2 RAM SCRC BCNT2 check the new BC for too smal 38E F2C803EAD04000038F 2678 X2 SCRC RAM CLKFIX FICKBC set clock adjuster 2679 STARTSKP 38F C0CFCD6B6FC8000391 2680 FICKBC X2 LIT AND RAM BCNT2 #8000 SKIP FIISBIG if BC < 4, then 2681 >>>>>>>>>> 390 72C80AEAD04000037D 2682 > X2 SCRC RAM BCNT FIEND don't allow interrupt 391 72CB0ADAD040000FF0 2683 >FIISBIG I,X2 SCRC RAM BCNT POP DIDNTPOP otherwise, continue 2684 >>>>>>>>>> 2685 TITLE.MAC FIFO Output processor 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 72 PPU3/REV 25 microcode | FIFO Output processor 2686 2687 ***************************************************************************************************** 2688 * * 2689 * FIFO output interrupt processor - Single Word Fetch. * 2690 * * 2691 ***************************************************************************************************** 2693 BLOCK 8,OUT1WIOR 2694 >>>>>>>>>> 750 C2CF0E7B52400407F0 2695 >FOSETI1W LIT IADR PRT0IADR FOUTI1W POP DIDNTPOP set output- port 0 751 42CF0C7B52400407F0 2696 > LIT IADR PRT1IADR FOUTI1W POP DIDNTPOP 752 42CF0A7B52400407F0 2697 > LIT IADR PRT2IADR FOUTI1W POP DIDNTPOP 753 C2CF087B52400407F0 2698 > LIT IADR PRT3IADR FOUTI1W POP DIDNTPOP set output- port 3 754 C2CF0E5B5240040FF0 2699 >FOSI1WIP I LIT IADR PRT0IADR FOUTI1W POP DIDNTPOP set output- port 0 755 42CF0C5B5240040FF0 2700 > I LIT IADR PRT1IADR FOUTI1W POP DIDNTPOP 756 42CF0A5B5240040FF0 2701 > I LIT IADR PRT2IADR FOUTI1W POP DIDNTPOP 757 C2CF085B5240040FF0 2702 > I LIT IADR PRT3IADR FOUTI1W POP DIDNTPOP set output- port 3 2703 >>>>>>>>>> 2704 ENDBLOCK 2706 VECTOR 2707 >>>>>>>>>> 040 C0C48BEB6401000392 2708 >FOUTI1W X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start READ 041 C0C48BEB6401000392 2709 > X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start READ 042 C0C48BEB6401000392 2710 > X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start READ 043 C0C48BEB6401000392 2711 > X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start READ 044 42CF005B37C0000FF0 2712 > IP POP DIDNTPOP RTO set, wait for it 045 42CF005B37C0000FF0 2713 > IP POP DIDNTPOP RTO set, wait for it 046 42CF005B37C0000FF0 2714 > IP POP DIDNTPOP RTO set, wait for it 047 42CF005B37C0000FF0 2715 > IP POP DIDNTPOP RTO set, wait for it 048 42CC006D31507F62F5 2716 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 049 42CC006D31507F62F5 2717 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 04A 42CC006D31507F62F5 2718 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 04B 42CC006D31507F62F5 2719 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 04C 42CC006D31507F62F5 2720 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 04D 42CC006D31507F62F5 2721 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 04E 42CC006D31507F62F5 2722 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 04F 42CC006D31507F62F5 2723 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 2724 >>>>>>>>>> 2725 ENDVECTOR 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 73 PPU3/REV 25 microcode | FIFO Output processor 2727 2728 392 C2CC0C636C40000768 2729 FOREAD1W X2 RAM SBLC LADDR INDX FOSETIN2 setup for Double Word Fetches 2731 BLOCK 4,OUTIOR2 2732 >>>>>>>>>> 768 42CC0E6B5240050393 2733 >FOSETIN2 LIT IADR PRT0IADR FOUTINT FOSBCB1W set output- port 0 769 C2CC0C6B5240050393 2734 > LIT IADR PRT1IADR FOUTINT FOSBCB1W 76A C2CC0A6B5240050393 2735 > LIT IADR PRT2IADR FOUTINT FOSBCB1W 76B 42CC086B5240050393 2736 > LIT IADR PRT3IADR FOUTINT FOSBCB1W set output- port 3 2737 >>>>>>>>>> 2738 ENDBLOCK 393 40CC8A0B6540004394 2740 FOSBCB1W X2 LIT XOR RAM SBCB SLOT XORFF1W complete the READ 394 C2CC046B5240070395 2741 LIT IADR IBFIADR ONEWORD FOCKND1W & setup for only 1 word 2742 2743 2744 STARTSKP 395 C0CF6AEB684FFFC396 2745 FOCKND1W X2 LIT ADD RAM RAM BCNT -4 SKIP FOEXIT1W decrement BC & check for end 2746 >>>>>>>>>> 396 80CF6C5B6040001FF0 2747 >FOEXIT1W I,X2,P LIT ADD RAM RAM LADDR 1 POP DIDNTPOP not end, inc address & exit 397 C0CFCB6B6FC800039D 2748 > X2 LIT AND RAM LAST LASTBIT SKIP FONLAST end, last BC? 2749 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 74 PPU3/REV 25 microcode | FIFO Output processor 2751 2752 2753 ***************************************************************************************************** 2754 * * 2755 * FIFO output interrupt processor - Double Word Fetch. * 2756 * The short path to set up a fetch from memory takes 14 ticks * 2757 * here (.933 usec). When the data comes in, another interrupt * 2758 * takes more time. * 2759 * * 2760 ***************************************************************************************************** 2762 VECTOR 2763 >>>>>>>>>> 050 82C40BA36400000398 2764 >FOUTINT X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start READ 051 82C40BA36400000398 2765 > X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start READ 052 82C40BA36400000398 2766 > X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start READ 053 82C40BA36400000398 2767 > X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start READ 054 42CF005B37C0000FF0 2768 > IP POP DIDNTPOP RTO set, wait for it 055 42CF005B37C0000FF0 2769 > IP POP DIDNTPOP RTO set, wait for it 056 42CF005B37C0000FF0 2770 > IP POP DIDNTPOP RTO set, wait for it 057 42CF005B37C0000FF0 2771 > IP POP DIDNTPOP RTO set, wait for it 058 42CC006D31507F62F5 2772 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 059 42CC006D31507F62F5 2773 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 05A 42CC006D31507F62F5 2774 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 05B 42CC006D31507F62F5 2775 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 05C 42CC006D31507F62F5 2776 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 05D 42CC006D31507F62F5 2777 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 05E 42CC006D31507F62F5 2778 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 05F 42CC006D31507F62F5 2779 > SBST SCR0 FOUTERR,P CONGODIE BUS Parity Error, go DIE! 2780 >>>>>>>>>> 2781 ENDVECTOR 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 75 PPU3/REV 25 microcode | FIFO Output processor 2783 398 42CC0A236540000399 2784 FOREAD X2 RAM SBCB SLOT complete the READ 399 02CC0C23644000037B 2785 X2,P RAM SBLC LADDR FOCKEND 2786 STARTSKP 37B 40CF6AEB684FFF839A 2787$ FOCKEND X2 LIT ADD RAM RAM BCNT -8 SKIP FOEXIT decrement BC & check for end 2788 >>>>>>>>>> 39A 00C76C5B6040002FF0 2789 >FOEXIT I,X2,P,C LIT ADD RAM RAM LADDR 2 POP DIDNTPOP incr address & exit 39B C0CFCB6B6FC800039D 2790 > X2 LIT AND RAM LAST LASTBIT SKIP FONLAST last BC ? 2791 >>>>>>>>>> 39C C0CFAB6B6FCFFFC3B2 2792 > X2 LIT IOR RAM LAST #FFFC SKIP FOODDBC yes, odd byte count? 39D 40CFCB6B6FC000839F 2793 >FONLAST X2 LIT AND RAM LAST 8 SKIP FOODDWRD not last BC, odd word? 2794 >>>>>>>>>> 2795 ***************************************************************************************************** 2796 * We get to FONOVRN if end of this BCNT (of double words) * 2797 * AND NOT last byte count. The lines from FONOVRN to the line * 2798 * just preceeding FONEXTBC have the effect of choosing whether * 2799 * we will be reading one or two words from memory. (We already * 2800 * sent a double word read to the memory.) * 2801 ***************************************************************************************************** 2802 >>>>>>>>>> 39E 80C46C6B60400023A1 2803 > X2,C,P LIT ADD RAM RAM LADDR 2 FONEXTBC no, adjust the memory address 39F 80CC6C6B60400013A0 2804 >FOODDWRD X2,P LIT ADD RAM RAM LADDR 1 yes, adjust the memory addres 2805 >>>>>>>>>> 3A0 42CC046B52400703A1 2806 LIT IADR IBFIADR ONEWORD & setup for only 1 word 3A1 40CFA96B6FC00003A3 2807 FONEXTBC X2 LIT IOR RAM BCOVERUN 0 SKIP FONOVRN overrun? 2808 2809 SKIPORG 2810 >>>>>>>>>> 3A2 E0C8A1EAE140000380 2811 > X2 SCR8 IOR RAM SCR8 PBITIM FIORUN yes, not ready, ints off 3A3 C0CCA2EB60400103A4 2812 >FONOVRN X2 LIT IOR RAM RAM PRTST BCROLL signal BC rollover 2813 >>>>>>>>>> 3A4 40CC096B70400003A5 2814 X2 ZERO RAM BCOVERUN set overrun detector 3A5 F2CC0D6361400003A6 2815 X2 RAM SCRC BCNT2 and move the rest of 3A6 F2C80AEAD0400003A7 2816 X2 SCRC RAM BCNT the parameters over 3A7 F2C803EAD0400003A8 2817 X2 SCRC RAM CLKFIX set clock adjuster 3A8 F2CC0E6361400003A9 2818 X2 RAM SCRC HADDR2 3A9 32C80BEAD0400003AA 2819 X2,P SCRC RAM HADDR 3AA 72CC0CE361400003AB 2820 X2 RAM SCRC SLOT2 3AB F2C80A6AD0400003AC 2821 X2 SCRC RAM SLOT 3AC F2CC0DE361400003AD 2822 X2 RAM SCRC LAST2 3AD F2C80B6AD0400003AE 2823 X2 SCRC RAM LAST 3AE 72CC0EE361400003AF 2824 X2 RAM SCRC LADDR2 FOCKIF1W 2825 STARTSKP 3AF 40CFCEEB6FC00013B0 2826 FOCKIF1W X2 LIT AND RAM LADDR2 1 SKIP FONOT1W need to do a single fetch? 2827 >>>>>>>>>> 3B0 32CB0C5AD040000FF0 2828 >FONOT1W I,X2,P SCRC RAM LADDR POP DIDNTPOP no, exit 3B1 B2C80C6AD840000754 2829 > X2,P SCRC RAM LADDR INDX FOSI1WIP yes, set vector & exit 2830 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 76 PPU3/REV 25 microcode | FIFO Output processor 2832 2833 SKIPORG 2834 >>>>>>>>>> 3B2 42CC046B52400803BC 2835 >FOODDBC LIT IADR IBFIADR ODDWORD FOODDBC1 yes, setup for it & exit 3B3 40CFCB6B6FC00083B4 2836 > X2 LIT AND RAM LAST 8 SKIP no, double Fetch? 2837 >>>>>>>>>> 3B4 00CC6C6B60400013B6 2838 > X2,P LIT ADD RAM RAM LADDR 1 *+2 no, correct memory address 3B5 80CC6C6B60400023B7 2839 > X2,P LIT ADD RAM RAM LADDR 2 FOLASTBC yes, correct memory address 2840 >>>>>>>>>> 3B6 C2CC046B52400703B7 2841 LIT IADR IBFIADR ONEWORD setup for 1 word 3B7 C0CCA2EB60400B23B8 2842 FOLASTBC X2 LIT IOR RAM RAM PRTST LASTBC signal end and 3B8 E0C8A1EAE1400003B9 2843 X2 SCR8 IOR RAM SCR8 PBITIM disallow interrupts 3B9 E2C8002AD5C00003BA 2844 SCR8 IMR 3BA C0CC0AEB70400003BB 2845 X2 ZERO RAM BCNT zero the byte count 3BB 42CF0B5B5048000FF0 2846 I,X2 LIT RAM LAST LASTBIT POP DIDNTPOP exit, clear last bcnt, set la 2847 3BC F2CC0B6361400003B7 2848 FOODDBC1 X2 RAM SCRC LAST FOLASTBC save this for IBF intrpt rout 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 77 PPU3/REV 25 microcode | FIFO Output processor 2850 2851 2852 ***************************************************************************************************** 2853 * * 2854 * Here if fetching two words (double word fetch) * 2855 * The short path through this code takes 9 ticks (.6 usec) to * 2856 * handle a double word that the memory has handed us. * 2857 * * 2858 ***************************************************************************************************** 2860 VECTOR 2861 >>>>>>>>>> 060 C0CCA2EB6040100061 2862 >TWOWORDS X2 LIT IOR RAM RAM PRTST MPECODE BPE*, RTO* but Abnormal Data 061 C2CC002DF2C00003BD 2863 > X2 SBHC DPOUT TWOWRDS1 BPE*, RTO* and Normal Data 062 42CC006D31507F72F2 2864 > SBST SCR0 MEM1ERR,P BFGODIE BPE*, RTO* but Command Flags 063 42CC006D31507F72F2 2865 > SBST SCR0 MEM1ERR,P BFGODIE BPE*, RTO* but Illegal Flags 064 C2CC006D31507F72F5 2866 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go DIE! 065 C2CC006D31507F72F5 2867 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go DIE! 066 C2CC006D31507F72F5 2868 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go DIE! 067 C2CC006D31507F72F5 2869 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go DIE! 068 42CC006D31507F72F1 2870 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 069 42CC006D31507F72F1 2871 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 06A 42CC006D31507F72F1 2872 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 06B 42CC006D31507F72F1 2873 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 06C 42CC006D31507F72F1 2874 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 06D 42CC006D31507F72F1 2875 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 06E 42CC006D31507F72F1 2876 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 06F 42CC006D31507F72F1 2877 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go DIE! 2878 >>>>>>>>>> 2879 ENDVECTOR 3BD 42CC002E72C00003BE 2881 TWOWRDS1 X2 SBLC DPOUT 3BE 42CC002EF2C00003BF 2882 X2 SBHD DPOUT 3BF 42CF005F72C0000FF0 2883 IP,X2 SBLD DPOUT POP DIDNTPOP & exit 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 78 PPU3/REV 25 microcode | FIFO Output processor 2885 2886 2887 ***************************************************************************************************** 2888 * * 2889 * Here if only fetching one word * 2890 * * 2891 ***************************************************************************************************** 2893 VECTOR 2894 >>>>>>>>>> 070 C2CC17ED30400003C0 2895 >ONEWORD X2 SBST RAM IBFCKPE ONEWORDCKPE BPE*, RTO* but Abnormal Da 071 42CC002DF2C00003C4 2896 > X2 SBHC DPOUT ONEWORD1 BPE*, RTO* and Normal Data 072 42CC006D31507F82F2 2897 > SBST SCR0 MEM2ERR,P BFGODIE BPE*, RTO* but Command Flags 073 42CC006D31507F82F2 2898 > SBST SCR0 MEM2ERR,P BFGODIE BPE*, RTO* but Illegal Flags 074 C2CC006D31507F82F5 2899 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 075 C2CC006D31507F82F5 2900 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 076 C2CC006D31507F82F5 2901 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 077 C2CC006D31507F82F5 2902 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 078 42CC006D31507F82F1 2903 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 079 42CC006D31507F82F1 2904 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 07A 42CC006D31507F82F1 2905 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 07B 42CC006D31507F82F1 2906 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 07C 42CC006D31507F82F1 2907 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 07D 42CC006D31507F82F1 2908 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 07E 42CC006D31507F82F1 2909 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 07F 42CC006D31507F82F1 2910 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 2911 >>>>>>>>>> 2912 ENDVECTOR 2914 STARTSKP 3C0 C0CFD7EB6FC10003C2 2915$ ONEWORDCKPE X2 LIT AND RAM IBFCKPE WORD1DATA SKIP ONEWORDPE abnormal data flags on word 2916 >>>>>>>>>> 3C2 40CCA2EB60401003C3 2917 >ONEWORDPE X2 LIT IOR RAM RAM PRTST MPECODE word 1 is abnormal data,note 3C3 42CC002DF2C00003C4 2918 > X2 SBHC DPOUT word is normal data 2919 >>>>>>>>>> 3C4 42CC002E72C00003C5 2920 ONEWORD1 X2 SBLC DPOUT finish outputting 3C5 42CF045B5240060FF0 2921 I LIT IADR IBFIADR TWOWORDS POP DIDNTPOP reset the vector & exit 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 79 PPU3/REV 25 microcode | FIFO Output processor 2923 2924 2925 ***************************************************************************************************** 2926 * * 2927 * Here if fetching an odd number of bytes * 2928 * * 2929 ***************************************************************************************************** 2931 VECTOR 2932 >>>>>>>>>> 080 70C8606AF14FFFB3C1 2933 >ODDWORD X2 SCRC ADD LIT SCRC -5 OWCKIFONE BPE*, RTO* and Abnormal Data 081 F0CBC06AFFC00043CC 2934 >ODDWORDOK X2 SCRC AND LIT 4 SKIP OWISONE BPE*, RTO* and Normal Data 082 42CC006D31507F82F2 2935 > SBST SCR0 MEM2ERR,P BFGODIE BPE*, RTO* but Command Flags 083 42CC006D31507F82F2 2936 > SBST SCR0 MEM2ERR,P BFGODIE BPE*, RTO* but Illegal Flags 084 C2CC006D31507F82F5 2937 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 085 C2CC006D31507F82F5 2938 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 086 C2CC006D31507F82F5 2939 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 087 C2CC006D31507F82F5 2940 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go DIE! 088 42CC006D31507F82F1 2941 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 089 42CC006D31507F82F1 2942 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 08A 42CC006D31507F82F1 2943 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 08B 42CC006D31507F82F1 2944 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 08C 42CC006D31507F82F1 2945 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 08D 42CC006D31507F82F1 2946 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 08E 42CC006D31507F82F1 2947 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 08F 42CC006D31507F82F1 2948 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go DIE! 2949 >>>>>>>>>> 2950 ENDVECTOR 2952 STARTSKP 3C1 70CBC06AFFC80003C7 2953$ OWCKIFONE X2 SCRC AND LIT #8000 SKIP OWPENOTONE check if 1 or 2 words used? 2954 >>>>>>>>>> 3C6 C2CC17ED30400003C9 2955 > X2 SBST RAM IBFCKPE ODDWORDCKPE 1 word used,get flags 3C7 C0CCA2EB60401003C8 2956 >OWPENOTONE X2 LIT IOR RAM RAM PRTST MPECODE 2 words used,set parity error 2957 >>>>>>>>>> 3C8 F0C8606AF1400053CD 2958 X2 SCRC ADD LIT SCRC 5 OWNOTONE correct SCRC, finish processi 2959 2960 STARTSKP 3C9 40CFD7EB6FC10003CA 2961 ODDWORDCKPE X2 LIT AND RAM IBFCKPE WORD1DATA SKIP ODDWORDPE abnormal data flags on word 2962 >>>>>>>>>> 3CA C0CCA2EB60401003CB 2963 >ODDWORDPE X2 LIT IOR RAM RAM PRTST MPECODE word 1 is abnormal data,note 3CB 70C8606AF140005081 2964 > X2 SCRC ADD LIT SCRC 5 ODDWORDOK no PE on word 1,finish proce 2965 >>>>>>>>>> 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 80 PPU3/REV 25 microcode | FIFO Output processor 2967 2968 SKIPORG 2969 >>>>>>>>>> 3CC F0C8AB6AF1400003D4 2970 >OWISONE X2 SCRC IOR LIT SCRC LAST OW1BCIOR OWISONE1 less than 1 word, process 3CD 42CC002DF2C00003CE 2971 >OWNOTONE X2 SBHC DPOUT more than 1, save the 1st 2972 >>>>>>>>>> 3CE 42CC002E72C00003CF 2973 X2 SBLC DPOUT 3CF F0C8606AF14FFFC3D0 2974 X2 SCRC ADD LIT SCRC -4 reflect it in the count and 3D0 80CC6C6B60400023D1 2975 X2,P LIT ADD RAM RAM LADDR 2 make sure the address is righ 3D1 70C8A06AF14000C3D2 2976 X2 SCRC IOR LIT SCRC OW2BCIOR process the 2nd word 3D2 72CA006ADFC000076C 2977 SCRC DB0 OWIS2BC 2978 BLOCK 4,OW2BCIOR 2979 >>>>>>>>>> 76C CECC006B51400147F1 2980 >OWIS2BC LIT SCR3 #14 NOBRANCH 76D 428C002EF2C00003D7 2981 > X2 SBHD DPOUT,H OWEXIT move 1 byte 76E C2CC002EF2C00003D7 2982 > X2 SBHD DPOUT OWEXIT move 2 bytes 76F 42CC002EF2C00003D3 2983 > X2 SBHD DPOUT OWIS2BC1 move 3 bytes 2984 >>>>>>>>>> 2985 ENDBLOCK 3D3 428C002F72C00003D7 2987 OWIS2BC1 X2 SBLD DPOUT,H OWEXIT 3D4 00CC6C6B60400013D5 2989 OWISONE1 X2,P LIT ADD RAM RAM LADDR 1 make sure the address is righ 3D5 F2CA006ADFC0000740 2990 SCRC DB0 OWIS1BC 2992 BLOCK 4,OW1BCIOR 2993 >>>>>>>>>> 740 4ECC006B51400157F1 2994 >OWIS1BC LIT SCR3 #15 NOBRANCH 741 428C002DF2C00003D7 2995 > X2 SBHC DPOUT,H OWEXIT move 1 byte 742 C2CC002DF2C00003D7 2996 > X2 SBHC DPOUT OWEXIT move 2 bytes 743 42CC002DF2C00003D6 2997 > X2 SBHC DPOUT OWIS1BC1 move 3 bytes 2998 >>>>>>>>>> 2999 ENDBLOCK 3D6 C28C002E72C00003D7 3001 OWIS1BC1 X2 SBLC DPOUT,H OWEXIT 3D7 42CF045B5240060FF0 3003 OWEXIT I LIT IADR IBFIADR TWOWORDS POP DIDNTPOP reset the vector & exit 3004 TITLE.MAC Diagnostic Section 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 81 PPU3/REV 25 microcode | Diagnostic Section 3005 3006 ***************************************************************************************************** 3007 * * 3008 * PPU self-test diagnostics * 3009 * * 3010 ***************************************************************************************************** 3011 3D8 C2CC002B5480000400 3012 SELFTEST LIT DPOE #00 DOTEST turn off the controllers 3013 * and do the self-test 3015 ***************************************************************************************************** 3016 * End of test stuff. * 3017 ***************************************************************************************************** 3018 3D9 C2CC006B31C00003DA 3019 ENDTEST T4 SBRST clear the BUS interface 3DA D8CC006B71400003DB 3020 ZERO SCR6 clear PPU Internal Status 3DB 66CC006B51400F03DC 3021 LIT SCR9 #F0 set up controller enable flag 3DC E6C8002AD4800003DD 3022 SCR9 DPOE issue (again) to hardware 3DD C2CC006B51400033DE 3024 LIT SCR0 3 clear WRU responses, but don' 3DE 42C8002AD4C00003E4 3025 SCR0 INDX1 WRULOOP1 touch the Self-test response 3026 3027 SKIPORG 3028 >>>>>>>>>> 3E0 42CC002B37C000009E 3029 > RESTART SELF-TEST complete, restart 3E1 42C8002AD4C00003E2 3030 >WRULOOP SCR0 INDX1 3031 >>>>>>>>>> 3E2 40CC15EB70600003E3 3032 X1 ZERO RAM WRURES4B 3E3 40CC156B70600003E4 3033 X1 ZERO RAM WRURES4A 3E4 C0CC14EB70600003E5 3034 WRULOOP1 X1 ZERO RAM WRURES3B 3E5 40CC146B70600003E6 3035 X1 ZERO RAM WRURES3A 3E6 C0CC13EB70600003E7 3036 X1 ZERO RAM WRURES2B 3E7 40CC136B70600003E8 3037 X1 ZERO RAM WRURES2A 3E8 C0CC12EB70600003E9 3038 X1 ZERO RAM WRURES1B 3E9 40CC126B70600003EA 3039 X1 ZERO RAM WRURES1A 3EA C0CB606AF94FFFF3E1 3040 SCR0 ADD LIT SCR0 #FFFF SKIP WRULOOP count and test 3EB 42CC002B55CFFFF3EB 3042 LIT IMR -1 * just a useful instruction 03EB 3044 MAXPCLOW EQU *-1 maximum PC in low RAM (0-3FF) 3046 IF MAXPCLOW GE #400, we've run out of code space 3048 TITLE.MAC PPU-3 REV. 3 SELFTEST 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 82 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 3049 0 INCLUDE UCODE.HRDPP4:SELFTEST.REV25 1 ***************************************************************************************************** 2 * * 3 * LOG OF CHANGES * 4 * * 5 * Revision 25 Jul, 1991 ECN 1724 * 6 * -------- -- ---- ---- --- ---- * 7 * * 8 * Log of changes added to file. No code changes. * 9 * Revision levels now in decimal in documentation. * 10 * * 11 ***************************************************************************************************** 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 83 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 13 * SELFTEST INTERRUPT RETURNS 14 0001 15 ORG 1 16 001 62CC006B5940001734 17 LIT SCR8 #0001 INDX PINTRTN 002 62CC006B5940002734 18 LIT SCR8 #0002 INDX PINTRTN 003 E2CC006B5940003734 19 LIT SCR8 #0003 INDX PINTRTN 004 E2CC006B514000468D 20 LIT SCR8 #0004 CBRTN 005 62CC006B514000568D 21 LIT SCR8 #0005 CBRTN 006 62CC006B514000668D 22 LIT SCR8 #0006 CBRTN 007 E2CC006B514000768D 23 LIT SCR8 #0007 CBRTN 008 62CC006B5140008692 24 LIT SCR8 #0008 BSERTN 009 E2CC006B5140009692 25 LIT SCR8 #0009 BSERTN 00A E2CC006B514000A692 26 LIT SCR8 #000A BSERTN 00B 62CC006B514000B692 27 LIT SCR8 #000B BSERTN 00C 62CC006B514000C68D 28 LIT SCR8 #000C CBRTN 00D E2CC006B514000D68D 29 LIT SCR8 #000D CBRTN 00E E2CC006B514000E68D 30 LIT SCR8 #000E CBRTN 00F 62CC006B514000F68D 31 LIT SCR8 #000F CBRTN 32 33 ***************************************************************************************************** 34 * * 35 * The error code that this routine returns in SCR0 or WRU 15 is * 36 * the microcode address of the place where it failed. * 37 * * 38 ***************************************************************************************************** 39 0400 40 ORG #400 41 42 ***************************************************************************************************** 43 * Start by testing SCR0 and RAM location ERRFLAG. * 44 ***************************************************************************************************** 45 400 42CC006B31C0000401 46 DOTEST T4 SBRST 401 C2CC002B54C0003402 47 LIT INDX1 #0003 X1 = 3 402 C0CC000B7540000403 48 ZERO SBCB 403 C2CC002B5340003404 49 LIT INDX2 #0003 X2 = 3 404 40CC006B7140000405 50 ZERO SCR0 SCR0<-0 405 C0CBA06AFFC0000406 51 SCR0 IOR LIT 0 SKIP SCR0=0? 406 42CC002B37C0000406 52 * no, stop can't do ERRTN 407 C2CC002B37C0000408 53 NOP yes 408 C0CCE06B7140000409 54 ONES SCR0 SCR0<-FFFF 409 C0CBC06AFFCFFFF40A 55 SCR0 AND LIT #FFFF SKIP SCR0=FFFF? 40A 42CC002B37C000040A 56 * no, stop can't do ERRTN 40B 42CC002B37C000040C 57 NOP yes, next test 40C C2CC15EB506000040D 58 X1 LIT RAM ERRFLAG #0000 set error location 40D 40CF95EB6CE000040E 59 X1 LIT XOR RAM INDX1 ERRFLAG #0000 SKIP is it 0? (X1 = 0) 40E C2CC006B514040E606 60 LIT SCR0 * ERRTN 40F C2CC15EB504FFFF411 61 X2 LIT RAM ERRFLAG #FFFF SKIPTEST assume error, until cleared 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 84 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 63 64 ***************************************************************************************************** 65 * This test is a test of the basic skip logic. It also * 66 * uses the ONES and ZEROS opcodes of the ALU and checks them. * 67 ***************************************************************************************************** 68 0410 69 ORG *+0 AND #7FE 0411 70 ORG *+1 71 411 C0CFE06B7FCFFFF412 72 SKIPTEST ONES #FFFF SKIP skip (true) test 412 42CC006B5140412606 73 LIT SCR0 * ERRTN bad skip 413 40CF006B7FC0000414 74 ZERO 0000 SKIP skip (true) test 414 42CC006B5140414606 75 LIT SCR0 * ERRTN bad skip 415 40CFE06B7FC0000416 76 ONES 0000 SKIP skip (false) test 416 C0CF006B7FCFFFF419 77 ZERO #FFFF SKIP *+3 skip (false) test 417 42CC006B5140417606 78 LIT SCR0 * ERRTN bad skip 418 42CC006B5140418606 79 LIT SCR0 * ERRTN bad skip 419 40CFE06B7FCFFFF41A 80 ONES #FFFF SKIP skip (true) test 41A C2CC006B514041A606 81 LIT SCR0 * ERRTN bad skip 41B C0CF006B7FC000041C 82 ZERO 0000 SKIP skip (true) test 41C C2CC006B514041C606 83 LIT SCR0 * ERRTN bad skip 41D C0CFE06B7FC000041E 84 ONES 0000 SKIP skip (false) test 41E 40CF006B7FCFFFF421 85 ZERO #FFFF SKIP *+3 skip (false) test 41F C2CC006B514041F606 86 LIT SCR0 * ERRTN bad skip 420 C2CC006B5140420606 87 LIT SCR0 * ERRTN bad skip 421 C2CC002B37C0000423 88 NOP PUSHPOPTEST next test 89 90 ***************************************************************************************************** 91 * This is a simple PUSH and POP test. It simply pushes 4 * 92 * addresses and does 4 pops. * 93 ***************************************************************************************************** 94 0422 95 ORG *+0 AND #7FE 0423 96 ORG *+1 97 423 C0CC006B715042F424 98 PUSHPOPTEST ZERO SCR0 POP4,P 424 42CC000B37D042D425 99 POP3,P 425 42CC000B37D042B426 100 POP2,P 426 42CC000B37D0429427 101 POP1,P 427 C0CB607AF140001428 102 SCR0 ADD LIT SCR0 #0001 POP 428 42CC006B5140428606 103 LIT SCR0 * ERRTN 429 40CB607AF14000142A 104 POP1 SCR0 ADD LIT SCR0 #0001 POP 42A C2CC006B514042A606 105 LIT SCR0 * ERRTN 42B 40CB607AF14000142C 106 POP2 SCR0 ADD LIT SCR0 #0001 POP 42C C2CC006B514042C606 107 LIT SCR0 * ERRTN 42D C0CB607AF14000142E 108 POP3 SCR0 ADD LIT SCR0 #0001 POP 42E 42CC006B514042E606 109 LIT SCR0 * ERRTN 42F C0CBC06AF940004430 110 POP4 SCR0 AND LIT SCR0 #0004 SKIP did we do 4 pops? 430 42CC006B5140430606 111 LIT SCR0 * ERRTN no, error 431 42CC002B37C0000433 112 NOP INDXTEST 113 114 ***************************************************************************************************** 115 * Index register tests. The opposite index register is set to a * 116 * different value to provide a little interaction. * 117 * INDX1 FIRST. * 118 ***************************************************************************************************** 119 0432 120 ORG *+0 AND #7FE 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 85 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 0433 121 ORG *+1 122 433 C0CC006B7140000434 123 INDXTEST ZERO SCR0 assume no error 434 42CC002B54C0000435 124 LIT INDX1 0 X1<-0 435 42CC002B5340003436 125 LIT INDX2 3 X2<-3 436 42CC006B3FF0437744 126 X1 INDXTSTB,P INDX INDXBLK0 do INDX branch 127 0436 128 ORG *+0 AND #7FE 0437 129 ORG *+1 130 437 40CBA06AFFC0000438 131 INDXTSTB SCR0 IOR LIT 0 SKIP error? 438 C2CC006B5140438606 132 LIT SCR0 * ERRTN yes, error 133 439 C2CC002B54C000143A 134 LIT INDX1 1 X1<-1 43A 42CC002B534000243B 135 LIT INDX2 2 X2<-2 43B 42CC006B3FF043D748 136 X1 INDXTSTD,P INDX INDXBLK1 do indx branch 137 043C 138 ORG *+0 AND #7FE 043D 139 ORG *+1 140 43D 40CBA06AFFC000043E 141 INDXTSTD SCR0 IOR LIT 0 SKIP error? 43E C2CC006B514043E606 142 LIT SCR0 * ERRTN yes, error 143 43F 42CC002B54C0002440 144 LIT INDX1 2 X1<-2 440 C2CC002B5340001441 145 LIT INDX2 1 X2<-1 441 C2CC006B3FF044374C 146 X1 INDXTSTF,P INDX INDXBLK2 do INDX branch 147 0442 148 ORG *+0 AND #7FE 0443 149 ORG *+1 150 443 C0CBA06AFFC0000444 151 INDXTSTF SCR0 IOR LIT 0 SKIP error? 444 42CC006B5140444606 152 LIT SCR0 * ERRTN yes, error 153 445 C2CC002B54C0003446 154 LIT INDX1 3 X1<-3 446 42CC002B5340000447 155 LIT INDX2 0 X2<-0 447 42CC006B3FF0449730 156 X1 INDXTSTH,P INDX INDXBLK3 do INDX branch 157 0448 158 ORG *+0 AND #7FE 0449 159 ORG *+1 160 449 40CBA06AFFC000044A 161 INDXTSTH SCR0 IOR LIT 0 SKIP error? 44A C2CC006B514044A606 162 LIT SCR0 * ERRTN yes, error 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 86 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 164 ***************************************************************************************************** 165 * Now do INDX2, enter with X1 = 3 and X2 = 0 * 166 ***************************************************************************************************** 44B 42CC006B3FD044D744 167 X2 INDXTSTJ,P INDX INDXBLK0 do INDX branch 168 044C 169 ORG *+0 AND #7FE 044D 170 ORG *+1 171 44D C0CBA06AFFC000044E 172 INDXTSTJ SCR0 IOR LIT 0 SKIP error? 44E 42CC006B514044E606 173 LIT SCR0 * ERRTN yes, error 174 44F C2CC002B5340001450 175 LIT INDX2 1 X2<-1 450 42CC002B54C0002451 176 LIT INDX1 2 X1<-2 451 42CC006B3FD0453748 177 X2 INDXTSTL,P INDX INDXBLK1 do INDX branch 178 0452 179 ORG *+0 AND #7FE 0453 180 ORG *+1 181 453 40CBA06AFFC0000454 182 INDXTSTL SCR0 IOR LIT 0 SKIP error? 454 C2CC006B5140454606 183 LIT SCR0 * ERRTN yes, error 184 455 C2CC002B5340002456 185 LIT INDX2 2 X2<-2 456 42CC002B54C0001457 186 LIT INDX1 1 X1<-1 457 C2CC006B3FD045974C 187 X2 INDXTSTN,P INDX INDXBLK2 do INDX branch 188 0458 189 ORG *+0 AND #7FE 0459 190 ORG *+1 191 459 C0CBA06AFFC000045A 192 INDXTSTN SCR0 IOR LIT 0 SKIP error? 45A 42CC006B514045A606 193 LIT SCR0 * ERRTN yes, error 194 45B 42CC002B534000345C 195 LIT INDX2 3 X2<-3 45C C2CC002B54C000045D 196 LIT INDX1 0 X1<-0 45D 42CC006B3FD045F730 197 X2 INDXTSTP,P INDX INDXBLK3 do INDX branch 198 045E 199 ORG *+0 AND #7FE 045F 200 ORG *+1 201 45F C0CBA06AFFC0000460 202 INDXTSTP SCR0 IOR LIT 0 SKIP error? 460 42CC006B5140460606 203 LIT SCR0 * ERRTN yes, error 204 205 * LIT INDX1 0 X1<-0 461 42CC002B5340000463 206 LIT INDX2 0 DB0TEST X2<-0 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 87 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 208 BLOCK 4,IBLK0IOR 209 >>>>>>>>>> 744 C2CF001B37C00007FE 210 >INDXBLK0 POP STERR ok 745 42CF007B51407457FE 211 > LIT SCR0 * POP STERR error 746 42CF007B51407467FE 212 > LIT SCR0 * POP STERR error 747 C2CF007B51407477FE 213 > LIT SCR0 * POP STERR error 214 >>>>>>>>>> 215 ENDBLOCK 216 217 BLOCK 4,IBLK1IOR 218 >>>>>>>>>> 748 C2CF007B51407487FE 219 >INDXBLK1 LIT SCR0 * POP STERR error 749 C2CF001B37C00007FE 220 > POP STERR ok 74A 42CF007B514074A7FE 221 > LIT SCR0 * POP STERR error 74B C2CF007B514074B7FE 222 > LIT SCR0 * POP STERR error 223 >>>>>>>>>> 224 ENDBLOCK 225 226 BLOCK 4,IBLK2IOR 227 >>>>>>>>>> 74C 42CF007B514074C7FE 228 >INDXBLK2 LIT SCR0 * POP STERR error 74D C2CF007B514074D7FE 229 > LIT SCR0 * POP STERR error 74E C2CF001B37C00007FE 230 > POP STERR ok 74F 42CF007B514074F7FE 231 > LIT SCR0 * POP STERR error 232 >>>>>>>>>> 233 ENDBLOCK 234 235 BLOCK 4,IBLK3IOR 236 >>>>>>>>>> 730 C2CF007B51407307FE 237 >INDXBLK3 LIT SCR0 * POP STERR error 731 42CF007B51407317FE 238 > LIT SCR0 * POP STERR error 732 42CF007B51407327FE 239 > LIT SCR0 * POP STERR error 733 C2CF001B37C00007FE 240 > POP STERR ok 241 >>>>>>>>>> 242 ENDBLOCK 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 88 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 244 245 ***************************************************************************************************** 246 * Now for the DB0 and DB4 tests. * 247 ***************************************************************************************************** 248 0462 249 ORG *+0 AND #7FE 0463 250 ORG *+1 251 463 46CC006B514000F464 252 DB0TEST LIT SCR1 #000F init. br. addr. = F 464 C6CA006AD870465720 253 DB0LOOP X1 SCR1 RAM #00 *+1,P DB0 DB0BLOCK branch via DEST(3-0) 465 40CB806AEFE0000466 254 X1 SCR0 XOR RAM #00 #0000 SKIP correct branch? 466 42CC006B5140466606 255 LIT SCR0 * ERRTN bad branch addr 256 467 44CB606AF94FFFF468 257 SCR1 ADD LIT SCR1 #FFFF SKIP addr=addr-1, done? 468 C2CC002B37C0000464 258 DB0LOOP no 259 469 C6CC006B514000046A 260 LIT SCR1 #0000 init DB4 br. addr. = 0 46A 46C9006AD87046B710 261 DB4LOOP X1 SCR1 RAM #00 *+1,P DB4 DB4BLOCK branch via DEST(7-4) 46B 40CB806AEFE000046C 262 X1 SCR0 XOR RAM #00 #0000 SKIP correct branch? 46C 42CC006B514046C606 263 LIT SCR0 * ERRTN bad branch addr 264 46D C2CC002B37C000046E 265 NOP 46E C4C8606AF14001046F 266 SCR1 ADD LIT SCR1 #0010 addr=addr+10 46F 44CBC06AFFC0100470 267 SCR1 AND LIT #0100 SKIP done? 470 42CC002B37C000046A 268 DB4LOOP 471 42CC00237340000472 269 LIT INDX2 #0000 XCHG init X2 to 0, next test 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 89 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 271 272 BLOCK 16 273 >>>>>>>>>> 720 C2CF007B5140000721 274 >DB0BLOCK LIT SCR0 #0000 POP 721 42CF007B5140001722 275 > LIT SCR0 #0001 POP 722 C2CF007B5140002723 276 > LIT SCR0 #0002 POP 723 C2CF007B5140003724 277 > LIT SCR0 #0003 POP 724 C2CF007B5140004725 278 > LIT SCR0 #0004 POP 725 42CF007B5140005726 279 > LIT SCR0 #0005 POP 726 C2CF007B5140006727 280 > LIT SCR0 #0006 POP 727 42CF007B5140007728 281 > LIT SCR0 #0007 POP 728 C2CF007B5140008729 282 > LIT SCR0 #0008 POP 729 42CF007B514000972A 283 > LIT SCR0 #0009 POP 72A C2CF007B514000A72B 284 > LIT SCR0 #000A POP 72B C2CF007B514000B72C 285 > LIT SCR0 #000B POP 72C C2CF007B514000C72D 286 > LIT SCR0 #000C POP 72D 42CF007B514000D72E 287 > LIT SCR0 #000D POP 72E C2CF007B514000E72F 288 > LIT SCR0 #000E POP 72F C2CF007B514000F730 289 > LIT SCR0 #000F POP 290 >>>>>>>>>> 291 ENDBLOCK 293 BLOCK 16 294 >>>>>>>>>> 710 C2CF007B5140000711 295 >DB4BLOCK LIT SCR0 #0000 POP 711 42CF007B5140010712 296 > LIT SCR0 #0010 POP 712 C2CF007B5140020713 297 > LIT SCR0 #0020 POP 713 C2CF007B5140030714 298 > LIT SCR0 #0030 POP 714 C2CF007B5140040715 299 > LIT SCR0 #0040 POP 715 42CF007B5140050716 300 > LIT SCR0 #0050 POP 716 C2CF007B5140060717 301 > LIT SCR0 #0060 POP 717 42CF007B5140070718 302 > LIT SCR0 #0070 POP 718 C2CF007B5140080719 303 > LIT SCR0 #0080 POP 719 42CF007B514009071A 304 > LIT SCR0 #0090 POP 71A C2CF007B51400A071B 305 > LIT SCR0 #00A0 POP 71B C2CF007B51400B071C 306 > LIT SCR0 #00B0 POP 71C C2CF007B51400C071D 307 > LIT SCR0 #00C0 POP 71D 42CF007B51400D071E 308 > LIT SCR0 #00D0 POP 71E C2CF007B51400E071F 309 > LIT SCR0 #00E0 POP 71F 42CF007B51400F0720 310 > LIT SCR0 #00F0 POP 311 >>>>>>>>>> 312 ENDBLOCK 314 BLOCK 16 315 >>>>>>>>>> 700 C2CF007B50407017FE 316 >ABLK LIT RAM #00 ABLK+1 POP STERR 701 C2CF007B50407027FE 317 > LIT RAM #00 ABLK+2 POP STERR 702 42CF007B50407037FE 318 > LIT RAM #00 ABLK+3 POP STERR 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 90 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 703 C2CF007B50407047FE 319 > LIT RAM #00 ABLK+4 POP STERR 704 42CF007B50407057FE 320 > LIT RAM #00 ABLK+5 POP STERR 705 42CF007B50407067FE 321 > LIT RAM #00 ABLK+6 POP STERR 706 C2CF007B50407077FE 322 > LIT RAM #00 ABLK+7 POP STERR 707 C2CF007B50407087FE 323 > LIT RAM #00 ABLK+8 POP STERR 708 42CF007B50470907FE 324 > LIT RAM #00 ABLK*#10+#90 POP STERR 709 42CF007B50470A07FE 325 > LIT RAM #00 ABLK*#10+#A0 POP STERR 70A C2CF007B50470B07FE 326 > LIT RAM #00 ABLK*#10+#B0 POP STERR 70B 42CF007B50470C07FE 327 > LIT RAM #00 ABLK*#10+#C0 POP STERR 70C C2CF007B50470D07FE 328 > LIT RAM #00 ABLK*#10+#D0 POP STERR 70D C2CF007B50470E07FE 329 > LIT RAM #00 ABLK*#10+#E0 POP STERR 70E 42CF007B50470F07FE 330 > LIT RAM #00 ABLK*#10+#F0 POP STERR 70F C2CF007B50471007FE 331 > LIT RAM #00 ABLK*#10+#100 POP STERR 332 >>>>>>>>>> 333 ENDBLOCK 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 91 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 335 336 ***************************************************************************************************** 337 * * 338 * The 'EXCHANGE' (, X) option in the ALU field puts * 339 * ALU (15-8) on DEST2 (7-0) and ALU (7-0) on DEST2 (15-8). * 340 * This test will see if the exchange is functional by * 341 * swapping the pattern #ABCD, then checking for #CDAB. Then we * 342 * will check the 'B' inputs to the exchange MUX with an * 343 * incrementing pattern. * 344 * * 345 ***************************************************************************************************** 346 0472 347 ORG *+1 AND #7FE 348 472 C2CC006B514ABCD473 349 XCHG LIT SCR0 #ABCD SCR0 = #ABCD 473 C6CC006B514CDAB474 350 LIT SCR1 #CDAB expected patt in SCR1 474 41C8C06AF04FFFF475 351 X2 SCR0 AND,X LIT RAM #00 #FFFF SCR0=ABCD, RAM=CDAB 475 C4CB806AEFC0000476 352 X2 SCR1 XOR RAM #00 #0000 SKIP ok? 476 C2CC006B5140476606 353 LIT SCR0 * ERRTN no 354 477 C6CC006B51400FF478 355 LIT SCR1 #00FF SCR1=starting pattern 478 4ACC006B514FF0047C 356 LIT SCR2 #FF00 XCHG0 SCR2=known good pattern 357 047A 358 ORG *+1 AND #7FE 359 47A 48C8606AF14FF0047B 360 XCHG0A SCR2 ADD LIT SCR2 #FF00 known good -1 (-100) 47B 44CB606AF94FFFF47C 361 SCR1 ADD LIT SCR1 #FFFF SKIP kick test patt-1 47C 42CC000B37D047A47E 362 XCHG0 XCHG0A,P XCHGTST do the exchange 47D 42CC002B37C0000484 363 HBLB done, next test 364 047E 365 ORG *+1 AND #7FE 366 47E 46C8006AD04000047F 367 XCHGTST X2 SCR1 RAM #00 test pattern 47F C1CCC06B614FFFF480 368 X2 LIT AND,X RAM SCR0 #00 #FFFF switch patt to SCR0 480 CAC8006AD040000481 369 X2 SCR2 RAM #00 expected patt to ram 481 40CB806AEFC0000483 370 X2 SCR0 XOR RAM #00 #0000 SKIP *+2 ok? 482 C2CF001B37C00007FE 371 POP STERR ok 483 C2CC006B5140483606 372 LIT SCR0 * ERRTN no 373 374 ***************************************************************************************************** 375 * * 376 * REGISTER USAGE * 377 * * 378 * SCR0 - bad pattern after exchange * 379 * SCR1 - pattern under test B/4 exchange * 380 * SCR2 - expected pattern after exchange * 381 * * 382 ***************************************************************************************************** 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 92 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 384 385 ***************************************************************************************************** 386 * * 387 * The store high byte (,H) or store low byte (,L) options in the * 388 * destination bus field cause either bits (15-8) or (7-0) respectively * 389 * to be stored in the RAM or scratch pads. The register contents not * 390 * being stored remains unchanged. * 391 * * 392 ***************************************************************************************************** 393 394 0484 395 ORG *+1 AND #7FE 396 484 C2CC006B514FF00485 397 HBLB LIT SCR0 #FF00 init. DATA(7-0) = 00 485 42CC006B504FFFF486 398 HBLB1 X2 LIT RAM #00 #FFFF init. RAM B/4 store 486 C248006AD040000487 399 X2 SCR0 RAM,L #00 store 7-0 only 487 C0CB806AEFC0000488 400 X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = FFXX? 488 42CC006B5140488606 401 LIT SCR0 * ERRTN no 489 40CBC06AFFCFFFF48A 402 SCR0 AND LIT #FFFF SKIP last pattern? 48A C0C8606AF140001485 403 SCR0 ADD LIT SCR0 #0001 HBLB1 loop 404 48B C2CC002B37C000048C 405 NOP 48C 42CC006B51400FF48D 406 LIT SCR0 #00FF init. DATA(15-8) = 00 48D C2CC006B504FFFF48E 407 HBLB2 X2 LIT RAM #00 #FFFF init. RAM B/4 store 48E 4288006AD04000048F 408 X2 SCR0 RAM,H #00 store 15-8 only 48F C0CB806AEFC0000490 409 X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = XXFF? 490 42CC006B5140490606 410 LIT SCR0 * ERRTN no 491 40CBC06AFFCFFFF492 411 SCR0 AND LIT #FFFF SKIP last pattern? 492 40C8606AF14010048D 412 SCR0 ADD LIT SCR0 #0100 HBLB2 loop 413 493 C2CC002B37C0000494 414 NOP 494 C2CC006B504FF00495 415 X2 LIT RAM #00 #FF00 init. DATA(7-0) = 00 495 42CC006B514FFFF496 416 HBLB3 LIT SCR0 #FFFF init. SCR0 B/4 store 496 C24C00636140000497 417 X2 RAM SCR0,L #00 store SCR0(7-0) only 497 40CB806AEFC0000498 418 X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = FFXX? 498 C2CC006B5140498606 419 LIT SCR0 * ERRTN no 499 C0CFC06B6FCFFFF49A 420 X2 LIT AND RAM #00 #FFFF SKIP last pattern? 49A C0CC606B6040001495 421 X2 LIT ADD RAM RAM #00 #0001 HBLB3 loop on inc pattern 422 49B 42CC002B37C000049C 423 NOP 49C 42CC006B50400FF49D 424 X2 LIT RAM #00 #00FF init. DATA(15-8) = 00 49D C2CC006B514FFFF49E 425 HBLB4 LIT SCR0 #FFFF init. SCR0 B/4 store 49E 428C0063614000049F 426 X2 RAM SCR0,H #00 store SCR0(15-8) only 49F C0CB806AEFC00004A0 427 X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = XXFF? 4A0 42CC006B51404A0606 428 LIT SCR0 * ERRTN no 4A1 40CFC06B6FCFFFF4A2 429 X2 LIT AND RAM #00 #FFFF SKIP last pattern? 4A2 40CC606B604010049D 430 X2 LIT ADD RAM RAM #00 #0100 HBLB4 loop on inc pattern 4A3 C2CC002B37C00004A4 431 SCRADDRTST next test 432 433 ***************************************************************************************************** 434 * Store the patterns 0000 - 000F in scratch pads 0 - 0F * 435 * read the scratch pads back and verify that the patterns are unchanged. * 436 ***************************************************************************************************** 437 04A4 438 ORG *+1 AND #7FE 439 4A4 42CC006B51400004A5 440 SCRADDRTST LIT SCR0 #0000 SCR0 = 0000 4A5 46CC006B51400014A6 441 LIT SCR1 #0001 SCR1 = 0001 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 93 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 4A6 CACC006B51400024A7 442 LIT SCR2 #0002 SCR2 = 0002 4A7 CECC006B51400034A8 443 LIT SCR3 #0003 SCR3 = 0003 4A8 52CC006B51400044A9 444 LIT SCR4 #0004 SCR4 = 0004 4A9 56CC006B51400054AA 445 LIT SCR5 #0005 SCR5 = 0005 4AA DACC006B51400064AB 446 LIT SCR6 #0006 SCR6 = 0006 4AB 5ECC006B51400074AC 447 LIT SCR7 #0007 SCR7 = 0007 4AC E2CC006B51400084AD 448 LIT SCR8 #0008 SCR8 = 0008 4AD E6CC006B51400094AE 449 LIT SCR9 #0009 SCR9 = 0009 4AE 6ACC006B514000A4AF 450 LIT SCRA #000A SCRA = 000A 4AF EECC006B514000B4B0 451 LIT SCRB #000B SCRB = 000B 4B0 72CC006B514000C4B1 452 LIT SCRC #000C SCRC = 000C 4B1 76CC006B514000D4B2 453 LIT SCRD #000D SCRD = 000D 4B2 FACC006B514000E4B3 454 LIT SCRE #000E SCRE = 000E 4B3 7ECC006B514000F4B4 455 LIT SCRF #000F SCRF = 000F 456 4B4 42CC006B50400004B5 457 X2 LIT RAM #00 #0000 1st check value = 0 4B5 40CB806AEFC00004B6 458 X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 = 0000? 4B6 C2CC006B51404B6606 459 LIT SCR0 * ERRTN no 4B7 42CC002B37C00004B8 460 NOP 461 4B8 C2CC006B50400014B9 462 X2 LIT RAM #00 #0001 check pattern = #0001 4B9 C4CB806AEFC00004BA 463 X2 SCR1 XOR RAM #00 #0000 SKIP SCR1 = 0001? 4BA C2CC006B51404BA606 464 LIT SCR0 * ERRTN no 4BB C2CC002B37C00004BC 465 NOP 466 4BC 42CC006B50400024BD 467 X2 LIT RAM #00 #0002 check pattern = #0002 4BD 48CB806AEFC00004BE 468 X2 SCR2 XOR RAM #00 #0000 SKIP SCR2 = 0002? 4BE 42CC006B51404BE606 469 LIT SCR0 * ERRTN no 4BF 42CC002B37C00004C0 470 NOP 471 4C0 42CC006B50400034C1 472 X2 LIT RAM #00 #0003 check pattern = #0003 4C1 4CCB806AEFC00004C2 473 X2 SCR3 XOR RAM #00 #0000 SKIP SCR3 = 0003? 4C2 C2CC006B51404C2606 474 LIT SCR0 * ERRTN no 4C3 C2CC002B37C00004C4 475 NOP 476 4C4 42CC006B50400044C5 477 X2 LIT RAM #00 #0004 check pattern = #0004 4C5 50CB806AEFC00004C6 478 X2 SCR4 XOR RAM #00 #0000 SKIP SCR4 = 0004? 4C6 42CC006B51404C6606 479 LIT SCR0 * ERRTN no 4C7 C2CC002B37C00004C8 480 NOP 481 4C8 C2CC006B50400054C9 482 X2 LIT RAM #00 #0005 check pattern = #0005 4C9 D4CB806AEFC00004CA 483 X2 SCR5 XOR RAM #00 #0000 SKIP SCR5 = 0005? 4CA 42CC006B51404CA606 484 LIT SCR0 * ERRTN no 4CB 42CC002B37C00004CC 485 NOP 486 4CC 42CC006B50400064CD 487 X2 LIT RAM #00 #0006 check pattern = #0006 4CD 58CB806AEFC00004CE 488 X2 SCR6 XOR RAM #00 #0000 SKIP SCR6 = 0006? 4CE C2CC006B51404CE606 489 LIT SCR0 * ERRTN no 4CF C2CC002B37C00004D0 490 NOP 491 4D0 42CC006B50400074D1 492 X2 LIT RAM #00 #0007 check pattern = #0007 4D1 5CCB806AEFC00004D2 493 X2 SCR7 XOR RAM #00 #0000 SKIP SCR7 = 0007? 4D2 42CC006B51404D2606 494 LIT SCR0 * ERRTN no 4D3 42CC002B37C00004D4 495 NOP 496 4D4 C2CC006B50400084D5 497 X2 LIT RAM #00 #0008 check pattern = #0008 4D5 E0CB806AEFC00004D6 498 X2 SCR8 XOR RAM #00 #0000 SKIP SCR8 = 0008? 4D6 C2CC006B51404D6606 499 LIT SCR0 * ERRTN no 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 94 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 4D7 42CC002B37C00004D8 500 NOP 501 4D8 42CC006B50400094D9 502 X2 LIT RAM #00 #0009 check pattern = #0009 4D9 64CB806AEFC00004DA 503 X2 SCR9 XOR RAM #00 #0000 SKIP SCR9 = 0009? 4DA C2CC006B51404DA606 504 LIT SCR0 * ERRTN no 4DB C2CC002B37C00004DC 505 NOP 506 4DC C2CC006B504000A4DD 507 X2 LIT RAM #00 #000A check pattern = #000A 4DD E8CB806AEFC00004DE 508 X2 SCRA XOR RAM #00 #0000 SKIP SCRA = 000A? 4DE 42CC006B51404DE606 509 LIT SCR0 * ERRTN no 4DF C2CC002B37C00004E0 510 NOP 511 4E0 42CC006B504000B4E1 512 X2 LIT RAM #00 #000B check pattern = #000B 4E1 6CCB806AEFC00004E2 513 X2 SCRB XOR RAM #00 #0000 SKIP SCRB = 000B? 4E2 42CC006B51404E2606 514 LIT SCR0 * ERRTN no 4E3 42CC002B37C00004E4 515 NOP 516 4E4 42CC006B504000C4E5 517 X2 LIT RAM #00 #000C check pattern = #000C 4E5 70CB806AEFC00004E6 518 X2 SCRC XOR RAM #00 #0000 SKIP SCRC = 000C? 4E6 C2CC006B51404E6606 519 LIT SCR0 * ERRTN no 4E7 42CC002B37C00004E8 520 NOP 521 4E8 C2CC006B504000D4E9 522 X2 LIT RAM #00 #000D check pattern = #000D 4E9 F4CB806AEFC00004EA 523 X2 SCRD XOR RAM #00 #0000 SKIP SCRD = 000D? 4EA C2CC006B51404EA606 524 LIT SCR0 * ERRTN no 4EB C2CC002B37C00004EC 525 NOP 526 4EC 42CC006B504000E4ED 527 X2 LIT RAM #00 #000E check pattern = #000E 4ED 78CB806AEFC00004EE 528 X2 SCRE XOR RAM #00 #0000 SKIP SCRE = 000E? 4EE 42CC006B51404EE606 529 LIT SCR0 * ERRTN no 4EF 42CC002B37C00004F0 530 NOP 531 4F0 42CC006B504000F4F1 532 X2 LIT RAM #00 #000F check pattern = #000F 4F1 7CCB806AEFC00004F2 533 X2 SCRF XOR RAM #00 #0000 SKIP SCRF = 000F? 4F2 C2CC006B51404F2606 534 LIT SCR0 * ERRTN no 4F3 C2CC002B53400004F4 535 LIT INDX2 #0000 SCRTST next test, set index 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 95 PPU3/REV 25 microcode | PPU-3 REV. 3 SELFTEST 537 538 ***************************************************************************************************** 539 * * 540 * This exerciser will test the 16 scratch pads with floating 1, * 541 * floating 0, and incrementing patterns. * 542 * * 543 ***************************************************************************************************** 544 545 ***************************************************************************************************** 546 * FLOATING ONES * 547 ***************************************************************************************************** 548 4F4 42CC006B50400014F6 549 SCRTST X2 LIT RAM #00 #0001 SCRTST1 RAM 0 = 1st flt 1 patt 550 04F4 551 ORG *+0 AND #7FE 04F5 552 ORG *+1 553 4F5 40CB606AE8400004F6 554 SCRTST1A X2 SCR0 ADD RAM RAM #00 #0000 SKIP shift left 1, done? 4F6 42CC000B37D04F54FE 555 SCRTST1 SCRTST1A,P WSCR no, hit it 556 557 ***************************************************************************************************** 558 * FLOATING ZEROES * 559 ***************************************************************************************************** 560 4F7 42CC006B504FFFE4FC 561 X2 LIT RAM #00 #FFFE SCRTST2 RAM 0=1st flt. 0 patt 4F8 40CC806B614FFFF4F9 562 SCRTST2A X2 LIT XOR RAM SCR0 #00 #FFFF invert pattern 4F9 42C8006AD0400004FA 563 X2 SCR0 RAM #00 RAM 0=SCR0 for add 4FA C0C8606AE1400004FB 564 X2 SCR0 ADD RAM SCR0 #00 shift pattern left 1 4FB 40CB806AF84FFFF4FC 565 X2 SCR0 XOR LIT RAM #00 #FFFF SKIP invert for FLT0, done? 4FC C2CC000B37D04F84FE 566 SCRTST2 SCRTST2A,P WSCR write the scratch pads 4FD 42CC002B37C0000531 567 TESTCARY next test 568 TITLE.MAC WRITE, READ, AND TEST SCRATCH PADS 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 96 PPU3/REV 25 microcode | WRITE, READ, AND TEST SCRATCH PADS 569 ***************************************************************************************************** 570 * SUBROUTINE TO WRITE, READ, AND TEST SCRATCH PADS * 571 ***************************************************************************************************** 572 4FE C2CC006361400004FF 573 WSCR X2 RAM SCR0 #00 4FF C6CC00636140000500 574 X2 RAM SCR1 #00 500 4ACC00636140000501 575 X2 RAM SCR2 #00 501 CECC00636140000502 576 X2 RAM SCR3 #00 502 D2CC00636140000503 577 X2 RAM SCR4 #00 503 D6CC00636140000504 578 X2 RAM SCR5 #00 504 5ACC00636140000505 579 X2 RAM SCR6 #00 505 DECC00636140000506 580 X2 RAM SCR7 #00 506 62CC00636140000507 581 X2 RAM SCR8 #00 507 E6CC00636140000508 582 X2 RAM SCR9 #00 508 6ACC00636140000509 583 X2 RAM SCRA #00 509 EECC0063614000050A 584 X2 RAM SCRB #00 50A F2CC0063614000050B 585 X2 RAM SCRC #00 50B F6CC0063614000050C 586 X2 RAM SCRD #00 50C 7ACC0063614000050D 587 X2 RAM SCRE #00 50D 7ECC0063614000050F 588 X2 RAM SCRF #00 RSCR 589 050E 590 ORG *+0 AND #7FE 050F 591 ORG *+1 592 50F C0CB806AEFC0000510 593 RSCR X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 ok? 510 42CC006B5140510606 594 LIT SCR0 * ERRTN SCR0 bad 511 C4CB806AEFC0000512 595 X2 SCR1 XOR RAM #00 #0000 SKIP SCR1 ok? 512 C2CC006B5140512606 596 LIT SCR0 * ERRTN SCR1 bad 513 C8CB806AEFC0000514 597 X2 SCR2 XOR RAM #00 #0000 SKIP SCR2 ok? 514 C2CC006B5140514606 598 LIT SCR0 * ERRTN SCR2 bad 515 CCCB806AEFC0000516 599 X2 SCR3 XOR RAM #00 #0000 SKIP SCR3 ok? 516 42CC006B5140516606 600 LIT SCR0 * ERRTN SCR3 bad 517 D0CB806AEFC0000518 601 X2 SCR4 XOR RAM #00 #0000 SKIP SCR4 ok? 518 C2CC006B5140518606 602 LIT SCR0 * ERRTN SCR4 bad 519 D4CB806AEFC000051A 603 X2 SCR5 XOR RAM #00 #0000 SKIP SCR5 ok? 51A 42CC006B514051A606 604 LIT SCR0 * ERRTN SCR5 bad 51B D8CB806AEFC000051C 605 X2 SCR6 XOR RAM #00 #0000 SKIP SCR6 ok? 51C 42CC006B514051C606 606 LIT SCR0 * ERRTN SCR6 bad 51D DCCB806AEFC000051E 607 X2 SCR7 XOR RAM #00 #0000 SKIP SCR7 ok? 51E C2CC006B514051E606 608 LIT SCR0 * ERRTN SCR7 bad 51F 60CB806AEFC0000520 609 X2 SCR8 XOR RAM #00 #0000 SKIP SCR8 ok? 520 42CC006B5140520606 610 LIT SCR0 * ERRTN SCR8 bad 521 64CB806AEFC0000522 611 X2 SCR9 XOR RAM #00 #0000 SKIP SCR9 ok? 522 C2CC006B5140522606 612 LIT SCR0 * ERRTN SCR9 bad 523 68CB806AEFC0000524 613 X2 SCRA XOR RAM #00 #0000 SKIP SCRA ok? 524 C2CC006B5140524606 614 LIT SCR0 * ERRTN SCRA bad 525 6CCB806AEFC0000526 615 X2 SCRB XOR RAM #00 #0000 SKIP SCRB ok? 526 42CC006B5140526606 616 LIT SCR0 * ERRTN SCRB bad 527 70CB806AEFC0000528 617 X2 SCRC XOR RAM #00 #0000 SKIP SCRC ok? 528 C2CC006B5140528606 618 LIT SCR0 * ERRTN SCRC bad 529 74CB806AEFC000052A 619 X2 SCRD XOR RAM #00 #0000 SKIP SCRD ok? 52A 42CC006B514052A606 620 LIT SCR0 * ERRTN SCRD bad 52B 78CB806AEFC000052C 621 X2 SCRE XOR RAM #00 #0000 SKIP SCRE ok? 52C 42CC006B514052C606 622 LIT SCR0 * ERRTN SCRE bad 52D 7CCB806AEFC000052E 623 X2 SCRF XOR RAM #00 #0000 SKIP SCRF ok? 52E C2CC006B514052E606 624 LIT SCR0 * ERRTN SCRF bad 52F C2CF001B37C00007FE 625 POP STERR return 626 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 97 PPU3/REV 25 microcode | WRITE, READ, AND TEST SCRATCH PADS 627 ***************************************************************************************************** 628 * * 629 * The next test does 2 consecutive adds W/O carry to see if carry * 630 * in got set, then sets carry to see if carry in is functional. * 631 * * 632 * S1 ALU S2 DEST.(RESULT) * 633 * CARRY OUT CARRY IN SCR4 ADD RAM RAM * 634 * 1 0 + FFFF + 0001 = 0000 * 635 * 0 0 + FFFF + 0000 = FFFF * 636 * * 637 ***************************************************************************************************** 638 0530 639 ORG *+0 AND #7FE 0531 640 ORG *+1 641 531 D2CC006B514FFFF532 642 TESTCARY LIT SCR4 #FFFF SCR4 = #FFFF 532 C2CC006B5040001533 643 X2 LIT RAM #00 #0001 (RAM #00) = #0001 533 50CB606AE840000535 644 X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 add w/o carry = 0? 534 50CB606AE84FFFF536 645 X2 SCR4 ADD RAM RAM #00 #FFFF SKIP *+2 did carry get set? 535 C2CC006B5140535606 646 LIT SCR0 * ERRTN #FFFF+1+0 <> 0 536 C2CC006B5140536606 647 LIT SCR0 * ERRTN #FFFF+0+0 <> #FFFF 537 42CC002B37C0000538 648 NOP 538 D2DC006B514FFFF539 649 STC LIT SCR4 #FFFF SCR4 = ONES, carry = 1 539 D0EB606AF94000053A 650 TWC SCR4 ADD LIT SCR4 #0000 SKIP does FFFF + 0 + 1 = 0? 53A C2CC006B514053A606 651 LIT SCR0 * ERRTN carry in logic failed 652 653 ***************************************************************************************************** 654 * * 655 * This sequence initializes carry in to a 0, generates a carry * 656 * out with carry logic enabled, checking for no carry in, does another * 657 * add, checking for carry in, and does one more add making sure carry * 658 * got flushed out. * 659 * * 660 * S1 ALU S2 DEST.(RESULT) * 661 * CARRY OUT CARRY IN SCR4 ADD RAM RAM * 662 * 1 0 + FFFF + 0001 = 0000 * 663 * 0 1 + FFFF + 0000 = 0000 * 664 * 0 0 + FFFF + 0000 = FFFF * 665 * * 666 ***************************************************************************************************** 667 53B C2CC002B37C000053C 668 NOP 53C D2CC006B514FFFF53D 669 LIT SCR4 #FFFF set SCR4 to ones 53D 46CC006B514FFFE53E 670 LIT SCR1 #FFFE *+1 use SCR1 for counter 53E C2FC006B504000153F 671 CLC,X2 LIT RAM #00 #0001 (RAM #00) = #0001 53F D0EB606AE840000541 672 TWC,X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 dest SB 0,CRY=1 @ RDTS 540 D0EB606AE840000542 673 TWC,X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 dest SB 0,CRY=0 @ RDTS 541 C2CC006B5140541606 674 LIT SCR0 * ERRTN #FFFF+#0001+0 <> #0000 542 C2CC006B5140542606 675 LIT SCR0 * ERRTN #FFFF+#0000+1 <> #0000 543 C4EB606AE84FFFF544 676 TWC,X2 SCR1 ADD RAM RAM #00 #FFFF SKIP did carry clear? 544 C2CC006B5140544606 677 LIT SCR0 * ERRTN #FFFF+#0000+0 <> #0000 545 42CC002B37C0000546 678 TESTCARY0 okay 679 TITLE.MAC Test Carry Logic 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 98 PPU3/REV 25 microcode | Test Carry Logic 680 681 ***************************************************************************************************** 682 * This test part will test the external carry logic connected to * 683 * the 74S381's by doing the following add sequence: * 684 * * 685 * S1 ALU S2 DEST.(RESULT) * 686 * CARRY IN SCR4 ADD RAM RAM * 687 * 1 + 0 + 1 = 2 * 688 * 1 + 0 + 3 = 4 * 689 * 1 + 0 + 7 = 8 * 690 * * 691 * 1 + 0 + ETC = ETC * 692 * * 693 * 1 + 0 + 1FFF = 2000 * 694 * 1 + 0 + 3FFF = 4000 * 695 * 1 + 0 + 7FFF = 8000 * 696 * * 697 * The test repeats the same sequence with source 2 = 0. * 698 ***************************************************************************************************** 699 0546 700 ORG *+1 AND #7FE 701 546 D2CC006B5140001547 702 TESTCARY0 LIT SCR4 #0001 starting S1 pattern 547 4ECC006B5140002548 703 LIT SCR3 #0002 starting known good 548 C2FC006B5040000549 704 TESTCARY1 CLC,X2 LIT RAM #00 #0000 S2 will be 0 this time 549 C2DC002B37C000054A 705 STC generate a carry 54A 50E8606AE04000054B 706 TWC,X2 SCR4 ADD RAM RAM #00 S1 + 0 + 1 = S1 +1 54B 4CCB806AEFC000054D 707 X2 SCR3 XOR RAM #00 #0000 SKIP *+2 ok? 54C C2CC002B37C000054E 708 *+2 yes 54D C2CC006B514054D606 709 LIT SCR0 * ERRTN add with carry failed 710 54E 52CC0063614000054F 711 X2 RAM SCR4 #00 get old result in SCR4 54F D0CB606AE840000551 712 X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 new known good, done? 550 C2CC002B37C0000553 713 TESTCARY2 next test 551 CECC00636140000552 714 X2 RAM SCR3 #00 save new known good 715 * if not done 552 D0CC606B614FFFF548 716 X2 LIT ADD RAM SCR4 #00 #FFFF TESTCARY1 subtract 1 for new 717 * pattern & loop 718 0552 719 ORG *+0 AND #7FE 0553 720 ORG *+1 721 553 4ACC006B5140001554 722 TESTCARY2 LIT SCR2 #0001 starting S2 pattern 554 4ECC006B5140002555 723 LIT SCR3 #0002 starting known good 555 52CC006B5140000556 724 TESTCARY3 LIT SCR4 #0000 S1 stayed 0 this time 556 CAF8006AD040000557 725 CLC,X2 SCR2 RAM #00 S2 pattern to RAM 557 40EC600B77CFFFF558 726 TWC LIT ADD LIT #FFFF generate a carry 558 50E8606AE040000559 727 TWC,X2 SCR4 ADD RAM RAM #00 0 + S2 + 1 = S2 + 1 559 CCCB806AEFC000055B 728 X2 SCR3 XOR RAM #00 #0000 SKIP *+2 ok? 55A C2CC002B37C000055C 729 *+2 OK 55B 42CC006B514055B606 730 LIT SCR0 * ERRTN add with carry failed 731 55C 52CC0063614000055D 732 X2 RAM SCR4 #00 old result to SCR4 55D 50CB606AE84000055F 733 X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 double it, done? 55E 42CC002B37C0000561 734 TESTCARY5 next test 55F 4ECC00636140000560 735 X2 RAM SCR3 #00 save in SCR3 560 C8CC606B614FFFF555 736 X2 LIT ADD RAM SCR2 #00 #FFFF TESTCARY3 new S2 patt & loop 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 99 PPU3/REV 25 microcode | Test Carry Logic 738 739 ***************************************************************************************************** 740 * * 741 * SUBTRACT source 1 from source 2 * 742 * * 743 ***************************************************************************************************** 744 561 D2CC006B514FFFF562 745 TESTCARY5 LIT SCR4 #FFFF set SCR4 = #FFFF 562 C2DC006B5040000563 746 STC,X2 LIT RAM #00 RAM 0=0,CIN=0 for sub 563 D0EB206AE940001564 747 TWC,X2 SCR4 RSUB RAM SCR4 #00 1 SKIP 1 0000 (-) FFFF=0001? 564 42CC006B5140564606 748 LIT SCR0 * ERRTN sub S1 from S2 bad 749 750 ***************************************************************************************************** 751 * * 752 * SUBTRACT source 2 from source 1 * 753 * * 754 ***************************************************************************************************** 755 565 52CC006B5140000566 756 LIT SCR4 SCR4 = 0000 566 42DC006B504FFFF567 757 STC,X2 LIT RAM #00 #FFFF RAM 00 = FFFF 567 D0EB406AE940001568 758 TWC,X2 SCR4 SUB RAM SCR4 #00 1 SKIP 1 0000 (-) FFFF=0001? 568 42CC006B5140568606 759 LIT SCR0 * ERRTN SUB S2 from S1 bad 569 C2CC002B37C000056A 760 ALUTEST next test 761 762 ** above copied from ppu5 763 764 TITLE.MAC ALU Test 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 100 PPU3/REV 25 microcode | ALU Test 56A C2CC006B514070056B 765 ALUTEST LIT SCR0 ABLK DB0 branch addr SCR0 56B 46CC006B514000056C 766 LIT SCR1 #0000 0 = DB0 56C C088A06AF04000056D 767 ALUTEST1 X2 SCR0 IOR LIT RAM,H #00 #0000 RAM = NNXX 56D C248006AD05057556E 768 X2 SCR0 RAM,L #00 ALUCHECK,P RAM = XXNN 56E CD8C806B614FFFF56F 769 X2 LIT XOR,X RAM SCR3,H #00 #FFFF swapped patt to SCR3 upper 56F 4D4C806B614FFFF570 770 X2 LIT XOR,X RAM SCR3,L #00 #FFFF swapped patt to SCR3 lower 570 41C8826AF04FFFF571 771 X2 SCR0 XOR,X LIT RAM #10 #FFFF swap a ck patt to RAM 571 C4CBA06AFFC0000572 772 SCR1 IOR LIT #0000 SKIP skip true = DB0 572 40C9606AF940010700 773 SCR0 ADD LIT SCR0 #0010 DB4 ABLK DB4 BR., addr+1 573 40CA606AF940001700 774 SCR0 ADD LIT SCR0 #0001 DB0 ABLK DB0 BR., addr+1 775 0574 776 ORG *+0 AND #7FE 0575 777 ORG *+1 778 575 40CB806AEFC0000577 779 ALUCHECK X2 SCR0 XOR RAM #00 #0000 SKIP *+2 addressing good? 576 CCCB826AEFC0000578 780 X2 SCR3 XOR RAM #10 #0000 SKIP *+2 data good? 577 C2CC006B5140577606 781 LIT SCR0 * ERRTN bad DB address 578 C2CC006B5140578606 782 LIT SCR0 * ERRTN bad HI - LO - XCHG 579 44CBA06AFFC000057A 783 SCR1 IOR LIT #0000 SKIP DB0 in progress? 57A C0CBA06AFFCFF0057C 784 SCR0 IOR LIT #FF00 SKIP *+2 done DB4? 57B C0CBC06AFFC000857E 785 SCR0 AND LIT #0008 SKIP *+3 done DB0? 57C C2CC002B37C000056C 786 ALUTEST1 doing DB4 57D C2CC002B54C0000588 787 LIT INDX1 #0000 CONFIG 57E C2CC002B37C000056C 788 ALUTEST1 doing DB0 57F C4C8806AF14FFFF580 789 SCR1 XOR LIT SCR1 #FFFF set DB4 flag 580 4ACC006B5140003581 790 LIT SCR2 #0003 -4 counter 581 C0C8C06AF04FFF0582 791 X2 SCR0 AND LIT RAM #00 #FFF0 orig addr to RAM 582 C2CC00636140000583 792 X2 RAM SCR0 #00 and SCR0 583 C0C8606AE140000584 793 X2 SCR0 ADD RAM SCR0 #00 left 1 four times 584 C8CB606AF94FFFF586 794 SCR2 ADD LIT SCR2 #FFFF SKIP *+2 DB4 set up yet? 585 42CC006B5140585606 795 LIT SCR0 * ERRTN should never get here 586 42C8006AD040000583 796 X2 SCR0 RAM #00 *-3 pussy tight loop 587 C0C8A06AF14008056C 797 SCR0 IOR LIT SCR0 #0080 ALUTEST1 start DB4 test 798 TITLE.MAC Bus Tests 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 101 PPU3/REV 25 microcode | Bus Tests 799 800 *SLOT CONFIGURATION AND 64 BIT FLOATING 1-RFI/FLOATNG ZERO-RFR 801 0010 802 PINTCK EQU #10 RAM 10 = expected port interrupt # 0014 803 VECTCK EQU #14 RAM 14 = vector interrupt address check 0018 804 WDCNT EQU #18 RAM 18,19,1A,1B=P0,P1,P2,P3 # words written 001C 805 PTFULL EQU #1C RAM 1C = 33 = all 4 output FIFOs should be full 0020 806 ID EQU #20 RAM 20 = expected N, PB, TO, and FROM IN 0040 807 HW1 EQU #40 RAM 40 = high word 1 (out) 0044 808 LW1 EQU #44 RAM 44 = low word 1 (out) 0060 809 HW2 EQU #60 RAM 60 = high word 2 (out) 0070 810 LW2 EQU #70 RAM 70 = low word 2 (out) 0050 811 TCON EQU #50 RAM 50 = test control counter 0080 812 EXSTAT EQU #80 RAM 80 = expected completion superbus status 00A0 813 BUSBITS EQU #A0 RAM A0 = superbus control bits 00AC 814 ERRFLAG EQU WRURES4B RAM WRURES4B+3 = selftest flag = 0 = no errors, + = error code 815 588 42CC006FB140000589 816 CONFIG SBFT SCR0 get N/T/F to SCR0 (want N) 589 C0C8C06AF14F00058A 817 SCR0 AND LIT SCR0 #F000 there's garbage there from BS 58A C1C8D46AF06F00058B 818 X1 SCR0 AND,X LIT RAM BUSBITS #F000 RAM #10=TO=#00T0 58B C0C8B46AE16000058C 819 X1 SCR0 IOR RAM SCR0 BUSBITS SCR0 = #N0T0 58C C2C8046AD06000058D 820 X1 SCR0 RAM ID part of ID = N0T0 (save it) 58D 46CC006B5140003590 821 LIT SCR1 #0003 CFSLOOP -4 counter for shift 822 058E 823 ORG *+1 AND #7FE 824 58E 40C8746AE06000058F 825 X1 SCR0 ADD RAM RAM BUSBITS left one 4 times 58F 44CB606AF94FFFF590 826 SCR1 ADD LIT SCR1 #FFFF SKIP 7-4 in 11-8? 590 C2CC1463616000058E 827 CFSLOOP X1 RAM SCR0 BUSBITS *-2 not in SBCB format yet 591 C1CCD46B6160F00592 828 X1 LIT AND,X RAM SCR0 BUSBITS #0F00 slot = 0T00, SCR0 = 000F 592 40C8A46AE060000593 829 X1 SCR0 IOR RAM RAM ID ID = N0TF = SBFT check 830 593 C0CCB46B6060053594 831 X1 LIT IOR RAM RAM BUSBITS #0053 SLOT+F0W1+F0W2+DW+RTO to RAM 832 833 ***************************************************************************************************** 834 * Sliding 1s test, RFI, each pattern once * 835 ***************************************************************************************************** 836 594 C2CC106B50690D0595 837 X1 LIT RAM EXSTAT #90D0 PFW-,F0W1,DW,IBF,F0W2 595 40CCE00B729059B596 838 ONES SBRFI DWRFI2,P set RFI 596 02CC086B5060000597 839 X1,P LIT RAM HW1 #0000 initial pattern = #0000- 597 82CC08EB5060000598 840 X1,P LIT RAM LW1 #0000 -#0000- 598 C2CC0C6B5060000599 841 X1 LIT RAM HW2 #0000 -#0000- 599 42CC0E6B50600025B3 842 X1 LIT RAM LW2 #0002 DWXFER -#0002 843 059A 844 ORG *+0 AND #7FE 059B 845 ORG *+1 846 59B C0FB806AFFC000059C 847 DWRFI2 CLC SCR0 XOR LIT #0000 SKIP any errors? 59C C2CC002B37C0000606 848 ERRTN error, code in SCR0 59D 5CEB6E6AE86000259F 849 X1,TWC SCR7 ADD RAM RAM LW2 #0002 SKIP *+2 low 2 left 1, last patt? 59E C2CC002B52800005A4 850 LIT SBRFI #0000 DWRFR done, clear RFI 59F 58E86C6AE0600005A0 851 X1,TWC SCR6 ADD RAM RAM HW2 hi 2 left 1 w/carry 5A0 14E868EAE0600005A1 852 X1,TWC,P SCR5 ADD RAM RAM LW1 LO 1 left 1 w/carry 5A1 10E8686AE0600005A2 853 X1,TWC,P SCR4 ADD RAM RAM HW1 hi 1 left 1 w/carry 5A2 40EC6E6B60600005A3 854 X1,TWC LIT ADD RAM RAM LW2 #0000 and around to low 5A3 C0CCE00B729059B5B3 855 ONES SBRFI DWRFI2,P DWXFER 856 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 102 PPU3/REV 25 microcode | Bus Tests 857 ***************************************************************************************************** 858 * Sliding 0s test, RFR, each pattern once * 859 ***************************************************************************************************** 860 5A4 C0CCB46B60600085A5 861 DWRFR X1 LIT IOR RAM RAM BUSBITS #0008 set the RFR bit 5A5 10C8886AF06FFFF5A6 862 X1,P SCR4 XOR LIT RAM HW1 #FFFF initial pattern = #FFFF- 5A6 94C888EAF06FFFF5A7 863 X1,P SCR5 XOR LIT RAM LW1 #FFFF -#FFFF- 5A7 58C88C6AF06FFFF5A8 864 X1 SCR6 XOR LIT RAM HW2 #FFFF -#FFFF- 5A8 DCC88E6AF06FFFC5A9 865 X1 SCR7 XOR LIT RAM LW2 #FFFC -#FFFD 5A9 C2CC000B37D05AB5B3 866 DWRFR2,P DWXFER hit it 867 05AA 868 ORG *+0 AND #7FE 05AB 869 ORG *+1 870 5AB C0FB806AFFC00005AC 871 DWRFR2 CLC SCR0 XOR LIT #0000 SKIP errors? 5AC C2CC002B37C0000606 872 ERRTN yes, error code in SCR0 5AD DCEB6E6AE86FFFC5AF 873 X1,TWC SCR7 ADD RAM RAM LW2 #FFFC SKIP *+2 LO word 2 left 1, done? 5AE C2CC002B37C00005D2 874 INTEST done, next test 5AF D8E86C6AE0600005B0 875 X1,TWC SCR6 ADD RAM RAM HW2 hi word 2 left 1 5B0 94E868EAE0600005B1 876 X1,TWC,P SCR5 ADD RAM RAM LW1 LO word 1 left 1 5B1 90E8686AE0705AB5B2 877 X1,TWC,P SCR4 ADD RAM RAM HW1 DWRFR2,P hi word 1 left 1 5B2 C0EC6E6B60600005B3 878 X1,TWC LIT ADD RAM RAM LW2 #0000 DWXFER carry back into lo word 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 103 PPU3/REV 25 microcode | Bus Tests 880 881 ***************************************************************************************************** 882 * Bus XFER subroutine * 883 * Needs 1 stack location. * 884 ***************************************************************************************************** 885 5B3 82CC082364200005B4 886 DWXFER X1,P RAM SBHC HW1 output hi word 1 5B4 02CC08A364600005B5 887 X1,P RAM SBLC LW1 output lo word 1 5B5 C2CC0C0363A00005B6 888 X1 RAM SBHD HW2 output hi word 2 5B6 42CC0E0363E00005B7 889 X1 RAM SBLD LW2 output lo word 2 5B7 C2CC142365600005B8 890 X1 RAM SBCB BUSBITS start the transfer 5B8 42CC006D31400005B9 891 SBST SCR0 and wait for IBF 5B9 C0CBA06AFFCFFBF5BB 892 SCR0 IOR LIT #FFBF SKIP *+2 5BA 42CC006D31400005B9 893 SBST SCR0 *-1 keep trying 5BB 42CC006D31400005BC 894 SBST SCR0 get the status again 5BC C2CC002B37C00005BD 895 NOP 5BD 52CC006DF1400005BE 896 SBHC SCR4 hi word 1 5BE D6CC006E71400005BF 897 SBLC SCR5 lo word 1 5BF 46CC006D31400005C0 898 SBST SCR1 IBF clear status pull 5C0 5ACC006EF1400005C1 899 SBHD SCR6 hi word 2 5C1 DECC006F71400005C2 900 SBLD SCR7 lo word 2 5C2 4ACC006FB1400005C3 901 SBFT SCR2 N - T - F 902 5C3 C0CB906AEFE00005C4 903 X1 SCR0 XOR RAM EXSTAT #0000 SKIP IBF+? (STAT=EXSTAT?) 5C4 C2CF007B51405C47FE 904 LIT SCR0 * POP STERR bum status 5C5 D0CB886AEFE00005C6 905 X1 SCR4 XOR RAM HW1 #0000 SKIP hi word 1 ok? 5C6 42CF007B51405C67FE 906 LIT SCR0 * POP STERR data error hi word 1 5C7 54CB88EAEFE00005C8 907 X1 SCR5 XOR RAM LW1 #0000 SKIP lo word 1 ok? 5C8 C2CF007B51405C87FE 908 LIT SCR0 * POP STERR data error lo word 1 5C9 44CBA06AFFCFFBF5CA 909 SCR1 IOR LIT #FFBF SKIP IBF clear? 5CA 42CF007B51405CA7FE 910 LIT SCR0 * POP STERR no, SBHC should've cleared it 5CB D8CB8C6AEFE00005CC 911 X1 SCR6 XOR RAM HW2 #0000 SKIP hi word 2 ok? 5CC 42CF007B51405CC7FE 912 LIT SCR0 * POP STERR data error hi word 2 5CD 5CCB8E6AEFE00005CE 913 X1 SCR7 XOR RAM LW2 #0000 SKIP lo word 2 ok? 5CE C2CF007B51405CE7FE 914 LIT SCR0 * POP STERR data error lo word 2 5CF 48CB846AEFE00005D0 915 X1 SCR2 XOR RAM ID #0000 SKIP N T F ok? 5D0 C2CF007B51405D07FE 916 LIT SCR0 * POP STERR NOPE 5D1 42FF007B51400007FE 917 CLC LIT SCR0 #0000 POP STERR return, no errors 918 TITLE.MAC Bus Interrupt Test 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 104 PPU3/REV 25 microcode | Bus Interrupt Test 919 ***************************************************************************************************** 920 * * 921 ** INTERRUPT TEST * 922 * * 923 * This part of the test tests the interrupt mechanism. * 924 * * 925 * This test should run after the config section which should set * 926 * up the TO and FROM slot # in ram BUSBITS and ram ID for use in * 927 * starting transfer and checking afterward. * 928 * * 929 * The test starts out by resetting all the ports to direction out * 930 * which should cause all the ports to be requesting an interrupt. The * 931 * reset subroutine checks to make sure the interrupt bit and PON bit * 932 * in PTST are correct after resetting the ports. * 933 * * 934 * The initialization includes putting the right thing into * 935 * ram PTFULL and setting ram WDCNT through WDCNT+3 to indicate * 936 * 10 (hex) 16 bit words left to put into each FIFO. The location * 937 * PTFULL is counted to decide when the ports are 4 (16 bit) * 938 * words from being full and all the way full. * 939 * * 940 * This routine sets all of the interrupt addresses to * 941 * #0000. This routine does double word transfers to * 942 * itself to get the exact interrupt address that it wants. This * 943 * routine decides exactly how it will set the bus logic (and the * 944 * 4 LSB's of the interrupt address) by doing a 16 way branch on * 945 * the 4 MSB's of the counter it is using. The 16 way branch is * 946 * to the BUSBLOCK. From there, control goes to a part that * 947 * decides how to set BUSBITS (SBCB) to get the bus logic set to * 948 * the desired state. * 949 * * 950 * The BUSBLOCK stuff is divided up into 3 basic types of routines * 951 * based on the branch address taken. The least significant nibble of * 952 * the BUSBLOCK branch address should be the same as the least * 953 * significant nibble of the interrupt address and the value in ram * 954 * VECTCK. I will therefore divide this discussion into 3 parts based * 955 * on this value. * 956 * * 957 ***************************************************************************************************** 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 105 PPU3/REV 25 microcode | Bus Interrupt Test 959 ***************************************************************************************************** 960 * * 961 * VECTCK = 0,1,2,3 * 962 * If this is the case, you check either the IBF interrupt or the * 963 * port interrupt after the branch to BUSBLOCK, call back and input * 964 * buffer full interrupts are enabled. The routine uses ram PTFULL to * 965 * decide whether to do an IBF interrupt or a port interrupt. If PTFULL * 966 * is equal to zero, we are doing an IBF interrupt. If PTFULL is not * 967 * equal to zero, then CBN and IBF interrupts and all interrupts for * 968 * higher priority ports are disabled (the interrupts for the port * 969 * being tested and lower priority ports are enabled). The port to be * 970 * tested is the same number as the value in VECTCK. If we are doing a * 971 * port test, we set BUSBITS correctly, set ram PINTCK to a value to * 972 * indicate which port we are trying to check, and then branch to the * 973 * routine that does the transfer. After the transfer is done, we take * 974 * an interrupt. The interrupt routine checks to see if we took the * 975 * right interrupt. If this was a port interrupt, we also check to * 976 * ensure that the correct port interrupted, read the bus input registers * 977 * into the FIFO of the interrupting port (doing the proper counting), * 978 * and decrement the counter of bytes remaining to be input. After all * 979 * this happens, control returns to just after the branch into * 980 * BUSBLOCK. * 981 * * 982 * VECTCK = 4,5,6,7,C,D,E,F * 983 * If this is the case, the routine first does a transfer with * 984 * BUSBITS set appropriately and RFR set. Next the RFR bit in ram * 985 * BUSBITS is cleared, CBN and IBF interrupts are enabled, and RFI is * 986 * cleared. The board then does another transfer without reloading the * 987 * bus output registers. (This is accomplished by just doing a store to * 988 * SBCB.) Since RFI and RFR are both clear, this transfer should result * 989 * in the PPU NAKing itself and should set the CBN interrupt. The * 990 * board will then be allowed to take the CBN interrupt. The interrupt * 991 * routine transfers control to a routine which checks to make sure the * 992 * correct interrupt was taken and disables all interrupts. After * 993 * that, RFI is set so the transfer may complete. When the transfer * 994 * completes, the routine checks to see if this was a transfer that set * 995 * bus error (C,D,E,F) and if so, the bus logic is reset. After all * 996 * this, control returns to just after the branch into BUSBLOCK. * 997 * * 998 ***************************************************************************************************** 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 106 PPU3/REV 25 microcode | Bus Interrupt Test 1000 ***************************************************************************************************** 1001 * * 1002 * VECTCK = 8,9,A,B * 1003 * In this routine, the IBF interrupt is used. First, CBN and IBF * 1004 * interrupts are enabled and port interrupts are disabled. Then, the * 1005 * bus transfer is done with force bus parity error set. After the * 1006 * transfer completes, the IBF interrupt is allowed to occur. The * 1007 * interrupt routine disables all interrupts, checks to make sure the * 1008 * correct interrupt was taken, and does a bus logic reset to clear out * 1009 * the bus error. After all this, control goes back to the place just * 1010 * after the branch into BUSBLOCK. * 1011 * * 1012 * * 1013 * After the return from all the BUSBLOCK routines, control * 1014 * will go to INTEST2. Here, all of the words of the bus xfer are * 1015 * read in and checked for correctness. After that, the bus data * 1016 * is incremented in 16 bit chunks. Next, we check to see * 1017 * if we are done yet and proceed if we are. If not, we check to * 1018 * see if ram PTFULL has been zeroed yet. If it is zero, we just * 1019 * loop back to INTEST1. If not zero, we count it down and check * 1020 * to see if the FIFO is four words from being full. If it just * 1021 * became zero we set ram EXSTAT to the appropriate state of the * 1022 * PTST "FIFO not interrupting" bit and check this bit for each * 1023 * port. If we happen to be checking for "FIFO not interrupting" * 1024 * = TRUE, then we also check to make sure the wordcount was * 1025 * decremented to zero. After all this, we loop back to INTEST1. * 1026 * * 1027 ***************************************************************************************************** 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 107 PPU3/REV 25 microcode | Bus Interrupt Test 1029 ***************************************************************************************************** 1030 * * 1031 ** Some comments about this part of the selftest: * 1032 * * 1033 * This explanation was first figured out and written down by * 1034 * Bill Oliver in November 1984. I hope is is accurate and usable. I * 1035 * do have some comments on some things I see wrong with this routine. * 1036 * I did correct some coding mistakes that could have prevented a few * 1037 * kinds of errors from being detected. This routine does not check * 1038 * out the vector addressing logic. This is because all the vectors are * 1039 * set to 000 (the selftest vector) for the entire test. This routine * 1040 * also does not distinguish very well between CBN and IBF interrupts. * 1041 * This is because these two interrupts are always enabled and disabled * 1042 * together. This routine does not check all combinations for all * 1043 * interrupts, i.e. port 0 is only tested for vector 0, port 1 for * 1044 * vector 1, etc. This may not be serious since, theoretically, the 4 * 1045 * LSB's of the interrupt taken should be independent of the other bits * 1046 * of the interrupt address. This routine does not very thoroughly * 1047 * check the priority encoding logic. This is partly because IBF and * 1048 * CBN interrupts are always dis/enabled together and partly because * 1049 * port interrupts are always enabled for the port to be tested and all * 1050 * lower priority ports. Also, because of the way interrupts are * 1051 * enabled and disabled, the interrupt mask register is not very * 1052 * thoroughly tested. A minor gripe might be that this interrupt * 1053 * test only does double word transfers. I think that this interrupt * 1054 * testing routine might have gotten written like it is because of * 1055 * space limitations in the old PPU. This might also explain why this * 1056 * routine seems to be trying to check a lot of functions in addition * 1057 * to interrupts (like the port logic). One thing I don't understand * 1058 * but won't change now is at address CBXFER + 2 where SBHC * 1059 * is done in the same instruction as clearing RFI. (SBHC seems * 1060 * unnecessary.) For now, I am not going to rewrite this interrupt * 1061 * test even though I disagree with the way some of it works. * 1062 * * 1063 * Variable usage * 1064 * RAM ID -- used to make sure we got correct result in SBFT * 1065 * RAM BUSBITS -- used to store into SBCB to do a transfer * 1066 * RAM HW1 -- used for high order 16 bits of 64 bit xfer and for BUSBLOCK branch * 1067 * RAM LW1 -- used for next 16 bits of 64 bit xfer * 1068 * RAM HW2 -- used for next 16 bits of 64 bit xfer * 1069 * RAM HW2 -- used for low order 16 bits of 64 bit xfer * 1070 * RAM VECTCK -- used to verify that we did go to correct interrupt address * 1071 * RAM EXSTAT -- used to check the "FIFO not interrupting" bit of PTST * 1072 * RAM PTFULL -- used to decide if FIFOs are full yet * 1073 * RAM PINTCK -- used to check if proper port interrupted * 1074 * RAM TCON -- counter for transfers * 1075 * RAM WDCNT to WDCNT+3 -- number of 16 bit words left to put in FIFOs * 1076 * * 1077 ***************************************************************************************************** 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 108 PPU3/REV 25 microcode | Bus Interrupt Test 1079 ***************************************************************************************************** 1080 * INTERRUPT test * 1081 * The first thing this test does is call the reset subroutine to * 1082 * reset the FIFO logic for direction out and check to make sure the * 1083 * interrupt bit in PTST (bit 11) is set correctly. * 1084 * This part then checks all the port's PON bits in PTST (bit 14) * 1085 * to see if it is clear. It should be clear because of the DPOE := * 1086 * zero instruction at the beginning of the SELFTEST. * 1087 * This section verifies that the ports interrupt at the * 1088 * proper level of FIFO empty/full-ness and that data transfers to * 1089 * ourselves work okay. * 1090 * The first group of transfers exercise Bus Error on some of * 1091 * the transfers, but then we enter a 'clean' section that does not * 1092 * assert bus error. We must ensure that no bus error is asserted * 1093 * after 800 ms from the start of test. This allows the one second * 1094 * mark to mean that any further bus error is a real bus error. * 1095 * We release the controllers to run their self-tests and etc * 1096 * about one second after the start of the test. * 1097 * No test after this should assert bus error (unless test fails) * 1098 * since this test lets the controllers go and in PPU5 the PFW signal * 1099 * to the controllers is the logical OR of BSE and PFW from the VRA * 1100 * bus. No other board on the system should assert BSE after this * 1101 * routine executes. * 1102 * * 1103 ***************************************************************************************************** 1104 05D2 1105 ORG *+1 AND #7FE 1106 5D2 C4CCE06B71505D369A 1107 INTEST ONES SCR1 *+1,P RESET all ports dir out 5D3 C0CB806AFFC00005D4 1108 SCR0 XOR LIT #0000 SKIP any port status errors? 5D4 C2CC002B37C0000606 1109 ERRTN yes, leave error code in SCR0 5D5 C6CC006B51400035D6 1110 LIT SCR1 3 initialize port counter 5D6 C6C8002AD3400005D8 1111 SCR1 INDX2 CONTRESET2 set index 2 1112 05D8 1113 ORG *+1 AND #7FE 1114 5D8 4ACC0068B1400005D9 1115 CONTRESET2 X2 PTST SCR2 get port status 5D9 C8CBC06AF9440005DB 1116 SCR2 AND LIT SCR2 #4000 SKIP *+2 PON bit set? 1117 5DA 42CC006B51405DA606 1118 LIT SCR0 * ERRTN yes, error 5DB C4CB606AF94FFFF5DC 1119 SCR1 ADD LIT SCR1 #FFFF SKIP no, done? 1120 5DC C6C8002AD3400005D8 1121 SCR1 INDX2 CONTRESET2 no, next port 5DD 7ECC006B51400035E0 1122 LIT SCRF #0003 INTESTA set 1123 5DE 42CC036B50400105DF 1124 X2 LIT RAM WDCNT #0010 wordcount 5DF 7CCB606AF94FFFF5E0 1125 SCRF ADD LIT SCRF #FFFF SKIP for all 5E0 7EC8002AD3400005DE 1126 INTESTA SCRF INDX2 *-2 four ports 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 109 PPU3/REV 25 microcode | Bus Interrupt Test 5E1 C2CC03EB50600405E2 1128 X1 LIT RAM PTFULL #0040 fifos S.B. full at this count 5E2 42CC006B52400005E3 1129 LIT IADR #00 #0000 all 5E3 42CC026B52400005E4 1130 LIT IADR #10 #0000 interrupt 5E4 C2CC046B52400005E5 1131 LIT IADR #20 #0000 vector 5E5 42CC066B52400005E6 1132 LIT IADR #30 #0000 buffer 5E6 42CC086B52400005E7 1133 LIT IADR #40 #0000 locations 5E7 C2CC0A6B52400005E8 1134 LIT IADR #50 #0000 get set 5E8 42CC0C6B52400005E9 1135 LIT IADR #60 #0000 to 5E9 C2CC0E6B52400005EA 1136 LIT IADR #70 #0000 zero 1137 1138 * set up 4 x 16 bit data pattern for the superbus portion of this test 1139 5EA 42CC086B5060F0A5EB 1140 X1 LIT RAM HW1 #0F0A set up ... 5EB 42CC08EB506F0F55EC 1141 X1 LIT RAM LW1 #F0F5 ... initial test ... 5EC C2CC0C6B506AAAA5ED 1142 X1 LIT RAM HW2 #AAAA ... pattern 5ED 42CC0E6B50655555EE 1143 X1 LIT RAM LW2 #5555 1144 5EE C2CC0A6B5067FFF5F2 1145 X1 LIT RAM TCON #7FFF BETEST set up count for section 1146 * testing bus error 1147 05EE 1148 ORG *+0 AND #7FE 05EF 1149 ORG *+1 1150 5EF C0CB806AFFC00005F0 1151 BETEST1 SCR0 XOR LIT #0000 SKIP any errors? 5F0 C2CC002B37C0000606 1152 ERRTN yes, quit now 5F1 40CF6A6B686FFFF5F2 1153 X1 LIT ADD RAM RAM TCON #FFFF SKIP down count and test 5F2 4ECC0A6361705EF608 1154 BETEST X1 RAM SCR3 TCON BETEST1,P INTEST1 do the transfer 1155 * done with count 1156 5F3 C2CC0A6B506FFFF5FA 1157 X1 LIT RAM TCON #FFFF FLTEST set up count for full scale t 1158 5F4 42CC000B37D05F5608 1159 FLTEST1 *+1,P INTEST1 off to do the transfer 5F5 C0CB806AFFC00005F6 1160 SCR0 XOR LIT #0000 SKIP any errors? 5F6 C2CC002B37C0000606 1161 ERRTN yes, quit now 5F7 40CF2A6B6FE30005F9 1162 X1 LIT RSUB RAM TCON #3000 SKIP *+2 check for controller release 5F8 42CC002B54800F05F9 1163 LIT DPOE #F0 release controllers to do sel 5F9 C0CF6A6B686FFFF5FA 1164 X1 LIT ADD RAM RAM TCON #FFFF SKIP down count and test 5FA CCCCCA6B61600075F4 1165 FLTEST X1 LIT AND RAM SCR3 TCON #7 FLTEST1 limit test options in longer 1166 * done with count 1167 5FB 44CC006B71505FD69A 1168 ZERO SCR1 RSTSTCK,P RESET set ports dir IN 1169 05FC 1170 ORG *+0 AND #7FE 05FD 1171 ORG *+1 1172 5FD 40CB806AFFC00005FE 1173 RSTSTCK SCR0 XOR LIT 0 SKIP status okay? 5FE C2CC002B37C0000606 1174 ERRTN no, status error 1175 1176 ***************************************************************************************************** 1177 * * 1178 * Now check all the port's PON bits in PTST to see if they got * 1179 * set. * 1180 * * 1181 ***************************************************************************************************** 1182 5FF C6CC006B5140003604 1183 LIT SCR1 3 PONCHECK5 initialize port counter 1184 0600 1185 ORG *+1 AND #7FE 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 110 PPU3/REV 25 microcode | Bus Interrupt Test 1186 600 4ACC0068B140000601 1187 PONCHECK4 X2 PTST SCR2 get port status 601 48CBC06AF944000602 1188 SCR2 AND LIT SCR2 #4000 SKIP PON bit set? 1189 602 42CC006B5140602606 1190 LIT SCR0 * ERRTN no,error 603 C4CB606AF94FFFF604 1191 SCR1 ADD LIT SCR1 -1 SKIP yes,done? 1192 604 C6C8002AD340000600 1193 PONCHECK5 SCR1 INDX2 PONCHECK4 no, next port 605 C2CC006B5140000606 1194 LIT SCR0 #0000 ERRTN done, no errors 1195 1196 ***************************************************************************************************** 1197 * End of Test Code * 1198 * Come here with error code in SCR0. 0 => no error, otherwise * 1199 * microcode address where failure was detected. * 1200 ***************************************************************************************************** 1201 606 42CC002B54C0003607 1202 ERRTN LIT INDX1 #0003 607 C2C815EAD0600003D9 1203 X1 SCR0 RAM ERRFLAG ENDTEST end of test 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 111 PPU3/REV 25 microcode | Bus Interrupt Test 1205 ***************************************************************************************************** 1206 * Bus transfer Routine * 1207 * This SR transfers one word on the bus using the scheme indicated * 1208 * in SCR3. We verify that the transfer happened okay. On return * 1209 * SCR0 contains zero or an error code. * 1210 ***************************************************************************************************** 1211 0608 1212 ORG *+1 AND #7FE 1213 608 C2CC006B5140000609 1214 INTEST1 LIT SCR0 #0000 initialize SCR0 609 40CCD46B6060F0060A 1215 X1 LIT AND RAM RAM BUSBITS #0F00 a little pre-processing 60A CCC8C2EAF06000F60B 1216 X1 SCR3 AND LIT RAM VECTCK #000F SCR3 = 000F for vector check 60B 40CF82EB6FE000060C 1217 X1 LIT XOR RAM VECTCK #0000 SKIP if 0 60C CECA006ADFF060F6F0 1218 X1 SCR3 INTEST2,P DB0 BUSBLOCK 60D C0CCA2EB606000160C 1219 X1 LIT IOR RAM RAM VECTCK #0001 *-1 make the check 1 1220 060E 1221 ORG *+0 AND #7FE 060F 1222 ORG *+1 1223 60F 40CB806AFFC0000610 1224 INTEST2 SCR0 XOR LIT #0000 SKIP any prev. int errors? 610 C2CF001B37C00007FE 1225 POP STERR yes, leave error code in SCR0 1226 611 52CC006DF140000612 1227 SBHC SCR4 read 612 D6CC006E7140000613 1228 SBLC SCR5 four 613 DACC006EF140000614 1229 SBHD SCR6 input 614 DECC006F7140000615 1230 SBLD SCR7 registers 1231 615 50CB886AEFE0000616 1232 X1 SCR4 XOR RAM HW1 #0000 SKIP high word 1 ok? 616 C2CF007B51406167FE 1233 LIT SCR0 * POP STERR 617 D4CB88EAEFE0000618 1234 X1 SCR5 XOR RAM LW1 #0000 SKIP low word 1 ok? 618 42CF007B51406187FE 1235 LIT SCR0 * POP STERR 619 58CB8C6AEFE000061A 1236 X1 SCR6 XOR RAM HW2 #0000 SKIP high word 2 ok? 61A C2CF007B514061A7FE 1237 LIT SCR0 * POP STERR 61B 5CCB8E6AEFE000061C 1238 X1 SCR7 XOR RAM LW2 #0000 SKIP low word 2 ok? 61C C2CF007B514061C7FE 1239 LIT SCR0 * POP STERR 61D 40CC686B606000161E 1240 X1 LIT ADD RAM RAM HW1 #0001 modify the test ... 61E 40CC68EB606001361F 1241 X1 LIT ADD RAM RAM LW1 #0013 ... pattern to exercize ... 61F 40CC6C6B6060105620 1242 X1 LIT ADD RAM RAM HW2 #0105 ... the drivers and ... 620 C0CC6E6B606100B621 1243 X1 LIT ADD RAM RAM LW2 #100B ... receivers 621 40CF83EB6FE0000623 1244 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 must we bother? 622 C2CF001B37C00007FE 1245 POP STERR not with that shit 623 C0CC63EB606FFFF624 1246 X1 LIT ADD RAM RAM PTFULL #FFFF decrement the counter 624 42CC002B37C0000625 1247 NOP for lineup 625 C0CF83EB6FE0000627 1248 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 check for all FIFOs full? 626 42CC106B506080062A 1249 X1 LIT RAM EXSTAT #0800 INTEST3 say bit 11=1=ints off 627 40CF83EB6FE0010628 1250 X1 LIT XOR RAM PTFULL #0010 SKIP 12 in all output FIFOs? 628 C2CF001B37C00007FE 1251 POP STERR not 12 yet 629 C2CC106B506000062A 1252 X1 LIT RAM EXSTAT #0000 say bit 11=0=ints on 62A 7ECC006B5140003634 1253 INTEST3 LIT SCRF #0003 INTEST6 init index and load it 62B C2CC0068B14000062C 1254 INTEST4 PTST SCR0 read port int stat 62C C0C8C06AF14080062D 1255 SCR0 AND LIT SCR0 #0800 interrupt bit 11 only 62D 40CB906AE96000062F 1256 X1 SCR0 XOR RAM SCR0 EXSTAT #0000 SKIP *+2 good? 62E C0CFD06B6FE0800630 1257 X1 LIT AND RAM EXSTAT #0800 SKIP *+2 is this a full test? 62F C2CF007B514062F7FE 1258 LIT SCR0 * POP STERR ungood 630 C2CC002B37C0000633 1259 INTEST5 don't check word count 631 40CF836B6FC0000632 1260 X2 LIT XOR RAM WDCNT #0000 SKIP all 4 word counts should be 0 632 C2CF007B51406327FE 1261 LIT SCR0 * POP STERR one of them isn't 633 7CCB606AF94FFFF634 1262 INTEST5 SCRF ADD LIT SCRF #FFFF SKIP done? 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 112 PPU3/REV 25 microcode | Bus Interrupt Test 634 7EC8002AD34000062B 1263 INTEST6 SCRF INDX2 INTEST4 not done, back 635 C2CF001B37C00007FE 1264 POP STERR get outta here 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 113 PPU3/REV 25 microcode | Bus Interrupt Test 1266 * SUBROUTINES 1267 1268 * branch here on counter in SCR3, SCR1 (5-0) = IMR, 15-8 to check vector addr. 1269 1270 BLOCK 16 1271 >>>>>>>>>> 6F0 C2CC002B55C000F637 1272 >BUSBLOCK LIT IMR #000F DATA0 IBFINT,P0INT 6F1 C2CC002B55C000F63B 1273 > LIT IMR #000F DATA1 IBFINT,P1INT 6F2 42CC002B55C000F63F 1274 > LIT IMR #000F DATA2 IBFINT,P2INT 6F3 C2CC002B55C000F643 1275 > LIT IMR #000F DATA3 IBFINT,P3INT 6F4 C2CC000B37D0648647 1276 > DATA4A,P DATA4 CBINT 6F5 C2CC000B37D064A649 1277 > DATA5A,P DATA5 CBINT 6F6 42CC000B37D064C64B 1278 > DATA6A,P DATA6 CBINT 6F7 C2CC000B37D064E64D 1279 > DATA7A,P DATA7 CBINT 6F8 C2CC002B55C000F64F 1280 > LIT IMR #000F DATA8 IBFINT-BSER 6F9 42CC002B55C000F650 1281 > LIT IMR #000F DATA9 IBFINT-BSER 6FA C2CC002B55C000F651 1282 > LIT IMR #000F DATAA IBFINT-BSER 6FB C2CC002B55C000F652 1283 > LIT IMR #000F DATAB IBFINT-BSER 6FC 42CC000B37D0654653 1284 > DATACA,P DATAC CBINT-BSER 6FD C2CC000B37D0656655 1285 > DATADA,P DATAD CBINT-BSER 6FE C2CC000B37D0658657 1286 > DATAEA,P DATAE CBINT-BSER 6FF C2CC000B37D065A659 1287 > DATAFA,P DATAF CBINT-BSER 1288 >>>>>>>>>> 1289 ENDBLOCK 1290 0636 1291 ORG *+0 AND #7FE 0637 1292 ORG *+1 1293 637 C0CF83EB6FE0000639 1294 DATA0 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 PORT0 or IBF? 638 C0CCB46B606005B66A 1295 DATA0A X1 LIT IOR RAM RAM BUSBITS #005B ENAINT SLOT+F0W1+RFR+DW+RTO 639 C2CC002B55C003E63A 1296 LIT IMR #3E ENABLE port 0 int 63A C2CC026B506C0DE638 1297 X1 LIT RAM PINTCK #C0DE DATA0A say port 0 int expected 63B 40CF83EB6FE000063D 1298 DATA1 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 1 or IBF? 63C C0CCB46B606005B66A 1299 DATA1A X1 LIT IOR RAM RAM BUSBITS #005B ENAINT SLOT+F0W1+RFR+DW+RTO 63D C2CC002B55C003C63E 1300 LIT IMR #003C enable port 1 ints (& P0) 63E 42CC026B506111163C 1301 X1 LIT RAM PINTCK #1111 DATA1A say port 1 int expected 63F C0CF83EB6FE0000641 1302 DATA2 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 2 or IBF? 640 40CCB46B606002B66A 1303 DATA2A X1 LIT IOR RAM RAM BUSBITS #002B ENAINT SLOT+F1W2+RFR+DW+RTO 641 C2CC002B55C0038642 1304 LIT IMR #0038 enable port 2 int (&P1&P0) 642 C2CC026B5062222640 1305 X1 LIT RAM PINTCK #2222 DATA2A port 2 int exp. 643 40CF83EB6FE0000645 1306 DATA3 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 3 or IBF? 644 C0CCB46B60600FB66A 1307 DATA3A X1 LIT IOR RAM RAM BUSBITS #00FB ENAINT SLOT+4FLAGS+RFR+DW+RTO 645 C2CC002B55C0030646 1308 LIT IMR #0030 enable port 3 int (&P2&P1&P0) 646 42CC026B5063333644 1309 X1 LIT RAM PINTCK #3333 DATA3A port 3 int exp. 647 C0CCB46B606000B669 1310 DATA4 X1 LIT IOR RAM RAM BUSBITS #000B DISAINT SLOT+RFR+DW+RTO 648 40CC946B606000865C 1311 DATA4A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER SLOT+DW+RTO 649 C0CCB46B606005B669 1312 DATA5 X1 LIT IOR RAM RAM BUSBITS #005B DISAINT SLOT+F0W2+F0W1+RFR+DW+RTO 64A 40CC946B606000865C 1313 DATA5A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER SLOT+FOW2+F0W1+DW+RTO 64B 40CCB46B606002B669 1314 DATA6 X1 LIT IOR RAM RAM BUSBITS #002B DISAINT LOT+F1W1+RFR+DW+RTO 64C 40CC946B606000865C 1315 DATA6A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER SLOT+F1W1+DW+RTO 64D C0CCB46B60600FB669 1316 DATA7 X1 LIT IOR RAM RAM BUSBITS #00FB DISAINT SLT+F0W1+F1W2+F0W2+RFR+DW+RTO 64E 40CC946B606000865C 1317 DATA7A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER SLOT+DW+RTO 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 114 PPU3/REV 25 microcode | Bus Interrupt Test 64F 40CCB46B606400B66A 1319 DATA8 X1 LIT IOR RAM RAM BUSBITS #400B ENAINT BPE+RFR+DW+RTO 650 40CCB46B606405B66A 1320 DATA9 X1 LIT IOR RAM RAM BUSBITS #405B ENAINT BPE+F0W2+RFR+DW+RTO+F0W1 651 C0CCB46B606402B66A 1321 DATAA X1 LIT IOR RAM RAM BUSBITS #402B ENAINT BPE+F0W1+DFR+DW+RTO 652 40CCB46B60640FB66A 1322 DATAB X1 LIT IOR RAM RAM BUSBITS #40FB ENAINT BPE+SLT+F0W1+F1W2+F0W2+RFR+DW 653 40CCB46B606400B669 1323 DATAC X1 LIT IOR RAM RAM BUSBITS #400B DISAINT F.D. = 0 + BE 654 C0CC946B606400865C 1324 DATACA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER SLOT+DW+RTO 655 40CCB46B606405B669 1325 DATAD X1 LIT IOR RAM RAM BUSBITS #405B DISAINT F.D. = 1 + BE 656 C0CC946B606400865C 1326 DATADA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER SLOT+DW+RTO 657 C0CCB46B606402B669 1327 DATAE X1 LIT IOR RAM RAM BUSBITS #402B DISAINT F.D. = 2 + BE 658 C0CC946B606400865C 1328 DATAEA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER SLOT+DW+RTO 659 40CCB46B60640FB669 1329 DATAF X1 LIT IOR RAM RAM BUSBITS #40FB DISAINT FLGS=7+BPE 65A C0CC946B606400865C 1330 DATAFA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER BUSBITS + DW + RTO 1331 1332 ***************************************************************************************************** 1333 * If this transfer is to be a callback test, we come here * 1334 * to set up the callback type of bus transfer. * 1335 * Needs 2 stack locations. * 1336 ***************************************************************************************************** 1337 065C 1338 ORG *+1 AND #7FE 1339 65C C2CC002B55C000F65D 1340 CBXFER LIT IMR #000F enable CBN-IBF ints 65D CACC006B514000065E 1341 LIT SCR2 #0000 allow the call back interrupt 65E C0CC000DF29065F671 1342 SBHC ZERO SBRFI *+1,P SXFER IBF=0,RFI=0, int returns *+1 65F C2CC002B5280004660 1343 LIT SBRFI #0004 set RFI 660 6ACC006D3140000661 1344 SBST SCRA and wait for IBF 661 E8CBA06AFFCFFBF663 1345 SCRA IOR LIT #FFBF SKIP *+2 662 6ACC006D3140000661 1346 SBST SCRA *-1 keep trying 663 E8CBC06AFFC0040665 1347 SCRA AND LIT #0040 SKIP *+2 IBF? 664 E8CBC06AFFC4000666 1348 SCRA AND LIT #4000 SKIP *+2 bus error? 665 42CF007B51406657FE 1349 LIT SCR0 * POP STERR no IBF 666 C2CF001B37C00007FE 1350 POP STERR no bus error, no reset 667 42CC002B37C0000697 1351 BSRST reset bus error 1352 1353 ***************************************************************************************************** 1354 * Routine to load the data for the transfer. If this is * 1355 * to be an RFI type transfer, then we go ahead and start it. * 1356 * Needs 2 stack locations (one is for interrupt routine). * 1357 ***************************************************************************************************** 1358 0668 1359 ORG *+0 AND #7FE 0669 1360 ORG *+1 1361 669 CACC006B514FFFF66B 1362 DISAINT LIT SCR2 #FFFF *+2 say no interrupts 66A CACC006B514000066B 1363 ENAINT LIT SCR2 #0000 allow interrupts 66B C0CFD46B6FE400066D 1364 X1 LIT AND RAM BUSBITS #4000 SKIP *+2 set bus error? 66C C2CC002B554400066D 1365 LIT SBCB #4000 yes 66D 42CC0803642000066E 1366 X1 RAM SBHC HW1 load 66E C2CC0883646000066F 1367 X1 RAM SBLC LW1 all 66F C2CC0C0363A0000670 1368 X1 RAM SBHD HW2 four 670 42CC0E0363E0000671 1369 X1 RAM SBLD LW2 words 671 40CCD40B656BFFF673 1370 SXFER X1 LIT AND RAM SBCB BUSBITS #BFFF INTLOOP start xfr w/o FBPE 1371 0672 1372 ORG *+0 AND #7FE 0673 1373 ORG *+1 1374 673 48CB806AFFC0000674 1375 INTLOOP SCR2 XOR LIT #0000 SKIP allow interrupts? 674 C2CF001B37C00007FE 1376 POP STERR no 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 115 PPU3/REV 25 microcode | Bus Interrupt Test 675 42CC002B37C0000676 1377 NOP 2 ticks (total of 6 ticks) 676 EACC006D3140000677 1378 SBST SCRA and wait for IBF or CBN 677 E8CBA06AFFCFBBF679 1379 SCRA IOR LIT #FBBF SKIP *+2 678 EACC006D3140000677 1380 SBST SCRA *-1 keep trying 679 42CC002B37C000067A 1381 NOP (to keep the address right) 67A 42CC002B37C0000E7B 1382 I awaaaayyyy weeee gooooo 67B 48CB806AFFC000067D 1383 SCR2 XOR LIT #0000 SKIP *+2 have we interrupted? 67C C2CF007B514067C7FE 1384 LIT SCR0 * POP STERR no 67D C2CF001B37C00007FE 1385 POP STERR yes 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 116 PPU3/REV 25 microcode | Bus Interrupt Test 1387 1388 ***************************************************************************************************** 1389 * Here lie routines to process the expected interrupt. * 1390 * We go to different routines depending on the interrupt * 1391 * vector that we took. * 1392 * * 1393 * Needs one stack location (the one for the interrupt). * 1394 ***************************************************************************************************** 1395 1396 * Branch table used on interrupt condition for entry 1397 * to this interrupt routine. 1398 1399 BLOCK 4,PINTRIOR 1400 >>>>>>>>>> 734 E6CC006B514C0DE67E 1401 >PINTRTN LIT SCR9 #C0DE PINTSUB INDX branch boundary 735 E6CC006B514111167E 1402 > LIT SCR9 #1111 PINTSUB 736 E6CC006B514222267E 1403 > LIT SCR9 #2222 PINTSUB 737 E6CC006B514333367E 1404 > LIT SCR9 #3333 PINTSUB 1405 >>>>>>>>>> 1406 ENDBLOCK 1407 067E 1408 PINTSUB EQU * 67E C2CC002B55C003F67F 1409 LIT IMR #003F shut em off 67F 60CB82EAEFE0000681 1410 X1 SCR8 XOR RAM VECTCK #0000 SKIP *+2 to the correct vector? 680 C0CF83EB6FE0000682 1411 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 IBF or port INT? 681 42CC006B5140681683 1412 LIT SCR0 * *+2 wrong vector address 682 64CB826AEFE0000684 1413 X1 SCR9 XOR RAM PINTCK #0000 SKIP *+2 did expected port interrupt? 683 CACF007B514FFFF7FE 1414 LIT SCR2 #FFFF POP STERR IBF, return 684 42CC006B5140684683 1415 LIT SCR0 * *-1 wrong port 685 C2C4002DF2C0000686 1416 C SBHC DPOUT 686 C2CC006E72C0000687 1417 T4 SBLC DPOUT 687 C2CC002EF2C0000688 1418 SBHD DPOUT 688 42CC002F72C0000689 1419 SBLD DPOUT 689 42CC002B37C000068A 1420 NOP 68A 4AD4006B514FFFF68B 1421 STC,C LIT SCR2 #FFFF say we interrupted 68B C0EF237B60400047FE 1422 TWC,X2 LIT RSUB RAM RAM WDCNT #0004 POP STERR wdcnt-4 1423 068C 1424 ORG *+0 AND #7FE 068D 1425 ORG *+1 1426 68D E0CB82EAEFE000068F 1427 CBRTN X1 SCR8 XOR RAM VECTCK #0000 SKIP *+2 correct int vector? 68E C2CC006B5140000690 1428 LIT SCR0 #0000 *+2 yes 68F 42CC006B514068F690 1429 LIT SCR0 * no 690 C2CC002B55C003F691 1430 LIT IMR #003F shut em off 691 CACF007B514FFFF7FE 1431 LIT SCR2 #FFFF POP STERR return 1432 692 42CC002B55C003F693 1433 BSERTN LIT IMR #003F shut em off 693 60CB82EAEFE0000695 1434 X1 SCR8 XOR RAM VECTCK #0000 SKIP *+2 correct int vector? 694 C2CC006B5140000696 1435 LIT SCR0 #0000 *+2 yes 695 C2CC006B5140695696 1436 LIT SCR0 * no 696 CACC006B514FFFF697 1437 LIT SCR2 #FFFF 697 C2CC006B31C0000698 1438 BSRST T4 SBRST 698 C2CC002B37C0000699 1439 NOP 699 C2CF001B55400007FE 1440 LIT SBCB #0000 POP STERR 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 117 PPU3/REV 25 microcode | Bus Interrupt Test 1442 1443 ***************************************************************************************************** 1444 * Reset subroutine to prepare for and clean up after this * 1445 * bus test. * 1446 * Needs 2 stack locations. * 1447 * * 1448 * SCR1 = DIRECTION bit COMING IN * 1449 * SCR2 = port # 3 DECREMENTED TO 0 * 1450 * SCR0 = 0 => port status good * 1451 * # 0 => error code (ucode PC address) * 1452 * * 1453 ***************************************************************************************************** 1454 069A 1455 ORG *+1 AND #7FE 1456 69A CACC006B514000369E 1457 RESET LIT SCR2 #0003 RESET1 set counter for 4 ports 69B C0CB806AFFC000069C 1458 RESET1A SCR0 XOR LIT #0000 SKIP check for any error 69C C2CF001B37C00007FE 1459 POP STERR go report error 69D C8CB606AF94FFFF69E 1460 SCR2 ADD LIT SCR2 #FFFF SKIP count port counter 69E CAC8000AD35069B6A1 1461 RESET1 SCR2 INDX2 RESET1A,P RESET2 69F C2CF001B37C00007FE 1462 POP STERR return, all ports done 1463 06A0 1464 ORG *+0 AND #7FE 06A1 1465 ORG *+1 1466 6A1 46C8002AD5800006A2 1467 RESET2 SCR1 DPDIR set direction 6A2 42CC002B30C00006A3 1468 DPRST reset FIFOs 6A3 C2CC006B37C00006A4 1469 T4 tick 6A4 42CC006B37C00006A5 1470 T4 tock 6A5 C2CC002B37C00006A6 1471 T2 tick 6A6 C2CC002B30C00006A7 1472 DPRST tock 6A7 C2CC006B37C00006A8 1473 T4 clock the status in 6A8 42CC0068B1400006A9 1474 PTST SCR0 and pull it 6A9 C4CBA06AFFCFFFE6AB 1475 SCR1 IOR LIT #FFFE SKIP *+2 direction in? 6AA C0CBC06AFFC08006AC 1476 SCR0 AND LIT #0800 SKIP *+2 in,int off? 6AB C0CBA06AFFCF7FF6AC 1477 SCR0 IOR LIT #F7FF SKIP out,int on? 6AC 42CF007B51406AC7FE 1478 LIT SCR0 * POP STERR return with SCR0 = ECODE 6AD 42CF007B51400007FE 1479 LIT SCR0 #0000 POP STERR no errors 3050 END 3052 IF ERRFLAG NE WRURES4B, Selftest flags do not match! 06AD 3054 MAXPCHIGH REEQU *-1 maximum PC in high RAM (400-7FF) 3056 IF MAXPCHIGH GE BLOCKORG+16, we've collided with the BLOCK structure 3057 TITLE.MAC PROM Use Parameters & PPU Halts 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 118 PPU3/REV 25 microcode | PROM Use Parameters & PPU Halts 3058 06F0 3059 LEASTBLK EQU BLOCKORG+16 0058 3060 WRDSLEFT EQU #400-MAXPCLOW+LEASTBLK-MAXPCHIGH 3061 0001 3062 SKIPWSTE EQU WSTECNTR-WSTEPNTR 0008 3063 BLK4WSTE EQU (4-B4.USED)*4 0008 3064 BLK8WSTE EQU (2-B8.USED)*8 3065 3066 EXPAND ON 3067 3068 3069 * WORDS remaining = 0088 3070 3071 3072 * SKIP waste = 0001 3073 3074 * BLOCK 4 waste = 0008 3075 3076 * BLOCK 8 waste = 0008 3078 ***************************************************************************************************** 3079 * * 3080 * PPU HALT'S * 3081 * * 3082 ***************************************************************************************************** 07F0 3084 ORG #7F0 3086 >>>>>>>>>> 7F0 42CC002B37C00007F0 3087 >DIDNTPOP * POP didn't POP 7F1 C2CC002B37C00007F1 3088 >NOBRANCH * illegal DBn or INDX branch 7F2 C2CC002B37C00007F2 3089 >CIRESERR * Call Back Needed Error 7F3 42CC002B37C00007F3 3090 >CBNERR * Call Back Needed Error 7F4 C2CC002B37C00007F4 3091 >CIINPERR * Call Back Needed Error 7F5 42CC002B37C00007F5 3092 >FINPERR * FIFO Input Error 7F6 42CC002B37C00007F6 3093 >FOUTERR * FIFO Output Error 7F7 C2CC002B37C00007F7 3094 >MEM1ERR * Memory Fetch Error #1 7F8 C2CC002B37C00007F8 3095 >MEM2ERR * Memory Fetch Error #2 7F9 42CC002B37C00007F9 3096 >BADINP * Bad Command or Data Input 7FA 42CC002B37C00007FA 3097 >RTOERR * RTO time-out Error 7FB C2CC002B37C00007FB 3098 >RESERR * Response time-out 7FC 42CC002B37C00007FC 3099 >WFBERR * Waiting for BUS time-out 7FD C2CC002B37C00007FD 3100 >MEM3ERR * Memory Fetch Error #3 7FE C2CC002B37C00007FE 3101 >STERR * BUS Self-test Error 7FF 42CC002B37C00007FF 3102 >PFWWAIT * Waiting for PFW to go away 3103 >>>>>>>>>> 3105 TITLE.MAC cross-reference table 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 119 PPU3/REV 25 microcode | cross-reference table 3106 END NO LINES WITH ERRORS 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 120 PPU3/REV 25 microcode | cross-reference table ABLK 0700 316 0700 316 0700 317 0701 318 0702 319 0703 320 0704 321 0705 322 0706 323 0707 324 0708 325 0709 326 070A 327 070B 328 070C 329 070D 330 070E 331 070F 765 056A 773 0572 774 0573 ABORT 0265 2073 0265 2045 0771 ABORTPRT 0267 2076 0267 1355 0142 2069 0263 2074 0266 ABTCLR 9A89 845 0000 2045 0771 ABTSET 8080 846 0000 2073 0265 ACK 000E 560 0000 1258 0121 1290 012B 1406 0153 ADATAXOR 0010 752 0000 1455 016C 1942 0231 ADDIR 02E4 2347 02E4 2049 0775 2051 0777 ADDRESS 0028 434 0028 1380 07B8 1392 07E4 1453 016B 1939 022F 2030 0259 ALLOWINT 0299 2192 0299 2169 0290 2189 0297 ALUCHECK 0575 779 0575 768 056D ALUTEST 056A 765 056A 760 0569 ALUTEST1 056C 767 056C 786 057C 788 057E 797 0587 B2LISBIG 02E3 2331 02E3 2326 02E1 B4.ORG 0738 973 00B9 973 00B9 973 07E0 973 07E0 1390 014E 1390 07E4 1390 07E4 1887 0211 1887 07E8 1887 07E8 2154 028A 2154 07EC 2154 07EC 2289 02CE 2289 02CE 2289 0760 2289 0760 2598 0374 2598 0764 2598 0764 2731 0393 2731 0768 2731 0768 2978 03D3 2978 076C 2978 076C 2992 03D6 2992 03D6 2992 0740 2992 0740 208 0462 208 0744 208 0744 217 0462 217 0748 217 0748 226 0462 226 074C 226 074C 235 0462 235 0462 235 0730 235 0730 1399 067E 1399 0734 1399 0734 B4.USED 0002 368 0000 973 00B9 973 00B9 973 07E0 973 07E0 973 07E0 1390 014E 1390 07E4 1390 07E4 1390 07E4 1887 0211 1887 07E8 1887 07E8 1887 07E8 2154 028A 2154 07EC 2154 07EC 2154 07EC 2289 02CE 2289 02CE 2289 0760 2289 0760 2289 0760 2598 0374 2598 0764 2598 0764 2598 0764 2731 0393 2731 0768 2731 0768 2731 0768 2978 03D3 2978 076C 2978 076C 2978 076C 2992 03D6 2992 03D6 2992 0740 2992 0740 2992 0740 208 0462 208 0744 208 0744 208 0744 217 0462 217 0748 217 0748 217 0748 226 0462 226 074C 226 074C 226 074C 235 0462 235 0462 235 0730 235 0730 235 0730 1399 067E 1399 0734 1399 0734 1399 0734 3063 06AE B8.ORG 0758 1275 0129 1275 0129 1275 07B0 1275 07B0 1378 014E 1378 07B8 1378 07B8 1560 0190 1560 0190 1560 0790 1560 0790 1762 01E6 1762 0798 1762 0798 2693 0392 2693 0392 2693 0750 2693 0750 B8.USED 0001 369 0000 1275 0129 1275 0129 1275 07B0 1275 07B0 1275 07B0 1378 014E 1378 07B8 1378 07B8 1378 07B8 1560 0190 1560 0190 1560 0790 1560 0790 1560 0790 1762 01E6 1762 0798 1762 0798 1762 0798 2693 0392 2693 0392 2693 0750 2693 0750 2693 0750 3064 06AE BADCOMM 01E5 1760 01E5 1755 01E2 1765 0799 1767 079B 1770 079E 1771 079F 1864 0200 1919 0223 1947 0232 1962 0789 1963 078A 1964 078B 1965 078C 1966 078D 1967 078E 1968 078F 2008 024A 2038 025E 2053 0779 2054 077A 2055 077B 2056 077C 2057 077D 2058 077E 2059 077F 2366 02F0 BADDATA 02F0 2366 02F0 2114 027A 2120 027C 2231 02AC 2237 02B0 BADINP 07F9 3096 07F9 1760 01E5 BC1CLR 1E0B 844 0000 2168 028F 2175 0295 BCACTIV 00EB 1086 00EB 1083 00C5 BCINT 0200 792 0000 842 0000 1727 01C7 BCLAST 0020 788 0000 831 0000 844 0000 845 0000 2204 029E BCNLAST 027C 2120 027C 2108 0276 BCNRDY 0040 789 0000 834 0000 844 0000 845 0000 1500 0179 2265 02BD 2269 02BF 2309 02D2 2313 02D5 BCNT 0054 448 0054 993 00C1 1026 00D1 1080 00E9 1519 0181 1974 0236 2166 028D 2174 0294 2189 0297 2273 02C1 2324 02DF 2589 0373 2646 0321 2682 0390 2683 0391 2745 0395 2787 037B 2816 03A6 2845 03BA BCNT2 0068 454 0068 1976 0238 2256 02B6 2263 02BB 2272 02C0 2307 02D0 2323 02DE 2326 02E1 2677 038D 2680 038F 2815 03A5 BCOVERUN 0048 444 0048 991 00C0 1671 01C9 2085 0270 2268 02BE 2312 02D4 2654 037C 2668 0384 2807 03A1 2814 03A4 BCRATEOR 0092 832 0000 1661 01C3 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 121 PPU3/REV 25 microcode | cross-reference table BCROLL 0010 787 0000 831 0000 832 0000 834 0000 843 0000 844 0000 845 0000 1730 01D7 2666 0383 2812 03A3 BETEST 05F2 1154 05F2 1145 05EE BETEST1 05EF 1151 05EF 1154 05F2 BFGODIE 02F2 2396 02F2 1697 0012 1698 0013 2864 0062 2865 0063 2897 0072 2898 0073 2935 0082 2936 0083 BIFT 0088 463 0088 1766 079A 1865 0201 2428 0302 2454 0311 2500 032B 2506 0330 2510 0334 BIHC 0078 459 0078 1753 01E0 1756 01E3 1764 0798 1913 021F 1914 0220 2013 024E 2426 0300 2448 030D 2496 0327 2512 0336 BIHD 0080 461 0080 2011 024C 2437 0306 2498 0329 2516 033A BILC 007C 460 007C 1768 079C 1870 0204 1881 020C 1912 021E 2009 024B 2427 0301 2497 0328 2514 0338 BILD 0084 462 0084 2012 024D 2438 0307 2499 032A 2518 033C BIREAD 021C 1910 021C 1766 079A BIRTAB 0798 1764 0798 1758 01E4 BIST 008C 464 008C 2416 02FB 2418 02CB 2424 02FF 2430 0303 2432 02D3 2444 030A 2447 030C 2495 0326 2504 032E 2508 0332 BIWRITE 0248 2006 0248 1764 0798 BLANKS 0000 636 0000 BLK.SIZE 0004 973 00B9 973 00B9 980 07E4 980 07E4 1124 00FD 1124 00FD 1124 00FD 1124 00FD 1143 07E0 1143 07E0 1228 011B 1228 011B 1228 011B 1228 011B 1247 07D0 1247 07D0 1275 0129 1275 0129 1275 0129 1286 07B8 1286 07B8 1305 0131 1305 0131 1305 0131 1305 0131 1324 07B0 1324 07B0 1378 014E 1378 014E 1378 014E 1390 07C0 1390 07C0 1390 014E 1390 014E 1397 07E8 1397 07E8 1560 0190 1560 0190 1560 0190 1571 0798 1571 0798 1762 01E6 1762 01E6 1762 01E6 1773 07A0 1773 07A0 1887 0211 1887 0211 1894 07EC 1894 07EC 1951 0234 1951 0234 1951 0234 1951 0234 1970 0790 1970 0790 2042 0260 2042 0260 2042 0260 2042 0260 2061 0780 2061 0780 2154 028A 2154 028A 2161 07F0 2161 07F0 2289 02CE 2289 02CE 2296 0764 2296 0764 2598 0374 2598 0374 2605 0768 2605 0768 2693 0392 2693 0392 2693 0392 2704 0758 2704 0758 2731 0393 2731 0393 2738 076C 2738 076C 2978 03D3 2978 03D3 2985 0770 2985 0770 2992 03D6 2992 03D6 2999 0744 2999 0744 208 0462 208 0462 215 0748 215 0748 217 0462 217 0462 224 074C 224 074C 226 0462 226 0462 233 0750 233 0750 235 0462 235 0462 242 0734 242 0734 272 0472 272 0472 272 0472 272 0472 291 0730 291 0730 293 0472 293 0472 293 0472 293 0472 312 0720 312 0720 314 0472 314 0472 314 0472 314 0472 333 0710 333 0710 1270 0636 1270 0636 1270 0636 1270 0636 1289 0700 1289 0700 1399 067E 1399 067E 1406 0738 1406 0738 BLK4WSTE 0008 3063 06AE 3074 06AE BLK8WSTE 0008 3064 06AE 3076 06AE BLOCKADD 0734 973 07E0 980 07E4 980 07E4 1124 07D0 1143 07E0 1143 07E0 1228 07C0 1247 07D0 1247 07D0 1275 07B0 1286 07B8 1286 07B8 1305 07A0 1324 07B0 1324 07B0 1378 07B8 1390 07C0 1390 07C0 1390 07E4 1397 07E8 1397 07E8 1560 0790 1571 0798 1571 0798 1762 0798 1773 07A0 1773 07A0 1887 07E8 1894 07EC 1894 07EC 1951 0780 1970 0790 1970 0790 2042 0770 2061 0780 2061 0780 2154 07EC 2161 07F0 2161 07F0 2289 0760 2296 0764 2296 0764 2598 0764 2605 0768 2605 0768 2693 0750 2704 0758 2704 0758 2731 0768 2738 076C 2738 076C 2978 076C 2985 0770 2985 0770 2992 0740 2999 0744 2999 0744 208 0744 215 0748 215 0748 217 0748 224 074C 224 074C 226 074C 233 0750 233 0750 235 0730 242 0734 242 0734 272 0720 291 0730 291 0730 293 0710 312 0720 312 0720 314 0700 333 0710 333 0710 1270 06F0 1289 0700 1289 0700 1399 0734 1406 0738 1406 0738 BLOCKON 0000 367 0000 973 00B9 973 07E0 980 00B9 1088 00EC 1124 00FD 1124 07D0 1143 00FD 1228 011B 1228 07C0 1247 011B 1275 0129 1275 07B0 1286 0129 1305 0131 1305 07A0 1324 0131 1378 014E 1378 07B8 1390 07C0 1390 014E 1390 07E4 1397 014E 1505 017C 1560 0190 1560 0790 1571 0190 1590 019A 1614 01A8 1667 01C6 1752 01E0 1762 01E6 1762 0798 1773 01E6 1869 0204 1887 0211 1887 07E8 1894 0211 1951 0234 1951 0780 1970 0234 2005 0248 2042 0260 2042 0770 2061 0260 2134 027E 2154 028A 2154 07EC 2161 028A 2203 029E 2289 02CE 2289 0760 2296 02CE 2450 030E 2598 0374 2598 0764 2605 0374 2651 037A 2693 0392 2693 0750 2704 0392 2731 0393 2731 0768 2738 0393 2914 03C0 2978 03D3 2978 076C 2985 03D3 2992 03D6 2992 0740 2999 03D6 208 0462 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 122 PPU3/REV 25 microcode | cross-reference table 208 0744 215 0462 217 0462 217 0748 224 0462 226 0462 226 074C 233 0462 235 0462 235 0730 242 0462 272 0472 272 0720 291 0472 293 0472 293 0710 312 0472 314 0472 314 0700 333 0472 1270 0636 1270 06F0 1289 0636 1399 067E 1399 0734 1406 067E BLOCKORG 06E0 366 0000 973 00B9 973 00B9 973 00B9 1124 00FD 1124 07D0 1124 07D0 1228 011B 1228 07C0 1228 07C0 1275 0129 1275 0129 1275 0129 1305 0131 1305 07A0 1305 07A0 1560 0190 1560 0190 1560 0190 1951 0234 1951 0780 1951 0780 2042 0260 2042 0770 2042 0770 2289 02CE 2289 02CE 2289 02CE 2693 0392 2693 0392 2693 0392 2992 03D6 2992 03D6 2992 03D6 235 0462 235 0462 235 0462 272 0472 272 0720 272 0720 293 0472 293 0710 293 0710 314 0472 314 0700 314 0700 1270 0636 1270 06F0 1270 06F0 3056 06AE 3059 06AE BPE 4000 707 0000 730 0000 2444 030A 2447 030C BSE 2000 744 0000 2545 034E BSERTN 0692 1433 0692 24 0008 25 0009 26 000A 27 000B BSRST 0697 1438 0697 1351 0667 BTWREC 8000 798 0000 839 0000 840 0000 841 0000 844 0000 846 0000 1077 00E7 1316 07A9 1349 013E 1353 0141 2048 0774 2121 027D BTWRECOE 7FFB 840 0000 1313 07A6 BUSACTIV F5FF 715 0000 1068 00E1 BUSBITS 00A0 813 0588 818 058A 819 058B 825 058E 827 0590 828 0591 831 0593 861 05A4 890 05B7 1215 0609 1295 0638 1299 063C 1303 0640 1307 0644 1310 0647 1311 0648 1312 0649 1313 064A 1314 064B 1315 064C 1316 064D 1317 064E 1319 064F 1320 0650 1321 0651 1322 0652 1323 0653 1324 0654 1325 0655 1326 0656 1327 0657 1328 0658 1329 0659 1330 065A 1364 066B 1370 0671 BUSBLOCK 06F0 1272 06F0 1218 060C BUSFREE F5BF 714 0000 1826 01F1 1829 01E1 1851 01FB BUSTO 000C 530 0000 1073 00E4 1076 00E6 BUSTO2 007D 531 0000 1563 0791 1564 0792 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 BUSY 0108 1186 0108 1134 07D8 CBIT 0200 808 0000 1923 0205 2016 0249 CBN 0400 709 0000 CBNERR 07F3 3090 07F3 2384 0028 2385 0029 2386 002A 2387 002B 2388 002C 2389 002D 2390 002E 2391 002F CBNIADR 0030 692 0000 952 00AA CBNIM 0010 660 0000 666 0000 1794 01EC 2412 02F7 2414 02F9 2483 0323 CBNINT 0020 2376 0020 952 00AA CBNINT1 02F6 2411 02F6 2376 0020 2377 0021 2378 0022 2379 0023 2380 0024 2381 0025 2382 0026 2383 0027 CBNTO 007D 529 0000 2416 02FB CBRTN 068D 1427 068D 20 0004 21 0005 22 0006 23 0007 28 000C 29 000D 30 000E 31 000F CBXFER 065C 1340 065C 1311 0648 1313 064A 1315 064C 1317 064E 1324 0654 1326 0656 1328 0658 1330 065A CFSLOOP 0590 827 0590 821 058D CHKBC 00C5 1083 00C5 1080 00E9 CICKDWT 02D3 2432 02D3 2430 0303 CICKPOL 030E 2451 030E 2448 030D CICKTO 02CB 2418 02CB 2423 02FE CICKUS 0313 2458 0313 2456 0312 CIEXIT 0322 2482 0322 2445 030B 2453 0310 2483 0323 CIEXIT1 0324 2485 0324 2482 0322 CIINPERR 07F4 3091 07F4 2478 0320 CIISUS 0314 2460 0314 2458 0313 CINOTBPE 031E 2475 031E 2444 030A 2447 030C CINOTCOM 030C 2447 030C 2441 0309 CINOTDAT 030A 2444 030A 2439 0308 CINOTDWT 0304 2434 0304 2432 02D3 CINOTIBF 02FE 2423 02FE 2416 02FB 2421 02FD 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 123 PPU3/REV 25 microcode | cross-reference table CINOTPOL 0310 2453 0310 2451 030E CINOTTO 02FD 2421 02FD 2418 02CB CIOURPOL 0318 2466 0318 2460 0314 CIPROCSW 0309 2441 0309 2434 0304 CIRESERR 07F2 3089 07F2 2420 02FC CK1STBYT 07C0 1230 07C0 1226 011A CKACKNAK 00FD 1293 00FD 1290 012B CKBCACTV 00E9 1080 00E9 1077 00E7 CKBCINT 01C7 1727 01C7 1044 00DC CKBSE 034D 2543 034D 2531 0346 2539 034C CKBUSACT 00E0 1067 00E0 1048 00DF CKBUSTO 00EC 1089 00EC 1079 00E8 1085 00EA CKCREAD 0149 1370 0149 1187 0109 CKDIR 02E5 2349 02E5 2347 02E4 CKFIFOBZ 016F 1471 016F 1022 00CE CKFORDPE 00D9 1039 00D9 1032 00D5 CKFORPFW 00F3 1101 00F3 1098 00F2 CKFULL 0163 1477 0163 1474 0171 CKGOING 017C 1506 017C 1499 0178 CKIFINT 0297 2189 0297 2176 0296 CKINPTO 0167 1447 0167 1424 015E CKINT 01D9 1733 01D9 1730 01D7 CKINTUS 023D 1990 023D 1987 023F CKLEGAL 01E0 1753 01E0 1047 00DE CKPORTE1 01CD 1678 01CD 1676 01CC CKPORTE2 01CB 1675 01CB CKPORTPE 01CA 1674 01CA CKRESP 07A0 1307 07A0 1303 0130 CKRUNING 0177 1497 0177 1025 00D0 CKTIMER 00ED 1217 00ED 1215 0113 CKTIMOUT 015F 1437 015F 1019 00CC CKWAIT 012D 1296 012D 1293 00FD 1303 0130 1410 0154 CKWASNAK 0137 1408 0137 1406 0153 CKWRUIS0 0204 1870 0204 1868 0203 CLKDIRT 00D6 1034 00D6 1031 00D4 CLKFIX 001C 430 001C 995 00C3 1028 00D2 1037 00D8 2167 028E 2274 02C2 2325 02E0 2678 038E 2817 03A7 CLKLFX 00D5 1032 00D5 1037 00D8 CLKQFX 00D8 1037 00D8 1034 00D6 1035 00D7 CLRFLAGS FC00 607 0000 1288 0129 1410 0154 CLRWAIT F3FF 608 0000 1366 0148 CM FFFF 493 0000 608 0000 609 0000 634 0000 666 0000 714 0000 715 0000 838 0000 840 0000 843 0000 844 0000 845 0000 1016 00CB 1020 00CD 1023 00CF 1039 00D9 1298 012E 1316 07A9 1355 0142 1471 016F 1473 0170 1480 0173 1576 0191 1591 019A 1615 01A8 1626 01AF 1653 01BE 1685 01D2 1794 01EC 2121 027D CNTDOWN 0024 433 0024 1219 0114 1439 0161 1936 022C 2029 0258 COCKPIT 0400 793 0000 835 0000 845 0000 COMMCOMM 2020 732 0000 2434 0304 COMMDATA 2010 733 0000 2435 0305 CONFIG 0588 816 0588 787 057D CONFUSED 0402 835 0000 1337 0138 1340 013A 1346 013C 2105 0274 2114 027A 2120 027C 2231 02AC 2237 02B0 CONGODIE 02F5 2399 02F5 1699 0014 1700 0015 1701 0016 1702 0017 1858 01FF 2384 0028 2385 0029 2386 002A 2387 002B 2388 002C 2389 002D 2390 002E 2391 002F 2628 0038 2629 0039 2630 003A 2631 003B 2632 003C 2633 003D 2634 003E 2635 003F 2716 0048 2717 0049 2718 004A 2719 004B 2720 004C 2721 004D 2722 004E 2723 004F 2772 0058 2773 0059 2774 005A 2775 005B 2776 005C 2777 005D 2778 005E 2779 005F 2866 0064 2867 0065 2868 0066 2869 0067 2899 0074 2900 0075 2901 0076 2902 0077 2937 0084 2938 0085 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 124 PPU3/REV 25 microcode | cross-reference table 2939 0086 2940 0087 CONTRESET2 05D8 1115 05D8 1111 05D6 1121 05DC COPYTOME 009B 754 0000 2525 0343 CORBC 004C 445 004C 1982 023C 2164 028B 2171 0291 2264 02BC 2308 02D1 CORRBC 023A 1979 023A 1974 0236 CORRBC2 023B 1981 023B 1976 0238 CORRBC3 023C 1982 023C 1979 023A CRDSTART 809D 583 0000 1420 015B 1935 022B CRDTAB 07E4 1392 07E4 1376 014D CRDTEST 8000 582 0000 583 0000 1370 0149 1414 0157 CRIOR 0004 1390 07E4 1373 014B CSFREE F4FF 609 0000 1929 0227 2022 0253 CSIBYTE 07B0 1277 07B0 1273 0128 CSINPRDY 0112 1214 0112 1160 0101 CTLRINT 0808 836 0000 1735 01DA CTLRINTE 0800 794 0000 836 0000 838 0000 842 0000 CTLRINTR 0008 786 0000 836 0000 843 0000 1312 07A5 CTLRRD 0062 571 0000 583 0000 1417 0159 1932 0229 CTLRWR 0096 572 0000 584 0000 1416 0158 2025 0255 CTMCKTO 030F 2529 030F 2534 0348 CTMNIBF 0348 2534 0348 2527 0345 2532 0347 CTMNOTTO 0347 2532 0347 2529 030F CTMTO 007D 538 0000 2527 0345 CUBCNEQ 01C0 1657 01C0 1655 01BF CUBCNLAS 01C3 1661 01C3 1658 01C1 CUCKBCEQ 01BF 1655 01BF 1653 01BE CUCKDONE 0183 1531 0183 1503 017B CUCKEXT 01C5 1666 01C5 1533 0184 CUCKEXT1 01C6 1668 01C6 1666 01C5 CUCKMT 017D 1537 017D 1534 0185 CUEXIT 01C9 1671 01C9 1539 0186 1660 01C2 1661 01C3 1664 01C4 CUEXTRA 01C8 1670 01C8 1668 01C6 CUNDONE 0185 1534 0185 1520 0182 1531 0183 CUNOTMT 0187 1540 0187 1537 017D CUNOTMT3 01B8 1641 01B8 1587 0198 1610 01A6 1638 01B7 CUNOTMTA 018B 1545 018B 1544 018A CUSETINT 01C4 1664 01C4 1657 01C0 CWIOR 0008 1378 07B8 1372 014A CWRSTART 0069 584 0000 1419 015A 2028 0257 CWRTAB 07B8 1380 07B8 1375 014C DATA0 0637 1294 0637 1272 06F0 DATA0A 0638 1295 0638 1297 063A DATA1 063B 1298 063B 1273 06F1 DATA1A 063C 1299 063C 1301 063E DATA2 063F 1302 063F 1274 06F2 DATA2A 0640 1303 0640 1305 0642 DATA3 0643 1306 0643 1275 06F3 DATA3A 0644 1307 0644 1309 0646 DATA4 0647 1310 0647 1276 06F4 DATA4A 0648 1311 0648 1276 06F4 DATA5 0649 1312 0649 1277 06F5 DATA5A 064A 1313 064A 1277 06F5 DATA6 064B 1314 064B 1278 06F6 DATA6A 064C 1315 064C 1278 06F6 DATA7 064D 1316 064D 1279 06F7 DATA7A 064E 1317 064E 1279 06F7 DATA8 064F 1319 064F 1280 06F8 DATA9 0650 1320 0650 1281 06F9 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 125 PPU3/REV 25 microcode | cross-reference table DATAA 0651 1321 0651 1282 06FA DATAB 0652 1322 0652 1283 06FB DATAC 0653 1323 0653 1284 06FC DATACA 0654 1324 0654 1284 06FC DATAD 0655 1325 0655 1285 06FD DATADA 0656 1326 0656 1285 06FD DATADATA 1010 734 0000 DATAE 0657 1327 0657 1286 06FE DATAEA 0658 1328 0658 1286 06FE DATAF 0659 1329 0659 1287 06FF DATAFA 065A 1330 065A 1287 06FF DB0BLOCK 0720 274 0720 253 0464 DB0LOOP 0464 253 0464 258 0468 DB0TEST 0463 252 0463 206 0461 DB4BLOCK 0710 295 0710 261 046A DB4LOOP 046A 261 046A 268 0470 DECIBF 01EA 1792 01EA 1783 01E9 1939 022F 2021 0252 2033 025C 2052 0778 2074 0266 2087 0271 2090 0273 2105 0274 2121 027D 2191 0298 2192 0299 2268 02BE 2298 02CE 2312 02D4 2330 02E2 2331 02E3 2358 02EB 2364 02EF DIDNTPOP 07F0 3087 07F0 975 07E0 976 07E1 977 07E2 978 07E3 1204 0110 1298 012E 1299 012F 1329 0133 1333 0136 1337 0138 1340 013A 1341 013B 1346 013C 1357 0143 1361 0144 1366 0148 1422 015D 1443 0164 1449 0168 1458 016E 1479 0172 1485 0176 1502 017A 1508 017E 1685 01D2 1716 01D5 1738 01DC 1743 01DF 1796 01EE 1832 01F3 1839 01F6 1907 021B 1931 0228 2024 0254 2085 0270 2200 029C 2206 02A0 2209 02A2 2212 02A4 2214 02A6 2216 02A8 2218 02AA 2351 02E6 2352 02E7 2471 031D 2485 0324 2589 0373 2600 0764 2601 0765 2602 0766 2603 0767 2624 0034 2625 0035 2626 0036 2627 0037 2648 0378 2658 037F 2661 0381 2683 0391 2695 0750 2696 0751 2697 0752 2698 0753 2699 0754 2700 0755 2701 0756 2702 0757 2712 0044 2713 0045 2714 0046 2715 0047 2747 0396 2768 0054 2769 0055 2770 0056 2771 0057 2789 039A 2828 03B0 2846 03BB 2883 03BF 2921 03C5 3003 03D7 DIRINP 0000 644 0000 963 00B0 1675 01CB 2079 026A DIRISIN 0280 2137 0280 2135 027E DIRISIN2 02B2 2243 02B2 2241 029F DIRISRD 02E6 2351 02E6 2349 02E5 DIROUT 0001 645 0000 DISAINT 0669 1362 0669 1310 0647 1312 0649 1314 064B 1316 064D 1323 0653 1325 0655 1327 0657 1329 0659 DMADIR 0001 783 0000 842 0000 1031 00D4 1338 0139 1347 013D 2135 027E 2198 027F 2241 029F 2349 02E5 DMANBZ 0080 790 0000 831 0000 832 0000 833 0000 839 0000 841 0000 844 0000 846 0000 1350 013F 1471 016F 1497 0177 2191 0298 2330 02E2 2658 037F DMAOE 0004 785 0000 840 0000 844 0000 845 0000 1355 0142 1483 0174 DO1FCK 027F 2198 027F 2196 029B DO1FETCH 029A 2195 029A 2192 0299 DO1FEXIT 029C 2200 029C 2198 027F DO1FLOOP 029E 2204 029E 2201 029D 2217 02A9 DO1FNEND 02A1 2207 02A1 2204 029E DOINGINP 0100 595 0000 607 0000 609 0000 611 0000 DOINGOUT 0200 596 0000 607 0000 609 0000 615 0000 DOPEXIT 010E 1201 010E 1159 0100 1164 0102 1169 0104 1174 0106 1186 0108 1191 010A 1196 010C DOPEXIT1 010F 1202 010F 1138 07DC 1139 07DD 1154 00FE DOPORT 00F9 1119 00F9 1015 00CA 1206 0111 1253 011F 1262 0123 1278 07B1 1279 07B2 1280 07B3 1281 07B4 1387 07BF 1395 07E7 1401 0150 DOPORT1 00FA 1120 00FA 1201 010E DOPORTAB 07D0 1126 07D0 1122 00FC DOTEST 0400 46 0400 3012 03D8 DOWRU 020B 1880 020B 1872 0206 1875 0208 DOWRU1 0211 1896 0211 1878 020A 1889 07E8 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 126 PPU3/REV 25 microcode | cross-reference table DOWRU2 0212 1897 0212 1890 07E9 DOWRU3 0213 1898 0213 1891 07EA DOWRU4 0214 1899 0214 1892 07EB DPPE 2000 796 0000 844 0000 845 0000 1041 00DA 1680 01CE DWRFI2 059B 847 059B 838 0595 855 05A3 DWRFR 05A4 861 05A4 850 059E DWRFR2 05AB 871 05AB 866 05A9 877 05B1 DWTIN 0080 712 0000 2432 02D3 DWTOUT 0002 748 0000 754 0000 773 0000 DWXFER 05B3 886 05B3 842 0599 855 05A3 866 05A9 878 05B2 ENAINT 066A 1363 066A 1295 0638 1299 063C 1303 0640 1307 0644 1319 064F 1320 0650 1321 0651 1322 0652 ENDINP 0129 1288 0129 1175 0107 ENDOUT 0151 1404 0151 1192 010B ENDTEST 03D9 3019 03D9 1203 0607 ENDWRITE 8082 841 0000 1352 0140 EOR 0090 568 0000 EOR1M1 0191 1576 0191 1574 0190 EOR1M2 0192 1578 0192 1576 0191 EOR1M3 0193 1579 0193 1584 0196 EOR1M4 0195 1582 0195 1579 0193 1593 019C 1617 01AA EOR1M5 0196 1584 0196 1582 0195 EOR1MORE 0190 1574 0190 1563 0791 EOR2M1 019A 1591 019A 1589 0199 EOR2M2 019D 1594 019D 1591 019A EOR2M3 01A1 1602 01A1 1607 01A4 EOR2M4 01A3 1605 01A3 1602 01A1 1625 01AE EOR2M5 01A4 1607 01A4 1605 01A3 EOR2M7 019B 1599 019B 1597 019F EOR2M8 01A0 1601 01A0 1599 019B EOR2MORE 0199 1589 0199 1564 0792 EOR3M1 01A8 1615 01A8 1613 01A7 EOR3M2 01AB 1618 01AB 1615 01A8 EOR3M3 01B0 1628 01B0 1626 01AF EOR3M4 01B3 1632 01B3 1629 01B1 EOR3M5 01B4 1634 01B4 1632 01B3 EOR3M6 01B1 1629 01B1 1634 01B4 EOR3M7 01A9 1623 01A9 1621 01AD EOR3M8 01AF 1626 01AF 1623 01A9 EOR3MORE 01A7 1613 01A7 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 EORBLOCK 0790 1562 0790 1549 018F EORIBF 0010 1695 0010 1547 018D EORIBF1 01D3 1714 01D3 1696 0011 EORINTR 0082 833 0000 1539 0186 1664 01C4 EORIOR 0000 1560 0790 1548 018E EORNPE 01CF 1681 01CF 1678 01CD EORTIMER 0018 428 0018 1563 0791 1564 0792 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 1579 0193 1593 019C 1602 01A1 1617 01AA 1625 01AE 1629 01B1 ERRFLAG 00AC 814 0588 3052 06AE 58 040C 59 040D 61 040F 1203 0607 ERRTN 0606 1202 0606 60 040E 73 0412 75 0414 78 0417 79 0418 81 041A 83 041C 86 041F 87 0420 103 0428 105 042A 107 042C 109 042E 111 0430 132 0438 142 043E 152 0444 162 044A 173 044E 183 0454 193 045A 203 0460 255 0466 263 046C 353 0476 372 0483 401 0488 410 0490 419 0498 428 04A0 459 04B6 464 04BA 469 04BE 474 04C2 479 04C6 484 04CA 489 04CE 494 04D2 499 04D6 504 04DA 509 04DE 514 04E2 519 04E6 524 04EA 529 04EE 534 04F2 594 0510 596 0512 598 0514 600 0516 602 0518 604 051A 606 051C 608 051E 610 0520 612 0522 614 0524 616 0526 618 0528 620 052A 622 052C 624 052E 646 0535 647 0536 651 053A 674 0541 675 0542 677 0544 709 054D 730 055B 748 0564 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 127 PPU3/REV 25 microcode | cross-reference table 759 0568 781 0577 782 0578 795 0585 848 059C 872 05AC 1109 05D4 1118 05DA 1152 05F0 1161 05F6 1174 05FE 1190 0602 1194 0605 EXSTAT 0080 812 0588 837 0594 903 05C3 1249 0626 1252 0629 1256 062D 1257 062E EXTRA 4000 797 0000 844 0000 845 0000 1578 0192 1601 01A0 1628 01B0 1670 01C8 FICKBC 038F 2680 038F 2678 038E FICKEND 0321 2646 0321 2644 0377 FICKLAST 037A 2652 037A 2649 0379 FIEND 037D 2655 037D 2682 0390 FIEXIT 0378 2648 0378 2646 0321 FIFONBZ 0170 1473 0170 1471 016F FIISBIG 0391 2683 0391 2680 038F FINEXTBC 0383 2666 0383 2654 037C FINOTEND 037C 2654 037C 2652 037A FINPERR 07F5 3092 07F5 2628 0038 2629 0039 2630 003A 2631 003B 2632 003C 2633 003D 2634 003E 2635 003F FINPINT 0030 2620 0030 2600 0764 2601 0765 2602 0766 2603 0767 FIORUN 0380 2660 0380 2665 0382 2811 03A2 FISETINT 0764 2600 0764 2137 0280 FIWRITE 0374 2641 0374 2620 0030 2621 0031 2622 0032 2623 0033 FLAGMASK 7030 730 0000 2430 0303 FLAGS 0010 425 0010 965 00B2 1016 00CB 1020 00CD 1023 00CF 1121 00FB 1160 0101 1170 0105 1206 0111 1217 00ED 1220 0115 1222 0116 1262 0123 1288 0129 1296 012D 1298 012E 1317 07AA 1341 013B 1357 0143 1366 0148 1387 07BF 1395 07E7 1410 0154 1411 0155 1413 0156 1421 015C 1422 015D 1424 015E 1444 0165 1446 0166 1473 0170 1480 0173 1685 01D2 1926 0225 1929 0227 1934 022A 1999 0245 2019 0251 2022 0253 2027 0256 2074 0266 2585 0370 FLAGSAB 0000 726 0000 752 0000 FLAGSCOMM 0002 728 0000 732 0000 732 0000 733 0000 754 0000 772 0000 773 0000 FLAGSDATA 0001 727 0000 731 0000 733 0000 734 0000 734 0000 751 0000 752 0000 754 0000 773 0000 FLTEST 05FA 1165 05FA 1157 05F3 FLTEST1 05F4 1159 05F4 1165 05FA FOCKEND 037B 2787 037B 2785 0399 FOCKIF1W 03AF 2826 03AF 2824 03AE FOCKND1W 0395 2745 0395 2741 0394 FOEXIT 039A 2789 039A 2787 037B FOEXIT1W 0396 2747 0396 2745 0395 FOLASTBC 03B7 2842 03B7 2839 03B5 2848 03BC FONEXTBC 03A1 2807 03A1 2803 039E FONLAST 039D 2793 039D 2748 0397 2790 039B FONOT1W 03B0 2828 03B0 2826 03AF FONOVRN 03A3 2812 03A3 2807 03A1 FOODDBC 03B2 2835 03B2 2792 039C FOODDBC1 03BC 2848 03BC 2835 03B2 FOODDWRD 039F 2804 039F 2793 039D FOREAD 0398 2784 0398 2764 0050 2765 0051 2766 0052 2767 0053 FOREAD1W 0392 2729 0392 2708 0040 2709 0041 2710 0042 2711 0043 FOSBCB1W 0393 2740 0393 2733 0768 2734 0769 2735 076A 2736 076B FOSETI1W 0750 2695 0750 2141 0283 FOSETIN1 07EC 2156 07EC 2140 0282 FOSETIN2 0768 2733 0768 2729 0392 FOSI1WIP 0754 2699 0754 2829 03B1 FOUTERR 07F6 3093 07F6 2716 0048 2717 0049 2718 004A 2719 004B 2720 004C 2721 004D 2722 004E 2723 004F 2772 0058 2773 0059 2774 005A 2775 005B 2776 005C 2777 005D 2778 005E 2779 005F FOUTI1W 0040 2708 0040 2291 0760 2292 0761 2293 0762 2294 0763 2695 0750 2696 0751 2697 0752 2698 0753 2699 0754 2700 0755 2701 0756 2702 0757 FOUTINT 0050 2764 0050 2156 07EC 2157 07ED 2158 07EE 2159 07EF 2733 0768 2734 0769 2735 076A 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 128 PPU3/REV 25 microcode | cross-reference table 2736 076B GETBSTAT 00F2 1098 00F2 1070 00E2 1076 00E6 1091 00EE GETFLAGS 036B 2580 036B 2551 0352 2559 0359 2566 035F 2574 0366 GO 0060 567 0000 GOCKRESP 0130 1303 0130 1295 012C GOODBITS 1A01 842 0000 2046 0772 2047 0773 HADDR 005C 450 005C 1543 0189 1641 01B8 1958 0785 2276 02C4 2316 02D7 2357 02EA 2582 036D 2620 0030 2621 0031 2622 0032 2623 0033 2670 0386 2708 0040 2709 0041 2710 0042 2711 0043 2764 0050 2765 0051 2766 0052 2767 0053 2819 03A9 HADDR2 0070 456 0070 1960 0787 2275 02C3 2315 02D6 2363 02EE 2669 0385 2818 03A8 HBLB 0484 397 0484 363 047D HBLB1 0485 398 0485 403 048A HBLB2 048D 407 048D 412 0492 HBLB3 0495 416 0495 421 049A HBLB4 049D 425 049D 430 04A2 HPR 8000 743 0000 772 0000 773 0000 HSW1 0038 439 0038 986 00BC 1249 011B 1327 0131 1955 0782 HSW2 0040 441 0040 988 00BE 1331 0134 1956 0783 HW1 0040 807 0588 839 0596 853 05A1 862 05A5 877 05B1 886 05B3 905 05C5 1140 05EA 1232 0615 1240 061D 1366 066D HW2 0060 809 0588 841 0598 851 059F 864 05A7 875 05AF 888 05B5 911 05CB 1142 05EC 1236 0619 1242 061F 1368 066F HWORD 002C 435 002C 1250 011C 1280 07B3 1281 07B4 1310 07A3 1319 07AC 1362 0145 1381 07B9 1382 07BA 2031 025A IBF 0040 713 0000 714 0000 2421 02FD 2532 0347 IBFCKPE 00BC 481 00BC 2895 0070 2915 03C0 2955 03C6 2961 03C9 IBFIADR 0020 691 0000 947 00A6 1547 018D 1715 01D4 2741 0394 2806 03A0 2835 03B2 2841 03B6 2921 03C5 3003 03D7 IBFIM 0020 659 0000 666 0000 IBIOR 0000 1275 07B0 1272 0127 IBLK0IOR 0004 208 0744 IBLK1IOR 0008 217 0748 IBLK2IOR 000C 226 074C IBLK3IOR 0000 235 0730 ID 0020 806 0588 820 058C 829 0592 915 05CF IDLE 00C9 1014 00C9 1003 00C8 1106 00F6 INCSTATE 014E 1399 014E 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1385 07BD 1386 07BE 1392 07E4 1393 07E5 1394 07E6 INDXBLK0 0744 210 0744 126 0436 167 044B INDXBLK1 0748 219 0748 136 043B 177 0451 INDXBLK2 074C 228 074C 146 0441 187 0457 INDXBLK3 0730 237 0730 156 0447 197 045D INDXTEST 0433 123 0433 112 0431 INDXTSTB 0437 131 0437 126 0436 INDXTSTD 043D 141 043D 136 043B INDXTSTF 0443 151 0443 146 0441 INDXTSTH 0449 161 0449 156 0447 INDXTSTJ 044D 172 044D 167 044B INDXTSTL 0453 182 0453 177 0451 INDXTSTN 0459 192 0459 187 0457 INDXTSTP 045F 202 045F 197 045D INITINTS FFCF 666 0000 945 00A5 INITLOOP 00AF 962 00AF 958 00AE 1000 00C6 INPIOR 0004 2598 0764 INPISLEG 011F 1253 011F 1233 07C3 1236 07C6 1239 07C9 1240 07CA 1242 07CC INPISRDY 0124 1269 0124 1170 0105 INT 0001 757 0000 1743 01DF INTCLR E7FF 838 0000 1998 0244 2469 031B 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 129 PPU3/REV 25 microcode | cross-reference table INTEST 05D2 1107 05D2 874 05AE INTEST1 0608 1214 0608 1154 05F2 1159 05F4 INTEST2 060F 1224 060F 1218 060C INTEST3 062A 1253 062A 1249 0626 INTEST4 062B 1254 062B 1263 0634 INTEST5 0633 1262 0633 1259 0630 INTEST6 0634 1263 0634 1253 062A INTESTA 05E0 1126 05E0 1122 05DD INTISUS 0242 1996 0242 1993 0241 INTLOOP 0673 1375 0673 1370 0671 INTNOTUS 0240 1992 0240 1990 023D INTR 0050 563 0000 INTREQ 011B 1249 011B 1235 07C5 INTRS 0054 564 0000 IRIOR 0008 1762 0798 1756 01E3 ISBSE 034E 2545 034E 2543 034D ISBTWREC 0138 1337 0138 1313 07A6 ISBUSACT 00E3 1071 00E3 1068 00E1 ISCI 0105 1170 0105 1129 07D3 ISDPE 00DA 1041 00DA 1039 00D9 ISEOREAD 013E 1349 013E 1347 013D ISGOING 017E 1508 017E 1506 017C ISPFW 00F4 1103 00F4 1101 00F3 ISRUNING 0178 1499 0178 1497 0177 ISTMNG 00CC 1019 00CC 1016 00CB ISWRITE 0158 1416 0158 1414 0157 LADDR 0060 451 0060 1545 018B 1642 01B9 1646 01BD 1975 0237 2138 0281 2285 02CC 2286 02CD 2318 02D9 2358 02EB 2587 0371 2641 0374 2648 0378 2649 0379 2672 0388 2729 0392 2747 0396 2785 0399 2789 039A 2803 039E 2804 039F 2828 03B0 2829 03B1 2838 03B4 2839 03B5 2975 03D0 2989 03D4 LADDR2 0074 457 0074 1977 0239 2251 02AB 2281 02C9 2282 02CA 2317 02D8 2364 02EF 2671 0387 2824 03AE 2826 03AF LAST 0058 449 0058 1503 017B 1520 0182 1548 018E 1653 01BE 1657 01C0 1658 01C1 1979 023A 2111 0278 2115 027B 2140 0282 2143 0284 2147 0287 2165 028C 2172 0292 2173 0293 2280 02C8 2322 02DD 2652 037A 2676 038C 2748 0397 2790 039B 2792 039C 2793 039D 2823 03AD 2836 03B3 2846 03BB 2848 03BC 2970 03CC LAST2 006C 455 006C 1981 023B 2234 02AE 2238 02B1 2243 02B2 2244 02B3 2257 02B7 2262 02BA 2279 02C7 2306 02CF 2321 02DC 2675 038B 2822 03AC LASTBC 00B2 831 0000 1533 0184 1660 01C2 2842 03B7 LASTBIT 8000 848 0000 1503 017B 1653 01BE 1658 01C1 2050 0776 2106 0275 2108 0276 2109 0277 2232 02AD 2652 037A 2748 0397 2790 039B 2846 03BB LDBC1 0274 2105 0274 2048 0774 LDBC2 02AD 2232 02AD 2050 0776 LDMA1 02E8 2355 02E8 2049 0775 LDMA2 02EC 2361 02EC 2051 0777 LDSTATUS 07AC 1319 07AC 1312 07A5 LEASTBLK 06F0 3059 06AE 3060 06AE LETGO 0174 1483 0174 1473 0170 1480 0173 LEVEL 0019 486 0000 939 00A0 LS1 00C4 565 0000 LS2 0034 566 0000 LSW1 003C 440 003C 987 00BD 1251 011D 1329 0133 1972 0234 LSW2 0044 442 0044 989 00BF 1333 0136 1973 0235 LW1 0044 808 0588 840 0597 852 05A0 863 05A6 876 05B0 887 05B4 907 05C7 1141 05EB 1234 0617 1241 061E 1367 066E LW2 0070 810 0588 842 0599 849 059D 854 05A2 865 05A8 873 05AD 878 05B2 889 05B6 913 05CD 1143 05ED 1238 061B 1243 0620 1369 0670 LWORD 0030 436 0030 1252 011E 1278 07B1 1279 07B2 1328 0132 1332 0135 1364 0146 1383 07BB 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 130 PPU3/REV 25 microcode | cross-reference table 1384 07BC 2033 025C MAXPCHIGH 06AD 3054 06AE 3056 06AE 3060 06AE MAXPCLOW 03EB 3044 03EC 3046 03EC 3060 06AE MEM1ERR 07F7 3094 07F7 2864 0062 2865 0063 2866 0064 2867 0065 2868 0066 2869 0067 2870 0068 2871 0069 2872 006A 2873 006B 2874 006C 2875 006D 2876 006E 2877 006F MEM2ERR 07F8 3095 07F8 2897 0072 2898 0073 2899 0074 2900 0075 2901 0076 2902 0077 2903 0078 2904 0079 2905 007A 2906 007B 2907 007C 2908 007D 2909 007E 2910 007F 2935 0082 2936 0083 2937 0084 2938 0085 2939 0086 2940 0087 2941 0088 2942 0089 2943 008A 2944 008B 2945 008C 2946 008D 2947 008E 2948 008F MEM3ERR 07FD 3100 07FD 1697 0012 1698 0013 1699 0014 1700 0015 1701 0016 1702 0017 1703 0018 1704 0019 1705 001A 1706 001B 1707 001C 1708 001D 1709 001E 1710 001F MEMORY 03C6 1082 00EA 1083 00C6 1216 0114 1217 00EE 1292 012C 1293 00FE 1407 0154 1408 0138 1476 0172 1477 0164 1536 0186 1537 017E 1598 01A0 1599 019C 1622 01AE 1623 01AA 1726 01D6 1727 01C8 1828 01F2 1829 01E2 1922 0224 1923 0206 1989 0240 1990 023E 2015 0250 2016 024A 2065 0262 2066 025E 2197 029C 2198 0280 2240 02B2 2241 02A0 2250 02B4 2251 02AC 2417 02FC 2418 02CC 2431 0304 2432 02D4 2528 0346 2529 0310 2645 0378 2646 0322 2786 039A 2787 037C 2952 03C6 2953 03C2 MPECODE 0100 791 0000 844 0000 845 0000 1695 0010 2862 0060 2917 03C2 2956 03C7 2963 03CA NAK 00F8 561 0000 1257 0120 NEWISCI 0101 1160 0101 1127 07D1 NEWNOTCI 00FE 1154 00FE 1126 07D0 NEWTRANS 00E6 1076 00E6 1074 00E5 1086 00EB NEXTPORT 0000 419 0000 982 00B9 1106 00F6 NOBRANCH 07F1 3088 07F1 1130 07D4 1131 07D5 1132 07D6 1135 07D9 1136 07DA 1137 07DB 1282 07B5 1283 07B6 1284 07B7 1307 07A0 1308 07A1 1309 07A2 1311 07A4 1314 07A7 1315 07A8 1318 07AB 1320 07AD 1321 07AE 1322 07AF 1562 0790 2980 076C 2994 0740 NOBUSTO 00EE 1091 00EE 1073 00E4 1089 00EC NOTBCINT 01D6 1729 01D6 1727 01C7 NOTBTREC 013C 1346 013C 1316 07A9 NOTCI 0102 1164 0102 1128 07D2 NOTCREAD 014A 1372 014A 1370 0149 NOTCTRIN 01DC 1738 01DC 1735 01DA NOTDONE 00C6 1000 00C6 997 00C4 NOTFULL 0172 1479 0172 1477 0163 NOTIMING 00E4 1073 00E4 1071 00E3 NOTIMOUT 0164 1443 0164 1440 0162 NOTINPTO 0168 1449 0168 1447 0167 NOTLEGAL 01E2 1755 01E2 1753 01E0 NOTODD2 02B4 2253 02B4 2251 02AB NOTPPUIN 01DA 1735 01DA 1729 01D6 1733 01D9 NOWAIT 012E 1298 012E 1296 012D NUMPORTS 0004 491 0000 654 0000 958 00AE 984 00BB 997 00C4 1003 00C8 NXTSTATE 0111 1206 0111 1155 00FF 1165 0103 1197 010D ODDWORD 0080 2933 0080 2835 03B2 ODDWORDCKPE 03C9 2961 03C9 2955 03C6 ODDWORDOK 0081 2934 0081 2964 03CB ODDWORDPE 03CA 2963 03CA 2961 03C9 OLDBCNT 00B8 479 00B8 994 00C2 1083 00C5 1086 00EB ONEWORD 0070 2895 0070 2741 0394 2806 03A0 2841 03B6 ONEWORD1 03C4 2920 03C4 2896 0071 ONEWORDCKPE 03C0 2915 03C0 2895 0070 ONEWORDPE 03C2 2917 03C2 2915 03C0 OUT1WIOR 0000 2693 0750 OUTIOR1 000C 2154 07EC OUTIOR2 0008 2731 0768 OVRRUN 0050 834 0000 2661 0381 OW1BCIOR 0000 2992 0740 2970 03CC OW2BCIOR 000C 2978 076C 2976 03D1 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 131 PPU3/REV 25 microcode | cross-reference table OWCKIFONE 03C1 2953 03C1 2933 0080 OWEXIT 03D7 3003 03D7 2981 076D 2982 076E 2987 03D3 2995 0741 2996 0742 3001 03D6 OWIS1BC 0740 2994 0740 2990 03D5 OWIS1BC1 03D6 3001 03D6 2997 0743 OWIS2BC 076C 2980 076C 2977 03D2 OWIS2BC1 03D3 2987 03D3 2983 076F OWISONE 03CC 2970 03CC 2934 0081 OWISONE1 03D4 2989 03D4 2970 03CC OWNOTONE 03CD 2971 03CD 2958 03C8 OWPENOTONE 03C7 2956 03C7 2953 03C1 PBITHIGH 0008 422 0008 970 00B7 971 00B8 2044 0770 2063 0260 2071 0264 PBITIM 000C 423 000C 975 07E0 976 07E1 977 07E2 978 07E3 1509 017F 2081 026C 2192 0299 2195 029A 2210 02A3 2298 02CE 2331 02E3 2655 037D 2665 0382 2811 03A2 2843 03B8 PBITLOW 0004 421 0004 967 00B4 968 00B5 1484 0175 2076 0267 2077 0268 PEGODIE 02F1 2395 02F1 1703 0018 1704 0019 1705 001A 1706 001B 1707 001C 1708 001D 1709 001E 1710 001F 2870 0068 2871 0069 2872 006A 2873 006B 2874 006C 2875 006D 2876 006E 2877 006F 2903 0078 2904 0079 2905 007A 2906 007B 2907 007C 2908 007D 2909 007E 2910 007F 2941 0088 2942 0089 2943 008A 2944 008B 2945 008C 2946 008D 2947 008E 2948 008F PFWCHECK 0096 926 0096 922 0094 924 0095 PFWNOT 8000 706 0000 924 0095 1101 00F3 PFWSTILL 0095 924 0095 926 0096 PFWWAIT 07FF 3102 07FF 1109 00F8 PINTCK 0010 802 0588 1297 063A 1301 063E 1305 0642 1309 0646 1413 0682 PINTRIOR 0004 1399 0734 PINTRTN 0734 1401 0734 17 0001 18 0002 19 0003 PINTSUB 067E 1408 067E 1401 0734 1402 0735 1403 0736 1404 0737 PONCHECK4 0600 1187 0600 1193 0604 PONCHECK5 0604 1193 0604 1183 05FF POP1 0429 104 0429 101 0426 POP2 042B 106 042B 100 0425 POP3 042D 108 042D 99 0424 POP4 042F 110 042F 98 0423 PORT0IM 0001 664 0000 975 07E0 PORT1IM 0002 663 0000 976 07E1 PORT2IM 0004 662 0000 977 07E2 PORT3IM 0008 661 0000 978 07E3 PORTDEAD 4000 601 0000 604 0000 605 0000 1926 0225 2019 0251 PORTHIGH 0010 657 0000 957 00AD PORTLOW 0001 656 0000 956 00AC PPUINT 1002 837 0000 1729 01D6 1733 01D9 PPUINTE 1000 795 0000 837 0000 838 0000 842 0000 PPUINTR 0002 784 0000 831 0000 832 0000 833 0000 835 0000 837 0000 841 0000 843 0000 845 0000 1732 01D8 PPUTYPE 3000 806 0000 938 009F PRT0IADR 0070 696 0000 2156 07EC 2291 0760 2600 0764 2695 0750 2699 0754 2733 0768 PRT1IADR 0060 695 0000 2157 07ED 2292 0761 2601 0765 2696 0751 2700 0755 2734 0769 PRT2IADR 0050 694 0000 2158 07EE 2293 0762 2602 0766 2697 0752 2701 0756 2735 076A PRT3IADR 0040 693 0000 2159 07EF 2294 0763 2603 0767 2698 0753 2702 0757 2736 076B PRTCI 2000 628 0000 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1140 07DE 1141 07DF PRTEMPTY FCFF 634 0000 1537 017D 1599 019B 1623 01A9 1668 01C6 PRTFREE 1000 629 0000 1133 07D7 1134 07D8 PRTHIGH 0200 632 0000 634 0000 PRTINIT 8080 839 0000 966 00B3 PRTINT 0800 630 0000 1477 0163 1506 017C PRTLOW 0100 633 0000 634 0000 1576 0191 1591 019A 1615 01A8 1626 01AF PRTNUMMASK 0003 654 0000 1736 01DB 1739 01DD 1913 021F 1916 0221 1987 023F 2006 0248 2013 024E PRTPE 0400 631 0000 1039 00D9 1678 01CD 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 132 PPU3/REV 25 microcode | cross-reference table PRTPON 4000 627 0000 PRTST 0014 426 0014 966 00B3 1031 00D4 1041 00DA 1077 00E7 1312 07A5 1313 07A6 1316 07A9 1337 0138 1338 0139 1340 013A 1346 013C 1347 013D 1349 013E 1350 013F 1352 0140 1353 0141 1355 0142 1471 016F 1483 0174 1497 0177 1500 0179 1533 0184 1539 0186 1578 0192 1601 01A0 1628 01B0 1660 01C2 1661 01C3 1664 01C4 1670 01C8 1680 01CE 1695 0010 1727 01C7 1729 01D6 1730 01D7 1732 01D8 1733 01D9 1735 01DA 1986 023E 1992 0240 1993 0241 1998 0244 2000 0246 2045 0771 2048 0774 2073 0265 2087 0271 2089 0272 2090 0273 2105 0274 2114 027A 2120 027C 2121 027D 2135 027E 2168 028F 2175 0295 2191 0298 2198 027F 2204 029E 2231 02AC 2237 02B0 2241 029F 2265 02BD 2269 02BF 2309 02D2 2313 02D5 2330 02E2 2349 02E5 2467 0319 2469 031B 2588 0372 2658 037F 2661 0381 2666 0383 2812 03A3 2842 03B7 2862 0060 2917 03C2 2956 03C7 2963 03CA PTFULL 001C 805 0588 1128 05E1 1244 0621 1246 0623 1248 0625 1250 0627 1294 0637 1298 063B 1302 063F 1306 0643 1411 0680 PUSHPOPTEST 0423 98 0423 88 0421 RCKWNPRT 0221 1916 0221 1914 0220 RDBCNT 0236 1974 0236 1957 0784 RDBCNT2 0238 1976 0238 1959 0786 RDCKWHO1 0205 1923 0205 1918 0222 RDISUS 0224 1925 0224 1923 0205 RDMA1 0237 1975 0237 1958 0785 RDMA2 0239 1977 0239 1960 0787 RDMODEDW 0247 2002 0247 1961 0788 RDNOTLEG 0232 1947 0232 1925 0224 RDSTEXIT 0245 1999 0245 1986 023E 1992 0240 RDSTS 023F 1987 023F 1954 0781 RDSW1 0234 1972 0234 1955 0782 RDSW2 0235 1973 0235 1956 0783 RDTAB 0780 1953 0780 1948 0233 READ1W 2000 768 0000 775 0000 1543 0189 READ2W 3000 769 0000 772 0000 775 0000 READB2B 02D4 2312 02D4 2309 02D2 READBC 0291 2171 0291 2137 0280 READBC2 02CF 2306 02CF 2243 02B2 READBITS B02D 772 0000 1542 0188 2352 02E7 RECVRESP 00F0 617 0000 1387 07BF 1395 07E7 REMEMBER 067E 973 00B9 980 07E4 1124 00FD 1143 07E0 1228 011B 1247 07D0 1275 0129 1286 07B8 1305 0131 1324 07B0 1378 014E 1390 07C0 1390 014E 1397 07E8 1560 0190 1571 0798 1693 01D3 1712 0020 1762 01E6 1773 07A0 1887 0211 1894 07EC 1951 0234 1970 0790 2042 0260 2061 0780 2154 028A 2161 07F0 2289 02CE 2296 0764 2374 02F1 2393 0030 2598 0374 2605 0768 2618 0374 2637 0040 2693 0392 2704 0758 2706 0392 2725 0050 2731 0393 2738 076C 2762 0398 2781 0060 2860 03BD 2879 0070 2893 03C0 2912 0080 2931 03C6 2950 0090 2978 03D3 2985 0770 2992 03D6 2999 0744 208 0462 215 0748 217 0462 224 074C 226 0462 233 0750 235 0462 242 0734 272 0472 291 0730 293 0472 312 0720 314 0472 333 0710 1270 0636 1289 0700 1399 067E 1406 0738 REOR 2000 600 0000 1023 00CF 1357 0143 1685 01D2 REP.LST 0000 980 07E4 1143 07E0 1247 07D0 1286 07B8 1324 07B0 1390 07C0 1397 07E8 1571 0798 1712 0020 1773 07A0 1894 07EC 1970 0790 2061 0780 2161 07F0 2296 0764 2393 0030 2605 0768 2637 0040 2704 0758 2725 0050 2738 076C 2781 0060 2879 0070 2912 0080 2950 0090 2985 0770 2999 0744 215 0748 224 074C 233 0750 242 0734 291 0730 312 0720 333 0710 1289 0700 1406 0738 REP.RPT 0000 980 07E4 980 07E4 1143 07E0 1143 07E0 1247 07D0 1247 07D0 1286 07B8 1286 07B8 1324 07B0 1324 07B0 1390 07C0 1390 07C0 1397 07E8 1397 07E8 1571 0798 1571 0798 1712 0020 1712 0020 1773 07A0 1773 07A0 1894 07EC 1894 07EC 1970 0790 1970 0790 2061 0780 2061 0780 2161 07F0 2161 07F0 2296 0764 2296 0764 2393 0030 2393 0030 2605 0768 2605 0768 2637 0040 2637 0040 2704 0758 2704 0758 2725 0050 2725 0050 2738 076C 2738 076C 2781 0060 2781 0060 2879 0070 2879 0070 2912 0080 2912 0080 2950 0090 2950 0090 2985 0770 2985 0770 2999 0744 2999 0744 215 0748 215 0748 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 133 PPU3/REV 25 microcode | cross-reference table 224 074C 224 074C 233 0750 233 0750 242 0734 242 0734 291 0730 291 0730 312 0720 312 0720 333 0710 333 0710 1289 0700 1289 0700 1406 0738 1406 0738 RESBUSY 0106 1174 0106 1133 07D7 RESCONT 0260 2063 0260 2044 0770 RESCONT1 025D 2066 025D 2064 0261 RESCONT2 0262 2068 0262 2066 025D 2068 0262 RESERR 07FB 3098 07FB 1094 00F0 1581 0194 1604 01A2 1631 01B2 RESET 069A 1457 069A 1107 05D2 1168 05FB RESET1 069E 1461 069E 1457 069A RESET1A 069B 1458 069B 1461 069E RESET2 06A1 1467 06A1 1461 069E RESGODIE 02F4 2398 02F4 1094 00F0 1581 0194 1604 01A2 1631 01B2 2420 02FC RESISCI 010B 1192 010B 1140 07DE RESNOTCI 010C 1196 010C 1141 07DF RESP 00A4 569 0000 RESPEXIT 01E6 1780 01E6 1896 0211 1897 0212 1898 0213 1899 0214 1942 0231 1972 0234 1973 0235 1975 0237 1977 0239 1982 023C 2000 0246 2002 0247 RESPONSE 0144 1361 0144 1317 07AA RESPTO 0034 437 0034 1365 0147 1455 016C 1456 016D 1937 022D RESTART 009E 937 009E 3029 03E0 RESTRDWR 0080 614 0000 615 0000 1422 015D RFIIN 0100 711 0000 RFIOUT 0004 747 0000 2376 0020 2377 0021 2378 0022 2379 0023 2380 0024 2381 0025 2382 0026 2383 0027 RFR2OUT 0004 746 0000 753 0000 772 0000 RFRIN 0200 710 0000 714 0000 715 0000 RFROUT 0008 745 0000 754 0000 772 0000 RGOB 1000 599 0000 1020 00CD 1341 013B 1473 0170 1480 0173 RLSW1 0131 1327 0131 1319 07AC RLSW2 0134 1331 0134 1310 07A3 RNOTDEAD 0227 1929 0227 1926 0225 1953 0780 RNOTFREE 0228 1931 0228 1929 0227 RPTNOTKN 0223 1919 0223 1916 0221 RSCR 050F 593 050F 588 050D RSTSTCK 05FD 1173 05FD 1168 05FB RTODATA 0011 751 0000 1867 0202 1910 021C 2456 0312 RTODELAY 016E 1458 016E 1455 016C 2464 0317 RTOERR 07FA 3097 07FA 1095 00F1 RTOGODIE 02F3 2397 02F3 1095 00F1 RTOIN 0800 708 0000 714 0000 715 0000 1092 00EF RTOOUT 0001 749 0000 751 0000 754 0000 772 0000 773 0000 SACKNAK 0122 1261 0122 1257 0120 1258 0121 SAVEIBF 0325 2494 0325 1109 00F8 2395 02F1 2396 02F2 2397 02F3 2398 02F4 2399 02F5 SCRADDRTST 04A4 440 04A4 431 04A3 SCRTST 04F4 549 04F4 535 04F3 SCRTST1 04F6 555 04F6 549 04F4 SCRTST1A 04F5 554 04F5 555 04F6 SCRTST2 04FC 566 04FC 561 04F7 SCRTST2A 04F8 562 04F8 566 04FC SCSTS 0272 2089 0272 2047 0773 SELFTEST 03D8 3012 03D8 1769 079D SENDLZ 0230 1941 0230 1928 0226 SENDNAK 0120 1257 0120 1230 07C0 1231 07C1 1232 07C2 1234 07C4 1237 07C7 1238 07C8 1241 07CB 1243 07CD 1244 07CE 1245 07CF 1277 07B0 SENDRESP 0070 612 0000 1262 0123 SETDEAD 40C0 604 0000 1424 015E SETIMED C0D0 605 0000 1446 0166 SETIMIOR 0000 973 07E0 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 134 PPU3/REV 25 microcode | cross-reference table SETINT 01DE 1742 01DE 1736 01DB 1739 01DD SETPDEAD 015E 1424 015E 1413 0156 SETPRTIM 07E0 975 07E0 971 00B8 SETREOR 0143 1357 0143 1349 013E SHIFTL2 0219 1905 0219 1880 020B SHIFTL3 0217 1903 0217 SHIFTL4 0215 1901 0215 1872 0206 1875 0208 2524 0342 2581 036C SKIPTEST 0411 72 0411 61 040F SKIPWSTE 0001 3062 06AE 3072 06AE SLOT 0050 447 0050 1540 0187 1645 01BC 1957 0784 2278 02C6 2320 02DB 2355 02E8 2580 036B 2643 0376 2674 038A 2740 0393 2784 0398 2821 03AB SLOT2 0064 453 0064 1959 0786 2277 02C5 2319 02DA 2361 02EC 2673 0389 2820 03AA SOPBTO 0200 549 0000 1070 00E2 1071 00E3 1073 00E4 SOPPFW 0100 548 0000 1103 00F4 1104 00F5 SSSTS 0271 2087 0271 2046 0772 START 0090 918 0090 914 0000 STARTINP 0520 611 0000 1220 0115 1222 0116 STARTRD 0E81 616 0000 1934 022A STARTWR 0681 615 0000 616 0000 2027 0256 STERR 07FE 3101 07FE 210 0744 211 0745 212 0746 213 0747 219 0748 220 0749 221 074A 222 074B 228 074C 229 074D 230 074E 231 074F 237 0730 238 0731 239 0732 240 0733 316 0700 317 0701 318 0702 319 0703 320 0704 321 0705 322 0706 323 0707 324 0708 325 0709 326 070A 327 070B 328 070C 329 070D 330 070E 331 070F 371 0482 625 052F 904 05C4 906 05C6 908 05C8 910 05CA 912 05CC 914 05CE 916 05D0 917 05D1 1225 0610 1233 0616 1235 0618 1237 061A 1239 061C 1245 0622 1251 0628 1258 062F 1261 0632 1264 0635 1349 0665 1350 0666 1376 0674 1384 067C 1385 067D 1414 0683 1422 068B 1431 0691 1440 0699 1459 069C 1462 069F 1478 06AC 1479 06AD STILLBZ 0140 1352 0140 1350 013F STSCLBTS FFE5 843 0000 2000 0246 SXFER 0671 1370 0671 1342 065E TCON 0050 811 0588 1145 05EE 1153 05F1 1154 05F2 1157 05F3 1162 05F7 1164 05F9 1165 05FA TEMP 00B0 476 00B0 1067 00E0 1074 00E5 1091 00EE 1223 0117 1224 0118 1290 012B 1293 00FD 1406 0153 1408 0137 1437 015F 1438 0160 1585 0197 1594 019D 1608 01A5 1610 01A6 1618 01AB 1635 01B5 1638 01B7 1655 01BF 1736 01DB 1739 01DD 1742 01DE 1867 0202 1868 0203 1872 0206 1875 0208 1880 020B 1901 0215 1902 0216 1903 0217 1904 0218 1905 0219 1906 021A 1907 021B 1910 021C 1911 021D 1987 023F 1990 023D 2049 0775 2051 0777 2347 02E4 2356 02E9 2362 02ED 2524 0342 2581 036C 2583 036E 2584 036F TEMP2 00B4 477 00B4 1831 01F2 1836 01F5 1840 01F7 1846 01F8 1848 01FA 1853 01FC TESTCARY 0531 642 0531 567 04FD TESTCARY0 0546 702 0546 678 0545 TESTCARY1 0548 704 0548 716 0552 TESTCARY2 0553 722 0553 713 0550 TESTCARY3 0555 724 0555 736 0560 TESTCARY5 0561 745 0561 734 055E TESTDIR 027E 2135 027E 2111 0278 2115 027B TESTDIR2 029F 2241 029F 2234 02AE 2238 02B1 TESTODD2 02AB 2251 02AB 2244 02B3 TIMBYRD 0018 524 0000 1034 00D6 TIMBYTC 0200 523 0000 1037 00D8 TIMBYWR 000C 525 0000 1035 00D7 TIMECNST 053C 516 0000 1219 0114 1936 022C 2029 0258 TIMECSIN 0004 518 0000 1225 0119 TIMEDOUT 8000 602 0000 605 0000 TIMEROFF 0114 1219 0114 1217 00ED TIMERSPX 0001 519 0000 1783 01E9 TIMERW 0003 520 0000 1938 022E TIMEWW 0006 521 0000 2032 025B 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 135 PPU3/REV 25 microcode | cross-reference table TIMIDLE 0001 517 0000 1014 00C9 TIMING 0400 597 0000 608 0000 611 0000 615 0000 1016 00CB 1217 00ED 1298 012E TWOWORDS 0060 2862 0060 947 00A6 1715 01D4 2921 03C5 3003 03D7 TWOWRDS1 03BD 2881 03BD 2863 0061 TYPECKSM 0020 432 0020 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1253 011F 1257 0120 1258 0121 1261 0122 1270 0125 1271 0126 1272 0127 1277 07B0 1289 012A 1295 012C 1370 0149 1372 014A 1373 014B 1386 07BE 1394 07E6 1400 014F 1401 0150 1414 0157 1419 015A 1420 015B 1935 022B 2028 0257 VECTCK 0014 803 0588 1216 060A 1217 060B 1219 060D 1410 067F 1427 068D 1434 0693 VECTORADD 0080 1693 0010 1712 0020 1712 0020 2374 0020 2393 0030 2393 0030 2618 0030 2637 0040 2637 0040 2706 0040 2725 0050 2725 0050 2762 0050 2781 0060 2781 0060 2860 0060 2879 0070 2879 0070 2893 0070 2912 0080 2912 0080 2931 0080 2950 0090 2950 0090 VECTORON 0000 398 0000 1693 01D3 1693 0010 1712 01D3 2374 02F1 2374 0020 2393 02F1 2618 0374 2618 0030 2637 0374 2706 0392 2706 0040 2725 0392 2762 0398 2762 0050 2781 0398 2860 03BD 2860 0060 2879 03BD 2893 03C0 2893 0070 2912 03C0 2931 03C6 2931 0080 2950 03C6 VECTORORG 0090 397 0000 1693 01D3 1693 0010 1693 0010 2374 02F1 2374 0020 2374 0020 2618 0374 2618 0030 2618 0030 2706 0392 2706 0040 2706 0040 2762 0398 2762 0050 2762 0050 2860 03BD 2860 0060 2860 0060 2893 03C0 2893 0070 2893 0070 2931 03C6 2931 0080 2931 0080 WAITING 0800 598 0000 608 0000 609 0000 616 0000 1296 012D 1317 07AA 1447 0167 WASNAK 0155 1411 0155 1408 0137 WB2INTSON 02CE 2298 02CE 2285 02CC 2291 0760 2292 0761 2293 0762 2294 0763 WB2NOT1W 02CC 2285 02CC 2282 02CA WB2O1WIOR 0000 2289 0760 WB2O1WIP 0760 2291 0760 2286 02CD WDCNT 0018 804 0588 1124 05DE 1260 0631 1422 068B WFB2AV 01FC 1853 01FC 1851 01FB WFBAV 01F2 1831 01F2 1829 01E1 WFBCKFRE 01E1 1829 01E1 1835 01F4 WFBERR 07FC 3099 07FC 1858 01FF WFBGSTAT 01F4 1835 01F4 1831 01F2 1840 01F7 WFBNAVAL 01F7 1840 01F7 1826 01F1 WFBOUTS 01F6 1839 01F6 1854 01FD WFBSTG2 01F8 1846 01F8 1836 01F5 WFBSTG2Q 01FB 1851 01FB 1857 01FE WFBSTG2Y 01FE 1857 01FE 1848 01FA 1853 01FC WFBTO 0064 534 0000 1840 01F7 WFBTO2 04E2 535 0000 1848 01FA WNOTDEAD 0253 2022 0253 2019 0251 WNOTFREE 0254 2024 0254 2022 0253 WORD1DATA 1000 731 0000 2915 03C0 2961 03C9 WPTNOTKN 024A 2008 024A 2006 0248 WRCKWHO 0249 2016 0249 2014 024F WRDSLEFT 0058 3060 06AE 3069 06AE WRISUS 0250 2018 0250 2016 0249 WRITBITS 8063 773 0000 2351 02E6 WRITE 0000 770 0000 773 0000 WRITEB2A 02BD 2265 02BD 2256 02B6 WRITEB2B 02BE 2268 02BE 2265 02BD WRITEBC 028A 2163 028A 2156 07EC 2157 07ED 2158 07EE 2159 07EF WRITEBC1 028B 2164 028B 2146 0286 2151 0289 WRITEBC2 02BA 2262 02BA 2253 02B4 WRNOTLEG 025E 2038 025E 2018 0250 WRTAB 0770 2044 0770 2039 025F WRTABABT 0771 2045 0771 2071 0264 WRUIOR 0008 1887 07E8 1884 020F WRULEGAL 0200 1864 0200 1768 079C 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 136 PPU3/REV 25 microcode | cross-reference table WRULOOP 03E1 3030 03E1 3040 03EA WRULOOP1 03E4 3034 03E4 3025 03DE WRUNOT0 0206 1872 0206 1870 0204 WRURES1A 0090 467 0090 938 009F 1878 020A 1889 07E8 2535 0349 2560 035A 2575 0367 3039 03E9 WRURES1B 0094 468 0094 939 00A0 1896 0211 2537 034A 2561 035B 2576 0368 3038 03E8 WRURES2A 0098 469 0098 1890 07E9 2503 032D 2505 032F 2507 0331 2538 034B 2562 035C 2577 0369 3037 03E7 WRURES2B 009C 470 009C 1897 0212 2509 0333 2511 0335 2539 034C 2563 035D 2578 036A 3036 03E6 WRURES3A 00A0 471 00A0 1891 07EA 2513 0337 2552 0353 2567 0360 3035 03E5 WRURES3B 00A4 472 00A4 1898 0213 2515 0339 2553 0354 2568 0361 3034 03E4 WRURES4A 00A8 473 00A8 931 009A 1892 07EB 2517 033B 2554 0355 2569 0362 3033 03E3 WRURES4B 00AC 474 00AC 814 0588 3052 06AE 932 009B 1899 0214 2519 033D 2555 0356 2570 0363 3032 03E2 WRUTABLE 07E8 1889 07E8 1885 0210 WSCR 04FE 573 04FE 555 04F6 566 04FC WSTE0000 00C5 998 00C5 1082 00EA WSTE0001 00ED 1089 00ED 1216 0114 WSTE0002 00FD 1152 00FD 1292 012C WSTE0003 0137 1335 0137 1407 0154 WSTE0004 0163 1441 0163 1476 0172 WSTE0005 017D 1506 017D 1536 0186 WSTE0006 019B 1591 019B 1598 01A0 WSTE0007 01A9 1615 01A9 1622 01AE WSTE0008 01C7 1668 01C7 1726 01D6 WSTE0009 01E1 1753 01E1 1828 01F2 WSTE0010 0205 1870 0205 1922 0224 WSTE0011 023D 1984 023D 1989 0240 WSTE0012 0249 2006 0249 2015 0250 WSTE0013 025D 2036 025D 2065 0262 WSTE0014 027F 2135 027F 2197 029C WSTE0015 029F 2204 029F 2240 02B2 WSTE0016 02AB 2229 02AB 2250 02B4 WSTE0017 02CB 2283 02CB 2417 02FC WSTE0018 02D3 2310 02D3 2431 0304 WSTE0019 030F 2451 030F 2528 0346 WSTE0020 0321 2480 0321 2645 0378 WSTE0021 037B 2652 037B 2786 039A WSTE0022 03C1 2915 03C1 2952 03C6 WSTE0023 03DF 3027 03DF WSTECNTR 0018 280 0000 998 00C5 998 00C6 998 00C6 1082 00EA 1088 00EC 1089 00ED 1089 00EE 1089 00EE 1152 00FD 1152 00FE 1152 00FE 1216 0114 1292 012C 1335 0137 1335 0138 1335 0138 1407 0154 1441 0163 1441 0164 1441 0164 1476 0172 1505 017C 1506 017D 1506 017E 1506 017E 1536 0186 1590 019A 1591 019B 1591 019C 1591 019C 1598 01A0 1614 01A8 1615 01A9 1615 01AA 1615 01AA 1622 01AE 1667 01C6 1668 01C7 1668 01C8 1668 01C8 1726 01D6 1752 01E0 1753 01E1 1753 01E2 1753 01E2 1828 01F2 1869 0204 1870 0205 1870 0206 1870 0206 1922 0224 1984 023D 1984 023E 1984 023E 1989 0240 2005 0248 2006 0249 2006 024A 2006 024A 2015 0250 2036 025D 2036 025E 2036 025E 2065 0262 2134 027E 2135 027F 2135 0280 2135 0280 2197 029C 2203 029E 2204 029F 2204 02A0 2204 02A0 2229 02AB 2229 02AC 2229 02AC 2240 02B2 2250 02B4 2283 02CB 2283 02CC 2283 02CC 2310 02D3 2310 02D4 2310 02D4 2417 02FC 2431 0304 2450 030E 2451 030F 2451 0310 2451 0310 2480 0321 2480 0322 2480 0322 2528 0346 2645 0378 2651 037A 2652 037B 2652 037C 2652 037C 2786 039A 2914 03C0 2915 03C1 2915 03C2 2915 03C2 2952 03C6 3027 03DF 3027 03E0 3027 03E0 3062 06AE WSTEPNTR 0017 281 0000 1082 00EA 1082 00EA 1082 00C5 1082 00C5 1088 00EC 1216 0114 1216 0114 1216 00ED 1216 00ED 1292 012C 1292 012C 1292 00FD 1292 00FD 1407 0154 1407 0154 1407 0137 1407 0137 1476 0172 1476 0172 1476 0163 1476 0163 1505 017C 1536 0186 1536 0186 1536 017D 1536 017D 1590 019A 1598 01A0 1598 01A0 1598 019B 1598 019B 1614 01A8 1622 01AE 1622 01AE 1622 01A9 1622 01A9 1667 01C6 1726 01D6 1726 01D6 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 137 PPU3/REV 25 microcode | cross-reference table 1726 01C7 1726 01C7 1752 01E0 1828 01F2 1828 01F2 1828 01E1 1828 01E1 1869 0204 1922 0224 1922 0224 1922 0205 1922 0205 1989 0240 1989 0240 1989 023D 1989 023D 2005 0248 2015 0250 2015 0250 2015 0249 2015 0249 2065 0262 2065 0262 2065 025D 2065 025D 2134 027E 2197 029C 2197 029C 2197 027F 2197 027F 2203 029E 2240 02B2 2240 02B2 2240 029F 2240 029F 2250 02B4 2250 02B4 2250 02AB 2250 02AB 2417 02FC 2417 02FC 2417 02CB 2417 02CB 2431 0304 2431 0304 2431 02D3 2431 02D3 2450 030E 2528 0346 2528 0346 2528 030F 2528 030F 2645 0378 2645 0378 2645 0321 2645 0321 2651 037A 2786 039A 2786 039A 2786 037B 2786 037B 2914 03C0 2952 03C6 2952 03C6 2952 03C1 2952 03C1 3062 06AE WTFORBUS 01EF 1824 01EF 1362 0145 1450 0169 1544 018A 1641 01B8 1780 01E6 WTFORPON 032C 2502 032C 1760 01E5 2478 0320 2500 032B XCHG 0472 349 0472 269 0471 XCHG0 047C 362 047C 356 0478 XCHG0A 047A 360 047A 362 047C XCHGTST 047E 367 047E 362 047C XORCF1W 1000 775 0000 2708 0040 2709 0041 2710 0042 2711 0043 XORFF1W 0004 753 0000 2740 0393 YESRETRY 0157 1414 0157 1411 0155 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 138 PPU3/REV 25 microcode | cross-reference table BLOCK 317 0000 973 00B9 1124 00FD 1228 011B 1275 0129 1305 0131 1378 014E 1390 07C0 1560 0190 1762 01E6 1887 0211 1951 0234 2042 0260 2154 028A 2289 02CE 2598 0374 2693 0392 2731 0393 2978 03D3 2992 03D6 208 0462 217 0462 226 0462 235 0462 272 0472 293 0472 314 0472 1270 0636 1399 067E ENDBLOCK 355 0000 980 07E4 1143 07E0 1247 07D0 1286 07B8 1324 07B0 1390 07C0 1397 07E8 1571 0798 1773 07A0 1894 07EC 1970 0790 2061 0780 2161 07F0 2296 0764 2605 0768 2704 0758 2738 076C 2985 0770 2999 0744 215 0748 224 074C 233 0750 242 0734 291 0730 312 0720 333 0710 1289 0700 1406 0738 ENDVECTOR 386 0000 1712 0020 2393 0030 2637 0040 2725 0050 2781 0060 2879 0070 2912 0080 2950 0090 REP 403 0000 980 07E4 1143 07E0 1247 07D0 1286 07B8 1324 07B0 1390 07C0 1397 07E8 1571 0798 1712 0020 1773 07A0 1894 07EC 1970 0790 2061 0780 2161 07F0 2296 0764 2393 0030 2605 0768 2637 0040 2704 0758 2725 0050 2738 076C 2781 0060 2879 0070 2912 0080 2950 0090 2985 0770 2999 0744 215 0748 224 074C 233 0750 242 0734 291 0730 312 0720 333 0710 1289 0700 1406 0738 SKIPORG 271 0000 998 00C5 1017 00CC 1152 00FD 1255 0120 1335 0137 1344 013C 1359 0144 1441 0163 1862 0200 1945 0232 1984 023D 2036 025D 2103 0274 2118 027C 2229 02AB 2266 02BE 2283 02CB 2310 02D3 2328 02E2 2442 030A 2473 031E 2480 0321 2663 0382 2809 03A2 2833 03B2 2968 03CC 3027 03DF STARTSKP 286 0000 923 0095 1038 00D9 1082 00EA 1088 00EC 1100 00F3 1216 0114 1292 012C 1369 0149 1407 0154 1470 016F 1476 0172 1496 0177 1505 017C 1530 0183 1536 0186 1575 0191 1590 019A 1598 01A0 1614 01A8 1622 01AE 1654 01BF 1667 01C6 1677 01CD 1726 01D6 1752 01E0 1828 01F2 1850 01FB 1869 0204 1915 0221 1922 0224 1989 0240 2005 0248 2015 0250 2065 0262 2134 027E 2188 0297 2197 029C 2203 029E 2240 02B2 2250 02B4 2348 02E5 2417 02FC 2431 0304 2450 030E 2457 0313 2528 0346 2542 034D 2645 0378 2651 037A 2679 038F 2744 0395 2786 039A 2825 03AF 2914 03C0 2952 03C6 2960 03C9 TITLE.MAC 12 0000 16 0000 72 0000 128 0000 267 0000 415 0000 482 00C0 849 0000 880 0000 1004 00C9 1110 00F9 1207 0112 1367 0149 1425 015F 1459 016F 1486 0177 1717 01D6 1744 01E0 1860 0200 1908 021C 2003 0248 2367 02F1 2590 0374 2685 0392 3004 03D8 3048 03EC 568 04FE 679 0546 764 056A 798 0588 918 05D2 3057 06AE 3105 0800 VECTOR 376 0000 1693 01D3 2374 02F1 2618 0374 2706 0392 2762 0398 2860 03BD 2893 03C0 2931 03C6 WASTE 274 0000 1089 00ED 1506 017D 1591 019B 1615 01A9 1668 01C7 1753 01E1 1870 0205 2006 0249 2135 027F 2204 029F 2451 030F 2652 037B 2915 03C1 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 139 PPU3/REV 25 microcode | cross-reference table C 0000 1416 0685 2620 0030 2621 0031 2622 0032 2623 0033 2708 0040 2709 0041 2710 0042 2711 0043 2764 0050 2765 0051 2766 0052 2767 0053 2789 039A 2803 039E 1421 068A CLC 0003 671 053E 704 0548 725 0556 847 059B 871 05AB 917 05D1 I 0001 1014 00C9 1015 00CA 1016 00CB 1019 00CC 1020 00CD 1022 00CE 1023 00CF 1025 00D0 1026 00D1 1028 00D2 1029 00D3 1031 00D4 1032 00D5 1034 00D6 1035 00D7 1037 00D8 1039 00D9 1041 00DA 1042 00DB 1044 00DC 1045 00DD 1047 00DE 1067 00E0 1068 00E1 1070 00E2 1073 00E4 1074 00E5 1076 00E6 1077 00E7 1079 00E8 1083 00C5 1085 00EA 1086 00EB 1089 00EC 1091 00EE 1098 00F2 1101 00F3 1103 00F4 1104 00F5 1106 00F6 1119 00F9 1120 00FA 1121 00FB 1122 00FC 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1133 07D7 1134 07D8 1138 07DC 1139 07DD 1140 07DE 1141 07DF 1154 00FE 1159 0100 1160 0101 1164 0102 1169 0104 1170 0105 1174 0106 1175 0107 1186 0108 1187 0109 1191 010A 1192 010B 1196 010C 1206 0111 1215 0113 1217 00ED 1219 0114 1220 0115 1222 0116 1223 0117 1224 0118 1225 0119 1226 011A 1230 07C0 1231 07C1 1232 07C2 1233 07C3 1234 07C4 1235 07C5 1236 07C6 1237 07C7 1238 07C8 1239 07C9 1240 07CA 1241 07CB 1242 07CC 1243 07CD 1244 07CE 1245 07CF 1249 011B 1250 011C 1251 011D 1252 011E 1253 011F 1257 0120 1258 0121 1262 0123 1270 0125 1271 0126 1272 0127 1273 0128 1277 07B0 1278 07B1 1279 07B2 1280 07B3 1281 07B4 1288 0129 1289 012A 1290 012B 1293 00FD 1295 012C 1296 012D 1303 0130 1310 07A3 1312 07A5 1313 07A6 1316 07A9 1317 07AA 1319 07AC 1327 0131 1328 0132 1329 0133 1331 0134 1332 0135 1333 0136 1337 0138 1338 0139 1340 013A 1341 013B 1346 013C 1347 013D 1349 013E 1350 013F 1352 0140 1353 0141 1355 0142 1357 0143 1362 0145 1370 0149 1372 014A 1373 014B 1375 014C 1376 014D 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1385 07BD 1386 07BE 1387 07BF 1392 07E4 1393 07E5 1394 07E6 1395 07E7 1400 014F 1401 0150 1405 0152 1406 0153 1408 0137 1410 0154 1411 0155 1413 0156 1414 0157 1419 015A 1420 015B 1421 015C 1422 015D 1424 015E 1437 015F 1438 0160 1439 0161 1440 0162 1444 0165 1446 0166 1447 0167 1450 0169 1471 016F 1473 0170 1474 0171 1477 0163 1480 0173 1483 0174 1484 0175 1497 0177 1499 0178 1500 0179 1503 017B 1506 017C 1531 0183 1533 0184 1534 0185 1537 017D 1539 0186 1540 0187 1542 0188 1543 0189 1544 018A 1563 0791 1564 0792 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 1574 0190 1576 0191 1578 0192 1579 0193 1582 0195 1584 0196 1585 0197 1589 0199 1591 019A 1593 019C 1596 019E 1599 019B 1601 01A0 1602 01A1 1605 01A3 1607 01A4 1608 01A5 1610 01A6 1613 01A7 1615 01A8 1617 01AA 1620 01AC 1623 01A9 1625 01AE 1626 01AF 1628 01B0 1629 01B1 1632 01B3 1634 01B4 1635 01B5 1638 01B7 1641 01B8 1657 01C0 1658 01C1 1660 01C2 1661 01C3 1664 01C4 1666 01C5 1668 01C6 1670 01C8 1671 01C9 1674 01CA 1680 01CE 1681 01CF 1683 01D0 1716 01D5 1727 01C7 1729 01D6 1730 01D7 1732 01D8 1733 01D9 1735 01DA 1736 01DB 1739 01DD 1742 01DE 1753 01E0 1756 01E3 1758 01E4 1766 079A 1768 079C 1780 01E6 1792 01EA 1824 01EF 1825 01F0 1831 01F2 1835 01F4 1836 01F5 1840 01F7 1853 01FC 1857 01FE 1865 0201 1867 0202 1868 0203 1870 0204 1872 0206 1873 0207 1875 0208 1876 0209 1878 020A 1880 020B 1881 020C 1882 020D 1883 020E 1884 020F 1885 0210 1889 07E8 1890 07E9 1891 07EA 1892 07EB 1896 0211 1897 0212 1898 0213 1899 0214 1910 021C 1911 021D 1912 021E 1913 021F 1916 0221 1918 0222 1923 0205 1925 0224 1926 0225 1928 0226 1929 0227 1934 022A 1935 022B 1936 022C 1937 022D 1938 022E 1939 022F 1941 0230 1942 0231 1948 0233 1953 0780 1955 0782 1956 0783 1957 0784 1958 0785 1959 0786 1960 0787 1961 0788 1972 0234 1973 0235 1977 0239 1986 023E 1992 0240 2002 0247 2006 0248 2009 024B 2011 024C 2012 024D 2013 024E 2014 024F 2016 0249 2018 0250 2019 0251 2021 0252 2022 0253 2027 0256 2028 0257 2029 0258 2030 0259 2031 025A 2032 025B 2033 025C 2039 025F 2046 0772 2047 0773 2048 0774 2049 0775 2050 0776 2051 0777 2052 0778 2066 025D 2068 0262 2069 0263 2071 0264 2087 0271 2090 0273 2105 0274 2106 0275 2108 0276 2109 0277 2111 0278 2112 0279 2114 027A 2115 027B 2120 027C 2121 027D 2143 0284 2144 0285 2146 0286 2147 0287 2150 0288 2151 0289 2163 028A 2166 028D 2167 028E 2168 028F 2171 0291 2174 0294 2175 0295 2191 0298 2231 02AC 2232 02AD 2234 02AE 2235 02AF 2237 02B0 2238 02B1 2241 029F 2244 02B3 2251 02AB 2254 02B5 2256 02B6 2257 02B7 2260 02B8 2263 02BB 2264 02BC 2265 02BD 2269 02BF 2272 02C0 2273 02C1 2274 02C2 2275 02C3 2276 02C4 2277 02C5 2278 02C6 2279 02C7 2280 02C8 2281 02C9 2282 02CA 2285 02CC 2298 02CE 2307 02D0 2308 02D1 2309 02D2 2313 02D5 2315 02D6 2316 02D7 2317 02D8 2318 02D9 2319 02DA 2320 02DB 2321 02DC 2322 02DD 2323 02DE 2324 02DF 2325 02E0 2326 02E1 2330 02E2 2331 02E3 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 140 PPU3/REV 25 microcode | cross-reference table 2347 02E4 2349 02E5 2351 02E6 2352 02E7 2355 02E8 2356 02E9 2357 02EA 2358 02EB 2361 02EC 2362 02ED 2363 02EE 2364 02EF 2471 031D 2485 0324 2648 0378 2683 0391 2699 0754 2700 0755 2701 0756 2702 0757 2747 0396 2789 039A 2828 03B0 2846 03BB 2921 03C5 3003 03D7 1382 067A IP 0002 1298 012E 1299 012F 1361 0144 1443 0164 1449 0168 1479 0172 1502 017A 1508 017E 1685 01D2 1738 01DC 1743 01DF 1796 01EE 1931 0228 2024 0254 2085 0270 2200 029C 2206 02A0 2209 02A2 2212 02A4 2214 02A6 2216 02A8 2218 02AA 2624 0034 2625 0035 2626 0036 2627 0037 2658 037F 2661 0381 2712 0044 2713 0045 2714 0046 2715 0047 2768 0054 2769 0055 2770 0056 2771 0057 2883 03BF NOP 0000 914 0000 918 0090 919 0091 920 0092 921 0093 2546 034F 53 0407 57 040B 88 0421 112 0431 265 046D 405 048B 414 0493 423 049B 460 04B7 465 04BB 470 04BF 475 04C3 480 04C7 485 04CB 490 04CF 495 04D3 500 04D7 505 04DB 510 04DF 515 04E3 520 04E7 525 04EB 530 04EF 648 0537 668 053B 895 05BC 1247 0624 1377 0675 1381 0679 1420 0689 1439 0698 P 0000 1545 018B 1642 01B9 1646 01BD 2276 02C4 2285 02CC 2286 02CD 2316 02D7 2318 02D9 2357 02EA 2358 02EB 2620 0030 2621 0031 2622 0032 2623 0033 2641 0374 2648 0378 2649 0379 2670 0386 2672 0388 2747 0396 2764 0050 2765 0051 2766 0052 2767 0053 2785 0399 2789 039A 2803 039E 2804 039F 2819 03A9 2828 03B0 2829 03B1 2838 03B4 2839 03B5 2975 03D0 2989 03D4 839 0596 840 0597 852 05A0 853 05A1 862 05A5 863 05A6 876 05B0 877 05B1 886 05B3 887 05B4 STC 0001 1071 00E3 1653 01BE 1987 023F 2164 028B 2172 0292 2243 02B2 2253 02B4 2261 02B9 649 0538 705 0549 746 0562 757 0566 1421 068A 1080 00E9 T2 0001 1471 06A5 2642 0375 2644 0377 T3 0000 2083 026E 1681 01CF 1683 01D0 T4 0003 927 0097 2520 033E 3019 03D9 46 0400 1417 0686 1438 0697 1469 06A3 1470 06A4 1473 06A7 965 00B2 970 00B7 1579 0193 1582 0195 1584 0196 1593 019C 1602 01A1 1605 01A3 1607 01A4 1617 01AA 1625 01AE 1629 01B1 1632 01B3 1634 01B4 1678 01CD 2081 026C 2140 0282 2141 0283 2189 0297 2192 0299 TWC 0002 1655 01BF 1990 023D 2165 028C 2173 0293 2262 02BA 2306 02CF 650 0539 672 053F 673 0540 676 0543 706 054A 726 0557 727 0558 747 0563 758 0567 1422 068B 1074 00E5 1083 00C5 849 059D 851 059F 852 05A0 853 05A1 854 05A2 873 05AD 875 05AF 876 05B0 877 05B1 878 05B2 X1 0001 931 009A 932 009B 938 009F 939 00A0 963 00B0 964 00B1 965 00B2 966 00B3 967 00B4 968 00B5 969 00B6 970 00B7 971 00B8 975 07E0 976 07E1 977 07E2 978 07E3 982 00B9 986 00BC 987 00BD 988 00BE 989 00BF 991 00C0 993 00C1 994 00C2 995 00C3 1080 00E9 1155 00FF 1165 0103 1197 010D 1214 0112 1261 0122 1269 0124 1364 0146 1365 0147 1366 0148 1399 014E 1404 0151 1416 0158 1417 0159 1453 016B 1455 016C 1456 016D 1509 017F 1519 0181 1520 0182 1545 018B 1546 018C 1548 018E 1587 0198 1594 019D 1597 019F 1618 01AB 1621 01AD 1637 01B6 1642 01B9 1645 01BC 1646 01BD 1675 01CB 1676 01CC 1678 01CD 1684 01D1 1695 0010 1696 0011 1764 0798 1846 01F8 1848 01FA 1901 0215 1902 0216 1903 0217 1904 0218 1905 0219 1906 021A 1907 021B 1914 0220 1932 0229 1974 0236 1975 0237 1976 0238 1979 023A 1981 023B 1982 023C 1993 0241 1998 0244 1999 0245 2000 0246 2025 0255 2044 0770 2045 0771 2063 0260 2073 0265 2074 0266 2076 0267 2077 0268 2079 026A 2080 026B 2081 026C 2084 026F 2089 0272 2135 027E 2137 0280 2138 0281 2140 0282 2141 0283 2169 0290 2176 0296 2189 0297 2192 0299 2195 029A 2198 027F 2204 029E 2210 02A3 2268 02BE 2286 02CD 2291 0760 2292 0761 2293 0762 2294 0763 2312 02D4 2495 0326 2496 0327 2497 0328 2498 0329 2499 032A 2500 032B 2504 032E 2506 0330 2508 0332 2510 0334 2512 0336 2514 0338 2516 033A 2518 033C 2524 0342 2580 036B 2581 036C 2582 036D 2583 036E 2584 036F 2585 0370 2587 0371 2588 0372 2589 0373 2600 0764 2601 0765 2602 0766 2603 0767 3032 03E2 3033 03E3 3034 03E4 3035 03E5 3036 03E6 3037 03E7 3038 03E8 3039 03E9 58 040C 59 040D 126 0436 136 043B 146 0441 156 0447 253 0464 254 0465 261 046A 262 046B 818 058A 819 058B 820 058C 825 058E 827 0590 828 0591 829 0592 831 0593 837 0594 839 0596 840 0597 841 0598 842 0599 849 059D 851 059F 852 05A0 853 05A1 854 05A2 861 05A4 862 05A5 863 05A6 864 05A7 865 05A8 873 05AD 875 05AF 876 05B0 877 05B1 878 05B2 886 05B3 887 05B4 888 05B5 889 05B6 890 05B7 903 05C3 905 05C5 907 05C7 911 05CB 913 05CD 915 05CF 1128 05E1 1140 05EA 1141 05EB 1142 05EC 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 141 PPU3/REV 25 microcode | cross-reference table 1143 05ED 1145 05EE 1153 05F1 1154 05F2 1157 05F3 1162 05F7 1164 05F9 1165 05FA 1203 0607 1215 0609 1216 060A 1217 060B 1218 060C 1219 060D 1232 0615 1234 0617 1236 0619 1238 061B 1240 061D 1241 061E 1242 061F 1243 0620 1244 0621 1246 0623 1248 0625 1249 0626 1250 0627 1252 0629 1256 062D 1257 062E 1294 0637 1295 0638 1297 063A 1298 063B 1299 063C 1301 063E 1302 063F 1303 0640 1305 0642 1306 0643 1307 0644 1309 0646 1310 0647 1311 0648 1312 0649 1313 064A 1314 064B 1315 064C 1316 064D 1317 064E 1319 064F 1320 0650 1321 0651 1322 0652 1323 0653 1324 0654 1325 0655 1326 0656 1327 0657 1328 0658 1329 0659 1330 065A 1364 066B 1366 066D 1367 066E 1368 066F 1369 0670 1370 0671 1410 067F 1411 0680 1413 0682 1427 068D 1434 0693 1016 00CB 1020 00CD 1023 00CF 1026 00D1 1028 00D2 1031 00D4 1032 00D5 1037 00D8 1041 00DA 1067 00E0 1074 00E5 1077 00E7 1083 00C5 1086 00EB 1091 00EE 1106 00F6 1120 00FA 1121 00FB 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1133 07D7 1134 07D8 1140 07DE 1141 07DF 1160 0101 1170 0105 1206 0111 1215 0113 1217 00ED 1219 0114 1220 0115 1222 0116 1223 0117 1224 0118 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1249 011B 1250 011C 1251 011D 1252 011E 1253 011F 1257 0120 1258 0121 1262 0123 1270 0125 1271 0126 1272 0127 1277 07B0 1278 07B1 1279 07B2 1280 07B3 1281 07B4 1288 0129 1289 012A 1290 012B 1293 00FD 1295 012C 1296 012D 1298 012E 1310 07A3 1312 07A5 1313 07A6 1316 07A9 1317 07AA 1319 07AC 1327 0131 1328 0132 1329 0133 1331 0134 1332 0135 1333 0136 1337 0138 1338 0139 1340 013A 1341 013B 1346 013C 1347 013D 1349 013E 1350 013F 1352 0140 1353 0141 1355 0142 1357 0143 1362 0145 1370 0149 1372 014A 1373 014B 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1386 07BE 1387 07BF 1392 07E4 1394 07E6 1395 07E7 1400 014F 1401 0150 1405 0152 1406 0153 1408 0137 1410 0154 1411 0155 1413 0156 1414 0157 1419 015A 1420 015B 1421 015C 1422 015D 1424 015E 1437 015F 1438 0160 1439 0161 1444 0165 1446 0166 1471 016F 1473 0170 1474 0171 1480 0173 1483 0174 1484 0175 1497 0177 1499 0178 1500 0179 1503 017B 1533 0184 1534 0185 1539 0186 1540 0187 1543 0189 1563 0791 1564 0792 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 1574 0190 1578 0192 1579 0193 1585 0197 1589 0199 1593 019C 1596 019E 1601 01A0 1602 01A1 1608 01A5 1610 01A6 1613 01A7 1617 01AA 1620 01AC 1625 01AE 1628 01B0 1629 01B1 1635 01B5 1638 01B7 1641 01B8 1653 01BE 1655 01BF 1657 01C0 1658 01C1 1660 01C2 1661 01C3 1664 01C4 1666 01C5 1670 01C8 1671 01C9 1674 01CA 1680 01CE 1685 01D2 1727 01C7 1729 01D6 1730 01D7 1732 01D8 1733 01D9 1735 01DA 1736 01DB 1739 01DD 1742 01DE 1753 01E0 1756 01E3 1766 079A 1768 079C 1831 01F2 1836 01F5 1840 01F7 1853 01FC 1865 0201 1867 0202 1868 0203 1870 0204 1872 0206 1875 0208 1878 020A 1880 020B 1881 020C 1889 07E8 1890 07E9 1891 07EA 1892 07EB 1896 0211 1897 0212 1898 0213 1899 0214 1910 021C 1911 021D 1912 021E 1913 021F 1926 0225 1929 0227 1934 022A 1935 022B 1936 022C 1937 022D 1939 022F 1955 0782 1956 0783 1957 0784 1958 0785 1959 0786 1960 0787 1972 0234 1973 0235 1977 0239 1986 023E 1987 023F 1990 023D 1992 0240 2009 024B 2011 024C 2012 024D 2013 024E 2019 0251 2022 0253 2027 0256 2028 0257 2029 0258 2030 0259 2031 025A 2033 025C 2048 0774 2049 0775 2051 0777 2071 0264 2085 0270 2087 0271 2090 0273 2105 0274 2108 0276 2111 0278 2114 027A 2115 027B 2120 027C 2121 027D 2143 0284 2147 0287 2164 028B 2165 028C 2166 028D 2167 028E 2168 028F 2171 0291 2172 0292 2173 0293 2174 0294 2175 0295 2191 0298 2231 02AC 2234 02AE 2237 02B0 2238 02B1 2241 029F 2243 02B2 2244 02B3 2251 02AB 2256 02B6 2257 02B7 2262 02BA 2263 02BB 2264 02BC 2265 02BD 2269 02BF 2272 02C0 2273 02C1 2274 02C2 2275 02C3 2276 02C4 2277 02C5 2278 02C6 2279 02C7 2280 02C8 2281 02C9 2282 02CA 2285 02CC 2298 02CE 2306 02CF 2307 02D0 2308 02D1 2309 02D2 2313 02D5 2315 02D6 2316 02D7 2317 02D8 2318 02D9 2319 02DA 2320 02DB 2321 02DC 2322 02DD 2323 02DE 2324 02DF 2325 02E0 2326 02E1 2330 02E2 2331 02E3 2347 02E4 2349 02E5 2355 02E8 2356 02E9 2357 02EA 2358 02EB 2361 02EC 2362 02ED 2363 02EE 2364 02EF X2 0000 2416 02FB 2418 02CB 2424 02FF 2426 0300 2427 0301 2428 0302 2430 0303 2432 02D3 2437 0306 2438 0307 2444 030A 2447 030C 2448 030D 2454 0311 2467 0319 2469 031B 2503 032D 2505 032F 2507 0331 2509 0333 2511 0335 2513 0337 2515 0339 2517 033B 2519 033D 2527 0345 2535 0349 2537 034A 2538 034B 2539 034C 2552 0353 2553 0354 2554 0355 2555 0356 2560 035A 2561 035B 2562 035C 2563 035D 2567 0360 2568 0361 2569 0362 2570 0363 2575 0367 2576 0368 2577 0369 2578 036A 2620 0030 2621 0031 2622 0032 2623 0033 2641 0374 2642 0375 2643 0376 2644 0377 2646 0321 2649 0379 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 142 PPU3/REV 25 microcode | cross-reference table 2652 037A 2654 037C 2655 037D 2665 0382 2666 0383 2668 0384 2669 0385 2670 0386 2671 0387 2672 0388 2673 0389 2674 038A 2675 038B 2676 038C 2677 038D 2678 038E 2680 038F 2682 0390 2708 0040 2709 0041 2710 0042 2711 0043 2729 0392 2740 0393 2745 0395 2748 0397 2764 0050 2765 0051 2766 0052 2767 0053 2784 0398 2785 0399 2787 037B 2790 039B 2792 039C 2793 039D 2803 039E 2804 039F 2807 03A1 2811 03A2 2812 03A3 2814 03A4 2815 03A5 2816 03A6 2817 03A7 2818 03A8 2819 03A9 2820 03AA 2821 03AB 2822 03AC 2823 03AD 2824 03AE 2826 03AF 2829 03B1 2836 03B3 2838 03B4 2839 03B5 2842 03B7 2843 03B8 2845 03BA 2848 03BC 2862 0060 2863 0061 2881 03BD 2882 03BE 2895 0070 2896 0071 2915 03C0 2917 03C2 2918 03C3 2920 03C4 2933 0080 2934 0081 2953 03C1 2955 03C6 2956 03C7 2958 03C8 2961 03C9 2963 03CA 2964 03CB 2970 03CC 2971 03CD 2973 03CE 2974 03CF 2975 03D0 2976 03D1 2981 076D 2982 076E 2983 076F 2987 03D3 2989 03D4 2995 0741 2996 0742 2997 0743 3001 03D6 61 040F 167 044B 177 0451 187 0457 197 045D 351 0474 352 0475 367 047E 368 047F 369 0480 370 0481 398 0485 399 0486 400 0487 407 048D 408 048E 409 048F 415 0494 417 0496 418 0497 420 0499 421 049A 424 049C 426 049E 427 049F 429 04A1 430 04A2 457 04B4 458 04B5 462 04B8 463 04B9 467 04BC 468 04BD 472 04C0 473 04C1 477 04C4 478 04C5 482 04C8 483 04C9 487 04CC 488 04CD 492 04D0 493 04D1 497 04D4 498 04D5 502 04D8 503 04D9 507 04DC 508 04DD 512 04E0 513 04E1 517 04E4 518 04E5 522 04E8 523 04E9 527 04EC 528 04ED 532 04F0 533 04F1 549 04F4 554 04F5 561 04F7 562 04F8 563 04F9 564 04FA 565 04FB 573 04FE 574 04FF 575 0500 576 0501 577 0502 578 0503 579 0504 580 0505 581 0506 582 0507 583 0508 584 0509 585 050A 586 050B 587 050C 588 050D 593 050F 595 0511 597 0513 599 0515 601 0517 603 0519 605 051B 607 051D 609 051F 611 0521 613 0523 615 0525 617 0527 619 0529 621 052B 623 052D 643 0532 644 0533 645 0534 707 054B 711 054E 712 054F 714 0551 716 0552 728 0559 732 055C 733 055D 735 055F 736 0560 767 056C 768 056D 769 056E 770 056F 771 0570 779 0575 780 0576 791 0581 792 0582 793 0583 796 0586 1115 05D8 1124 05DE 1187 0600 1260 0631 2648 0378 2658 037F 2661 0381 2683 0391 2747 0396 2789 039A 2828 03B0 2846 03BB 2883 03BF 671 053E 672 053F 673 0540 676 0543 704 0548 706 054A 725 0556 727 0558 746 0562 747 0563 757 0566 758 0567 1422 068B 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 143 PPU3/REV 25 microcode | cross-reference table CSCCO 0104 CSIN 0104 1214 0112 1269 0124 1404 0151 DPIN 0201 1587 0198 1594 019D 1618 01AB 1637 01B6 2642 0375 2644 0377 LIT 030D 930 0099 937 009E 938 009F 939 00A0 945 00A5 947 00A6 952 00AA 956 00AC 957 00AD 958 00AE 963 00B0 966 00B3 975 07E0 976 07E1 977 07E2 978 07E3 995 00C3 1003 00C8 1016 00CB 1020 00CD 1023 00CF 1031 00D4 1037 00D8 1041 00DA 1076 00E6 1077 00E7 1119 00F9 1130 07D4 1131 07D5 1132 07D6 1135 07D9 1136 07DA 1137 07DB 1160 0101 1170 0105 1206 0111 1217 00ED 1220 0115 1222 0116 1257 0120 1258 0121 1261 0122 1262 0123 1271 0126 1272 0127 1277 07B0 1282 07B5 1283 07B6 1284 07B7 1288 0129 1289 012A 1293 00FD 1295 012C 1296 012D 1298 012E 1307 07A0 1308 07A1 1309 07A2 1311 07A4 1312 07A5 1313 07A6 1314 07A7 1315 07A8 1316 07A9 1317 07AA 1318 07AB 1320 07AD 1321 07AE 1322 07AF 1337 0138 1338 0139 1340 013A 1341 013B 1346 013C 1347 013D 1349 013E 1350 013F 1352 0140 1353 0141 1355 0142 1357 0143 1366 0148 1370 0149 1372 014A 1373 014B 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1386 07BE 1387 07BF 1392 07E4 1394 07E6 1395 07E7 1401 0150 1408 0137 1410 0154 1411 0155 1414 0157 1416 0158 1417 0159 1419 015A 1420 015B 1421 015C 1424 015E 1446 0166 1453 016B 1455 016C 1471 016F 1473 0170 1480 0173 1483 0174 1497 0177 1500 0179 1503 017B 1519 0181 1520 0182 1533 0184 1539 0186 1540 0187 1543 0189 1547 018D 1548 018E 1562 0790 1563 0791 1564 0792 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 1578 0192 1579 0193 1585 0197 1593 019C 1601 01A0 1602 01A1 1610 01A6 1617 01AA 1625 01AE 1628 01B0 1629 01B1 1638 01B7 1646 01BD 1653 01BE 1658 01C1 1660 01C2 1661 01C3 1664 01C4 1670 01C8 1675 01CB 1680 01CE 1685 01D2 1695 0010 1715 01D4 1727 01C7 1729 01D6 1730 01D7 1732 01D8 1733 01D9 1735 01DA 1742 01DE 1743 01DF 1753 01E0 1755 01E2 1756 01E3 1764 0798 1765 0799 1766 079A 1767 079B 1768 079C 1770 079E 1771 079F 1831 01F2 1840 01F7 1848 01FA 1853 01FC 1864 0200 1865 0201 1870 0204 1876 0209 1878 020A 1881 020C 1913 021F 1914 0220 1919 0223 1926 0225 1929 0227 1932 0229 1934 022A 1935 022B 1947 0232 1962 0789 1963 078A 1964 078B 1965 078C 1966 078D 1967 078E 1968 078F 1998 0244 2000 0246 2008 024A 2013 024E 2019 0251 2022 0253 2025 0255 2027 0256 2028 0257 2038 025E 2045 0771 2048 0774 2053 0779 2054 077A 2055 077B 2056 077C 2057 077D 2058 077E 2059 077F 2066 025D 2073 0265 2079 026A 2105 0274 2114 027A 2120 027C 2121 027D 2135 027E 2138 0281 2140 0282 2143 0284 2147 0287 2156 07EC 2157 07ED 2158 07EE 2159 07EF 2168 028F 2171 0291 2172 0292 2175 0295 2189 0297 2191 0298 2198 027F 2201 029D 2204 029E 2231 02AC 2237 02B0 2241 029F 2243 02B2 2244 02B3 2251 02AB 2257 02B7 2265 02BD 2269 02BF 2282 02CA 2291 0760 2292 0761 2293 0762 2294 0763 2308 02D1 2309 02D2 2313 02D5 2326 02E1 2330 02E2 2347 02E4 2349 02E5 2366 02F0 2376 0020 2377 0021 2378 0022 2379 0023 2380 0024 2381 0025 2382 0026 2383 0027 2395 02F1 2396 02F2 2397 02F3 2398 02F4 2399 02F5 2416 02FB 2418 02CB 2430 0303 2432 02D3 2444 030A 2447 030C 2448 030D 2454 0311 2461 0315 2463 0316 2469 031B 2470 031C 2471 031D 2475 031E 2476 031F 2502 032C 2504 032E 2506 0330 2508 0332 2510 0334 2521 033F 2527 0345 2545 034E 2549 0350 2550 0351 2557 0357 2558 0358 2565 035E 2572 0364 2573 0365 2580 036B 2582 036D 2600 0764 2601 0765 2602 0766 2603 0767 2646 0321 2648 0378 2649 0379 2652 037A 2654 037C 2658 037F 2661 0381 2666 0383 2680 038F 2695 0750 2696 0751 2697 0752 2698 0753 2699 0754 2700 0755 2701 0756 2702 0757 2708 0040 2709 0041 2710 0042 2711 0043 2733 0768 2734 0769 2735 076A 2736 076B 2740 0393 2741 0394 2745 0395 2747 0396 2748 0397 2787 037B 2789 039A 2790 039B 2792 039C 2793 039D 2803 039E 2804 039F 2806 03A0 2807 03A1 2812 03A3 2826 03AF 2835 03B2 2836 03B3 2838 03B4 2839 03B5 2841 03B6 2842 03B7 2846 03BB 2862 0060 2915 03C0 2917 03C2 2921 03C5 2956 03C7 2961 03C9 2963 03CA 2975 03D0 2980 076C 2989 03D4 2994 0740 3003 03D7 3012 03D8 3021 03DB 3024 03DD 3042 03EB 17 0001 18 0002 19 0003 20 0004 21 0005 22 0006 23 0007 24 0008 25 0009 26 000A 27 000B 28 000C 29 000D 30 000E 31 000F 47 0401 49 0403 58 040C 59 040D 60 040E 61 040F 73 0412 75 0414 78 0417 79 0418 81 041A 83 041C 86 041F 87 0420 103 0428 105 042A 107 042C 109 042E 111 0430 124 0434 125 0435 132 0438 134 0439 135 043A 142 043E 144 043F 145 0440 152 0444 154 0445 155 0446 162 044A 173 044E 175 044F 176 0450 183 0454 185 0455 186 0456 193 045A 195 045B 196 045C 203 0460 206 0461 211 0745 212 0746 213 0747 219 0748 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 144 PPU3/REV 25 microcode | cross-reference table 221 074A 222 074B 228 074C 229 074D 231 074F 237 0730 238 0731 239 0732 252 0463 255 0466 260 0469 263 046C 274 0720 275 0721 276 0722 277 0723 278 0724 279 0725 280 0726 281 0727 282 0728 283 0729 284 072A 285 072B 286 072C 287 072D 288 072E 289 072F 295 0710 296 0711 297 0712 298 0713 299 0714 300 0715 301 0716 302 0717 303 0718 304 0719 305 071A 306 071B 307 071C 308 071D 309 071E 310 071F 316 0700 317 0701 318 0702 319 0703 320 0704 321 0705 322 0706 323 0707 324 0708 325 0709 326 070A 327 070B 328 070C 329 070D 330 070E 331 070F 349 0472 350 0473 353 0476 355 0477 356 0478 368 047F 372 0483 397 0484 398 0485 401 0488 406 048C 407 048D 410 0490 415 0494 416 0495 419 0498 420 0499 421 049A 424 049C 425 049D 428 04A0 429 04A1 430 04A2 440 04A4 441 04A5 442 04A6 443 04A7 444 04A8 445 04A9 446 04AA 447 04AB 448 04AC 449 04AD 450 04AE 451 04AF 452 04B0 453 04B1 454 04B2 455 04B3 457 04B4 459 04B6 462 04B8 464 04BA 467 04BC 469 04BE 472 04C0 474 04C2 477 04C4 479 04C6 482 04C8 484 04CA 487 04CC 489 04CE 492 04D0 494 04D2 497 04D4 499 04D6 502 04D8 504 04DA 507 04DC 509 04DE 512 04E0 514 04E2 517 04E4 519 04E6 522 04E8 524 04EA 527 04EC 529 04EE 532 04F0 534 04F2 535 04F3 549 04F4 561 04F7 562 04F8 594 0510 596 0512 598 0514 600 0516 602 0518 604 051A 606 051C 608 051E 610 0520 612 0522 614 0524 616 0526 618 0528 620 052A 622 052C 624 052E 642 0531 643 0532 646 0535 647 0536 649 0538 651 053A 669 053C 670 053D 671 053E 674 0541 675 0542 677 0544 702 0546 703 0547 704 0548 709 054D 716 0552 722 0553 723 0554 724 0555 726 0557 730 055B 736 0560 745 0561 746 0562 748 0564 756 0565 757 0566 759 0568 765 056A 766 056B 769 056E 770 056F 781 0577 782 0578 787 057D 790 0580 795 0585 821 058D 828 0591 831 0593 837 0594 839 0596 840 0597 841 0598 842 0599 850 059E 854 05A2 861 05A4 878 05B2 904 05C4 906 05C6 908 05C8 910 05CA 912 05CC 914 05CE 916 05D0 917 05D1 1110 05D5 1118 05DA 1122 05DD 1124 05DE 1128 05E1 1129 05E2 1130 05E3 1131 05E4 1132 05E5 1133 05E6 1134 05E7 1135 05E8 1136 05E9 1140 05EA 1141 05EB 1142 05EC 1143 05ED 1145 05EE 1153 05F1 1157 05F3 1162 05F7 1163 05F8 1164 05F9 1165 05FA 1183 05FF 1190 0602 1194 0605 1202 0606 1214 0608 1215 0609 1217 060B 1219 060D 1233 0616 1235 0618 1237 061A 1239 061C 1240 061D 1241 061E 1242 061F 1243 0620 1244 0621 1246 0623 1248 0625 1249 0626 1250 0627 1252 0629 1253 062A 1257 062E 1258 062F 1260 0631 1261 0632 1272 06F0 1273 06F1 1274 06F2 1275 06F3 1280 06F8 1281 06F9 1282 06FA 1283 06FB 1294 0637 1295 0638 1296 0639 1297 063A 1298 063B 1299 063C 1300 063D 1301 063E 1302 063F 1303 0640 1304 0641 1305 0642 1306 0643 1307 0644 1308 0645 1309 0646 1310 0647 1311 0648 1312 0649 1313 064A 1314 064B 1315 064C 1316 064D 1317 064E 1319 064F 1320 0650 1321 0651 1322 0652 1323 0653 1324 0654 1325 0655 1326 0656 1327 0657 1328 0658 1329 0659 1330 065A 1340 065C 1341 065D 1343 065F 1349 0665 1362 0669 1363 066A 1364 066B 1365 066C 1370 0671 1384 067C 1401 0734 1402 0735 1403 0736 1404 0737 1409 067E 1411 0680 1412 0681 1414 0683 1415 0684 1421 068A 1422 068B 1428 068E 1429 068F 1430 0690 1431 0691 1433 0692 1435 0694 1436 0695 1437 0696 1440 0699 1457 069A 1478 06AC 1479 06AD NOP 030D PTST 0102 1032 00D5 1120 00FA 1474 0171 1499 0178 1534 0185 1574 0190 1589 0199 1597 019F 1613 01A7 1621 01AD 1666 01C5 1674 01CA 1115 05D8 1187 0600 1254 062B 1474 06A8 SBFT 011E 2428 0302 2500 032B 2522 0340 816 0588 901 05C2 SBHC 0217 1696 0011 2426 0300 2496 0327 2535 0349 2863 0061 2896 0071 2918 03C3 2971 03CD 2995 0741 2996 0742 2997 0743 896 05BD 1227 0611 1342 065E 1416 0685 SBHD 021B 2437 0306 2498 0329 2538 034B 2882 03BE 2981 076D 2982 076E 2983 076F 899 05C0 1229 0613 1418 0687 SBLC 0219 1714 01D3 2427 0301 2497 0328 2537 034A 2881 03BD 2920 03C4 2973 03CE 3001 03D6 897 05BE 1228 0612 1417 0686 SBLD 021D 2438 0307 2499 032A 2539 034C 2883 03BF 2987 03D3 900 05C1 1230 0614 1419 0688 SBST 0114 926 0096 1048 00DF 1094 00F0 1095 00F1 1098 00F2 1107 00F7 1581 0194 1604 01A2 1631 01B2 1697 0012 1698 0013 1699 0014 1700 0015 1701 0016 1702 0017 1703 0018 1704 0019 1705 001A 1706 001B 1707 001C 1708 001D 1709 001E 1710 001F 1825 01F0 1835 01F4 1857 01FE 1858 01FF 2384 0028 2385 0029 2386 002A 2387 002B 2388 002C 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 145 PPU3/REV 25 microcode | cross-reference table 2389 002D 2390 002E 2391 002F 2420 02FC 2423 02FE 2424 02FF 2534 0348 2628 0038 2629 0039 2630 003A 2631 003B 2632 003C 2633 003D 2634 003E 2635 003F 2716 0048 2717 0049 2718 004A 2719 004B 2720 004C 2721 004D 2722 004E 2723 004F 2772 0058 2773 0059 2774 005A 2775 005B 2776 005C 2777 005D 2778 005E 2779 005F 2864 0062 2865 0063 2866 0064 2867 0065 2868 0066 2869 0067 2870 0068 2871 0069 2872 006A 2873 006B 2874 006C 2875 006D 2876 006E 2877 006F 2895 0070 2897 0072 2898 0073 2899 0074 2900 0075 2901 0076 2902 0077 2903 0078 2904 0079 2905 007A 2906 007B 2907 007C 2908 007D 2909 007E 2910 007F 2935 0082 2936 0083 2937 0084 2938 0085 2939 0086 2940 0087 2941 0088 2942 0089 2943 008A 2944 008B 2945 008C 2946 008D 2947 008E 2948 008F 2955 03C6 891 05B8 893 05BA 894 05BB 898 05BF 1344 0660 1346 0662 1378 0676 1380 0678 SCR0 000B 924 0095 1028 00D2 1029 00D3 1039 00D9 1068 00E1 1092 00EF 1101 00F3 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1133 07D7 1134 07D8 1140 07DE 1141 07DF 1215 0113 1223 0117 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1253 011F 1270 0125 1278 07B1 1279 07B2 1280 07B3 1281 07B4 1290 012B 1327 0131 1329 0133 1331 0134 1333 0136 1399 014E 1400 014F 1405 0152 1406 0153 1422 015D 1439 0161 1440 0162 1447 0167 1477 0163 1506 017C 1537 017D 1582 0195 1605 01A3 1632 01B3 1668 01C6 1678 01CD 1832 01F3 1839 01F6 1867 0202 1872 0206 1875 0208 1880 020B 1882 020D 1883 020E 1901 0215 1902 0216 1903 0217 1904 0218 1905 0219 1906 021A 1907 021B 1910 021C 1916 0221 1918 0222 2006 0248 2014 024F 2068 0262 2144 0285 2150 0288 2151 0289 2163 028A 2165 028C 2166 028D 2167 028E 2173 0293 2174 0294 2207 02A1 2253 02B4 2254 02B5 2260 02B8 2261 02B9 2262 02BA 2263 02BB 2273 02C1 2274 02C2 2276 02C4 2278 02C6 2280 02C8 2285 02CC 2286 02CD 2306 02CF 2307 02D0 2316 02D7 2318 02D9 2320 02DB 2322 02DD 2324 02DF 2325 02E0 2351 02E6 2352 02E7 2355 02E8 2357 02EA 2361 02EC 2363 02EE 2495 0326 2505 032F 2507 0331 2509 0333 2511 0335 2513 0337 2515 0339 2517 033B 2519 033D 2523 0341 2524 0342 2525 0343 2526 0344 2529 030F 2552 0353 2560 035A 2567 0360 2575 0367 2581 036C 2584 036F 3025 03DE 3030 03E1 3040 03EA 51 0405 55 0409 102 0427 104 0429 106 042B 108 042D 110 042F 131 0437 141 043D 151 0443 161 0449 172 044D 182 0453 192 0459 202 045F 254 0465 262 046B 351 0474 370 0481 399 0486 400 0487 402 0489 403 048A 408 048E 409 048F 411 0491 412 0492 418 0497 427 049F 458 04B5 554 04F5 563 04F9 564 04FA 565 04FB 593 050F 767 056C 768 056D 771 0570 773 0572 774 0573 779 0575 784 057A 785 057B 791 0581 793 0583 796 0586 797 0587 817 0589 818 058A 819 058B 820 058C 825 058E 829 0592 847 059B 871 05AB 892 05B9 903 05C3 1108 05D3 1151 05EF 1160 05F5 1173 05FD 1203 0607 1224 060F 1255 062C 1256 062D 1458 069B 1476 06AA 1477 06AB SCR1 010B 967 00B4 968 00B5 1083 00C5 1086 00EB 1159 0100 1164 0102 1169 0104 1174 0106 1186 0108 1191 010A 1196 010C 1531 0183 1542 0188 1546 018C 1643 01BA 1781 01E7 1979 023A 1981 023B 1982 023C 1990 023D 2031 025A 2049 0775 2051 0777 2553 0354 2561 035B 2568 0361 2576 0368 2583 036E 253 0464 257 0467 261 046A 266 046E 267 046F 352 0475 361 047B 367 047E 463 04B9 595 0511 676 0543 772 0571 783 0579 789 057F 826 058F 909 05C9 1111 05D6 1119 05DB 1121 05DC 1191 0603 1193 0604 1467 06A1 1475 06A9 SCR2 020B 970 00B7 971 00B8 1250 011C 1252 011E 1644 01BB 1782 01E8 1937 022D 1942 0231 2033 025C 2046 0772 2047 0773 2050 0776 2087 0271 2089 0272 2090 0273 2106 0275 2108 0276 2109 0277 2111 0278 2112 0279 2115 027B 2232 02AD 2234 02AE 2235 02AF 2238 02B1 2358 02EB 2364 02EF 2554 0355 2562 035C 2569 0362 2577 0369 360 047A 369 0480 468 04BD 597 0513 725 0556 794 0584 915 05CF 1116 05D9 1188 0601 1375 0673 1383 067B 1460 069D 1461 069E SCR3 030B 982 00B9 983 00BA 984 00BB 1122 00FC 1226 011A 1273 0128 1303 0130 1375 014C 1376 014D 1549 018F 1576 0191 1591 019A 1599 019B 1615 01A8 1623 01A9 1626 01AF 1655 01BF 1657 01C0 1758 01E4 1826 01F1 1829 01E1 1847 01F9 1851 01FB 1884 020F 1885 0210 1923 0205 1925 0224 1939 022F 1948 0233 2016 0249 2018 0250 2030 0259 2039 025F 2555 0356 2563 035D 2570 0363 2578 036A 473 04C1 599 0515 707 054B 728 0559 780 0576 1216 060A 1218 060C SCR4 040B 1014 00C9 1034 00D6 1035 00D7 1219 0114 1225 0119 1437 015F 1783 01E9 1936 022C 1938 022E 2029 0258 2032 025B 478 04C5 601 0517 644 0533 645 0534 650 0539 672 053F 673 0540 706 054A 712 054F 727 0558 733 055D 747 0563 758 0567 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 146 PPU3/REV 25 microcode | cross-reference table 853 05A1 862 05A5 877 05B1 905 05C5 1232 0615 SCR5 050B 962 00AF 997 00C4 1000 00C6 1015 00CA 1736 01DB 1739 01DD 1796 01EE 1931 0228 2024 0254 483 04C9 603 0519 852 05A0 863 05A6 876 05B0 907 05C7 1234 0617 SCR6 060B 1070 00E2 1071 00E3 1073 00E4 1079 00E8 1085 00EA 1089 00EC 1103 00F4 1104 00F5 488 04CD 605 051B 851 059F 864 05A7 875 05AF 911 05CB 1236 0619 SCR7 070B 1042 00DB 1873 0207 1954 0781 1987 023F 2458 0313 2460 0314 2466 0318 493 04D1 607 051D 849 059D 865 05A8 873 05AD 913 05CD 1238 061B SCR8 080B 1001 00C7 1201 010E 1202 010F 1509 017F 1511 0180 1794 01EC 1795 01ED 1836 01F5 1854 01FD 2081 026C 2082 026D 2192 0299 2195 029A 2196 029B 2210 02A3 2212 02A4 2298 02CE 2331 02E3 2412 02F7 2413 02F8 2414 02F9 2483 0323 2655 037D 2657 037E 2660 0380 2665 0382 2811 03A2 2843 03B8 2844 03B9 498 04D5 609 051F 1410 067F 1427 068D 1434 0693 SCR9 090B 1484 0175 1485 0176 2044 0770 2063 0260 2064 0261 2071 0264 2076 0267 2077 0268 2078 0269 3022 03DC 503 04D9 611 0521 1413 0682 SCRA 0A0B 1074 00E5 508 04DD 613 0523 1345 0661 1347 0663 1348 0664 1379 0677 SCRB 0B0B 1067 00E0 1824 01EF 2415 02FA 2503 032D 2543 034D 513 04E1 615 0525 SCRC 0C0B 2421 02FD 2434 0304 2435 0305 2439 0308 2441 0309 2451 030E 2456 0312 2464 0317 2468 031A 2532 0347 2670 0386 2672 0388 2674 038A 2676 038C 2678 038E 2682 0390 2683 0391 2816 03A6 2817 03A7 2819 03A9 2821 03AB 2823 03AD 2828 03B0 2829 03B1 2933 0080 2934 0081 2953 03C1 2958 03C8 2964 03CB 2970 03CC 2974 03CF 2976 03D1 2977 03D2 2990 03D5 518 04E5 617 0527 SCRD 0D0B 1045 00DD 1793 01EB 2445 030B 2453 0310 2482 0322 523 04E9 619 0529 SCRE 0E0B 2411 02F6 2478 0320 2485 0324 2494 0325 528 04ED 621 052B SCRF 0F0B 1047 00DE 1760 01E5 1792 01EA 533 04F1 623 052D 1125 05DF 1126 05E0 1262 0633 1263 0634 XLIT 010C 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 147 PPU3/REV 25 microcode | cross-reference table ADD 0003 968 00B5 971 00B8 983 00BA 1000 00C6 1014 00C9 1034 00D6 1035 00D7 1079 00E8 1085 00EA 1159 0100 1164 0102 1169 0104 1174 0106 1186 0108 1191 010A 1196 010C 1219 0114 1225 0119 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1271 0126 1290 012B 1401 0150 1406 0153 1422 015D 1439 0161 1503 017B 1519 0181 1520 0182 1579 0193 1593 019C 1602 01A1 1617 01AA 1625 01AE 1629 01B1 1646 01BD 1783 01E9 1792 01EA 1793 01EB 1824 01EF 1831 01F2 1853 01FC 1901 0215 1903 0217 1905 0219 1907 021B 1936 022C 1938 022E 1979 023A 1981 023B 1982 023C 2029 0258 2032 025B 2068 0262 2140 0282 2143 0284 2147 0287 2151 0289 2174 0294 2207 02A1 2244 02B3 2257 02B7 2261 02B9 2307 02D0 2415 02FA 2418 02CB 2434 0304 2435 0305 2482 0322 2485 0324 2529 030F 2646 0321 2648 0378 2649 0379 2745 0395 2747 0396 2787 037B 2789 039A 2803 039E 2804 039F 2838 03B4 2839 03B5 2933 0080 2958 03C8 2964 03CB 2974 03CF 2975 03D0 2989 03D4 3040 03EA 102 0427 104 0429 106 042B 108 042D 257 0467 266 046E 360 047A 361 047B 403 048A 412 0492 421 049A 430 04A2 554 04F5 564 04FA 644 0533 645 0534 650 0539 672 053F 673 0540 676 0543 706 054A 712 054F 716 0552 726 0557 727 0558 733 055D 736 0560 773 0572 774 0573 793 0583 794 0584 825 058E 826 058F 849 059D 851 059F 852 05A0 853 05A1 854 05A2 873 05AD 875 05AF 876 05B0 877 05B1 878 05B2 1119 05DB 1125 05DF 1153 05F1 1164 05F9 1191 0603 1240 061D 1241 061E 1242 061F 1243 0620 1246 0623 1262 0633 1460 069D AND 0006 924 0095 984 00BB 997 00C4 1031 00D4 1070 00E2 1071 00E3 1077 00E7 1089 00EC 1092 00EF 1101 00F3 1104 00F5 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1133 07D7 1134 07D8 1140 07DE 1141 07DF 1215 0113 1217 00ED 1253 011F 1261 0122 1277 07B0 1279 07B2 1281 07B4 1288 0129 1289 012A 1295 012C 1296 012D 1298 012E 1317 07AA 1338 0139 1347 013D 1350 013F 1355 0142 1366 0148 1370 0149 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1386 07BE 1392 07E4 1394 07E6 1405 0152 1410 0154 1414 0157 1421 015C 1440 0162 1447 0167 1473 0170 1477 0163 1480 0173 1497 0177 1500 0179 1506 017C 1540 0187 1653 01BE 1658 01C1 1678 01CD 1685 01D2 1727 01C7 1729 01D6 1730 01D7 1733 01D9 1735 01DA 1736 01DB 1739 01DD 1764 0798 1766 079A 1794 01EC 1865 0201 1881 020C 1882 020D 1913 021F 1914 0220 1923 0205 1926 0225 1987 023F 1998 0244 2000 0246 2013 024E 2016 0249 2019 0251 2045 0771 2046 0772 2047 0773 2048 0774 2108 0276 2109 0277 2121 027D 2135 027E 2138 0281 2150 0288 2163 028A 2168 028F 2172 0292 2175 0295 2189 0297 2198 027F 2204 029E 2232 02AD 2241 029F 2243 02B2 2251 02AB 2253 02B4 2260 02B8 2265 02BD 2282 02CA 2309 02D2 2326 02E1 2347 02E4 2349 02E5 2355 02E8 2357 02EA 2361 02EC 2363 02EE 2421 02FD 2430 0303 2432 02D3 2444 030A 2445 030B 2447 030C 2453 0310 2454 0311 2469 031B 2503 032D 2504 032E 2506 0330 2508 0332 2510 0334 2523 0341 2532 0347 2580 036B 2582 036D 2652 037A 2680 038F 2748 0397 2790 039B 2793 039D 2826 03AF 2836 03B3 2915 03C0 2934 0081 2953 03C1 2961 03C9 55 0409 110 042F 267 046F 351 0474 368 047F 402 0489 411 0491 420 0499 429 04A1 785 057B 791 0581 817 0589 818 058A 828 0591 1116 05D9 1165 05FA 1188 0601 1215 0609 1216 060A 1255 062C 1257 062E 1347 0663 1348 0664 1364 066B 1370 0671 1476 06AA IOR 0005 1016 00CB 1020 00CD 1023 00CF 1029 00D3 1039 00D9 1041 00DA 1042 00DB 1045 00DD 1068 00E1 1073 00E4 1103 00F4 1220 0115 1223 0117 1262 0123 1272 0127 1293 00FD 1312 07A5 1313 07A6 1316 07A9 1337 0138 1340 013A 1341 013B 1346 013C 1349 013E 1352 0140 1353 0141 1357 0143 1372 014A 1373 014B 1387 07BF 1395 07E7 1408 0137 1411 0155 1453 016B 1471 016F 1483 0174 1484 0175 1509 017F 1531 0183 1533 0184 1537 017D 1539 0186 1542 0188 1543 0189 1548 018E 1576 0191 1578 0192 1582 0195 1591 019A 1599 019B 1601 01A0 1605 01A3 1615 01A8 1623 01A9 1626 01AF 1628 01B0 1632 01B3 1660 01C2 1661 01C3 1664 01C4 1668 01C6 1670 01C8 1680 01CE 1695 0010 1732 01D8 1742 01DE 1753 01E0 1756 01E3 1768 079C 1826 01F1 1829 01E1 1836 01F5 1851 01FB 1867 0202 1870 0204 1873 0207 1878 020A 1884 020F 1910 021C 1916 0221 1925 0224 1929 0227 1954 0781 2006 0248 2018 0250 2022 0253 2044 0770 2050 0776 2073 0265 2076 0267 2081 026C 2087 0271 2089 0272 2105 0274 2106 0275 2112 0279 2114 027A 2120 027C 2144 0285 2191 0298 2192 0299 2231 02AC 2235 02AF 2237 02B0 2254 02B5 2330 02E2 2351 02E6 2352 02E7 2412 02F7 2439 0308 2441 0309 2451 030E 2456 0312 2458 0313 2483 0323 2505 032F 2507 0331 2511 0335 2525 0343 2543 034D 2584 036F 2654 037C 2655 037D 2658 037F 2661 0381 2665 0382 2666 0383 2792 039C 2807 03A1 2811 03A2 2812 03A3 2842 03B7 2843 03B8 2862 0060 2917 03C2 2956 03C7 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 148 PPU3/REV 25 microcode | cross-reference table 2963 03CA 2970 03CC 2976 03D1 51 0405 131 0437 141 043D 151 0443 161 0449 172 044D 182 0453 192 0459 202 045F 767 056C 772 0571 783 0579 784 057A 797 0587 819 058B 829 0592 831 0593 861 05A4 892 05B9 909 05C9 1219 060D 1295 0638 1299 063C 1303 0640 1307 0644 1310 0647 1312 0649 1314 064B 1316 064D 1319 064F 1320 0650 1321 0651 1322 0652 1323 0653 1325 0655 1327 0657 1329 0659 1345 0661 1379 0677 1475 06A9 1477 06AB NOP 1000 ONES 0007 932 009B 2268 02BE 2312 02D4 54 0408 72 0411 76 0415 80 0419 84 041D 838 0595 855 05A3 1107 05D2 OR 0005 RSUB 0001 1037 00D8 2165 028C 2173 0293 2262 02BA 2306 02CF 747 0563 1162 05F7 1422 068B SUB 0002 1028 00D2 1074 00E5 1083 00C5 1655 01BF 1990 023D 758 0567 XOR 0004 1160 0101 1170 0105 1206 0111 1270 0125 1400 014F 1437 015F 1455 016C 1942 0231 2063 0260 2071 0264 2077 0268 2090 0273 2195 029A 2210 02A3 2269 02BF 2298 02CE 2313 02D5 2331 02E3 2414 02F9 2448 030D 2708 0040 2709 0041 2710 0042 2711 0043 2740 0393 59 040D 254 0465 262 046B 352 0475 370 0481 400 0487 409 048F 418 0497 427 049F 458 04B5 463 04B9 468 04BD 473 04C1 478 04C5 483 04C9 488 04CD 493 04D1 498 04D5 503 04D9 508 04DD 513 04E1 518 04E5 523 04E9 528 04ED 533 04F1 562 04F8 565 04FB 593 050F 595 0511 597 0513 599 0515 601 0517 603 0519 605 051B 607 051D 609 051F 611 0521 613 0523 615 0525 617 0527 619 0529 621 052B 623 052D 707 054B 728 0559 769 056E 770 056F 771 0570 779 0575 780 0576 789 057F 847 059B 862 05A5 863 05A6 864 05A7 865 05A8 871 05AB 903 05C3 905 05C5 907 05C7 911 05CB 913 05CD 915 05CF 1108 05D3 1151 05EF 1160 05F5 1173 05FD 1217 060B 1224 060F 1232 0615 1234 0617 1236 0619 1238 061B 1244 0621 1248 0625 1250 0627 1256 062D 1260 0631 1294 0637 1298 063B 1302 063F 1306 0643 1311 0648 1313 064A 1315 064C 1317 064E 1324 0654 1326 0656 1328 0658 1330 065A 1375 0673 1383 067B 1410 067F 1411 0680 1413 0682 1427 068D 1434 0693 1458 069B ZERO 0000 929 0098 931 009A 934 009C 935 009D 941 00A1 942 00A2 943 00A3 944 00A4 949 00A7 950 00A8 951 00A9 955 00AB 965 00B2 986 00BC 987 00BD 988 00BE 989 00BF 991 00C0 993 00C1 994 00C2 1109 00F8 1385 07BD 1393 07E5 1450 0169 1452 016A 1671 01C9 1716 01D5 1928 0226 1941 0230 1953 0780 1961 0788 1996 0242 1997 0243 2002 0247 2074 0266 2085 0270 2146 0286 2164 028B 2256 02B6 2264 02BC 2668 0384 2814 03A4 2845 03BA 3020 03DA 3032 03E2 3033 03E3 3034 03E4 3035 03E5 3036 03E6 3037 03E7 3038 03E8 3039 03E9 48 0402 50 0404 74 0413 77 0416 82 041B 85 041E 98 0423 123 0433 1168 05FB 1342 065E 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 149 PPU3/REV 25 microcode | cross-reference table X 0001 1215 0113 1223 0117 1253 011F 1272 0127 1279 07B2 1281 07B4 1295 012C 1372 014A 1373 014B 1381 07B9 1383 07BB 1756 01E3 1766 079A 1865 0201 1882 020D 2454 0311 2523 0341 2580 036B 351 0474 368 047F 769 056E 770 056F 771 0570 818 058A 828 0591 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 150 PPU3/REV 25 microcode | cross-reference table LIT 0001 924 0095 983 00BA 984 00BB 997 00C4 1000 00C6 1014 00C9 1029 00D3 1034 00D6 1035 00D7 1039 00D9 1042 00DB 1045 00DD 1068 00E1 1070 00E2 1071 00E3 1073 00E4 1079 00E8 1085 00EA 1089 00EC 1092 00EF 1101 00F3 1103 00F4 1104 00F5 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1133 07D7 1134 07D8 1140 07DE 1141 07DF 1159 0100 1164 0102 1169 0104 1174 0106 1186 0108 1191 010A 1196 010C 1215 0113 1219 0114 1223 0117 1225 0119 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1253 011F 1279 07B2 1281 07B4 1290 012B 1405 0152 1406 0153 1422 015D 1437 015F 1440 0162 1447 0167 1477 0163 1506 017C 1531 0183 1537 017D 1542 0188 1576 0191 1582 0195 1591 019A 1599 019B 1605 01A3 1615 01A8 1623 01A9 1626 01AF 1632 01B3 1668 01C6 1678 01CD 1736 01DB 1739 01DD 1783 01E9 1792 01EA 1793 01EB 1794 01EC 1824 01EF 1826 01F1 1829 01E1 1836 01F5 1851 01FB 1867 0202 1873 0207 1882 020D 1884 020F 1910 021C 1916 0221 1923 0205 1925 0224 1936 022C 1938 022E 1942 0231 1954 0781 1987 023F 2006 0248 2016 0249 2018 0250 2029 0258 2032 025B 2046 0772 2047 0773 2050 0776 2068 0262 2106 0275 2108 0276 2109 0277 2112 0279 2144 0285 2150 0288 2151 0289 2163 028A 2174 0294 2207 02A1 2232 02AD 2235 02AF 2253 02B4 2254 02B5 2260 02B8 2261 02B9 2307 02D0 2351 02E6 2352 02E7 2355 02E8 2357 02EA 2361 02EC 2363 02EE 2412 02F7 2414 02F9 2415 02FA 2421 02FD 2434 0304 2435 0305 2439 0308 2441 0309 2445 030B 2451 030E 2453 0310 2456 0312 2458 0313 2482 0322 2483 0323 2485 0324 2503 032D 2523 0341 2525 0343 2529 030F 2532 0347 2543 034D 2933 0080 2934 0081 2953 03C1 2958 03C8 2964 03CB 2970 03CC 2974 03CF 2976 03D1 3040 03EA 51 0405 55 0409 102 0427 104 0429 106 042B 108 042D 110 042F 131 0437 141 043D 151 0443 161 0449 172 044D 182 0453 192 0459 202 045F 257 0467 266 046E 267 046F 269 0471 351 0474 360 047A 361 047B 402 0489 403 048A 411 0491 412 0492 565 04FB 650 0539 726 0557 767 056C 771 0570 772 0571 773 0572 774 0573 783 0579 784 057A 785 057B 789 057F 791 0581 794 0584 797 0587 817 0589 818 058A 826 058F 847 059B 862 05A5 863 05A6 864 05A7 865 05A8 871 05AB 892 05B9 909 05C9 1108 05D3 1116 05D9 1119 05DB 1125 05DF 1151 05EF 1160 05F5 1173 05FD 1188 0601 1191 0603 1216 060A 1224 060F 1255 062C 1262 0633 1345 0661 1347 0663 1348 0664 1375 0673 1379 0677 1383 067B 1458 069B 1460 069D 1475 06A9 1476 06AA 1477 06AB NOP 0001 RAM 0000 968 00B5 971 00B8 1016 00CB 1020 00CD 1023 00CF 1026 00D1 1028 00D2 1031 00D4 1037 00D8 1041 00DA 1074 00E5 1077 00E7 1080 00E9 1083 00C5 1091 00EE 1106 00F6 1121 00FB 1160 0101 1170 0105 1206 0111 1217 00ED 1220 0115 1224 0118 1249 011B 1251 011D 1261 0122 1262 0123 1270 0125 1271 0126 1272 0127 1277 07B0 1288 0129 1289 012A 1293 00FD 1295 012C 1296 012D 1298 012E 1310 07A3 1312 07A5 1313 07A6 1316 07A9 1317 07AA 1319 07AC 1328 0132 1332 0135 1337 0138 1338 0139 1340 013A 1341 013B 1346 013C 1347 013D 1349 013E 1350 013F 1352 0140 1353 0141 1355 0142 1357 0143 1362 0145 1364 0146 1365 0147 1366 0148 1370 0149 1372 014A 1373 014B 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1386 07BE 1387 07BF 1392 07E4 1394 07E6 1395 07E7 1400 014F 1401 0150 1408 0137 1410 0154 1411 0155 1413 0156 1414 0157 1421 015C 1438 0160 1439 0161 1444 0165 1453 016B 1455 016C 1456 016D 1471 016F 1473 0170 1480 0173 1483 0174 1484 0175 1497 0177 1500 0179 1503 017B 1509 017F 1519 0181 1520 0182 1533 0184 1539 0186 1540 0187 1543 0189 1545 018B 1548 018E 1578 0192 1579 0193 1593 019C 1601 01A0 1602 01A1 1608 01A5 1617 01AA 1625 01AE 1628 01B0 1629 01B1 1635 01B5 1641 01B8 1642 01B9 1645 01BC 1646 01BD 1653 01BE 1655 01BF 1658 01C1 1660 01C2 1661 01C3 1664 01C4 1670 01C8 1680 01CE 1685 01D2 1695 0010 1727 01C7 1729 01D6 1730 01D7 1732 01D8 1733 01D9 1735 01DA 1742 01DE 1753 01E0 1756 01E3 1764 0798 1766 079A 1768 079C 1831 01F2 1846 01F8 1853 01FC 1865 0201 1868 0203 1870 0204 1878 020A 1881 020C 1889 07E8 1890 07E9 1891 07EA 1892 07EB 1896 0211 1897 0212 1898 0213 1899 0214 1901 0215 1903 0217 1905 0219 1907 021B 1911 021D 1912 021E 1913 021F 1914 0220 1926 0225 1929 0227 1955 0782 1956 0783 1957 0784 1958 0785 1959 0786 1960 0787 1972 0234 1973 0235 1974 0236 1975 0237 1976 0238 1977 0239 1979 023A 1981 023B 1982 023C 1986 023E 1990 023D 1992 0240 1993 0241 1998 0244 1999 0245 2000 0246 2009 024B 2011 024C 2012 024D 2013 024E 2019 0251 2022 0253 2044 0770 2045 0771 2048 0774 2063 0260 2071 0264 2073 0265 2076 0267 2077 0268 2081 026C 2087 0271 2089 0272 2090 0273 2105 0274 2114 027A 2120 027C 2121 027D 2135 027E 2138 0281 2140 0282 2143 0284 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 151 PPU3/REV 25 microcode | cross-reference table 2147 0287 2165 028C 2168 028F 2172 0292 2173 0293 2175 0295 2189 0297 2191 0298 2192 0299 2195 029A 2198 027F 2204 029E 2210 02A3 2231 02AC 2237 02B0 2241 029F 2243 02B2 2244 02B3 2251 02AB 2257 02B7 2262 02BA 2265 02BD 2269 02BF 2272 02C0 2275 02C3 2277 02C5 2279 02C7 2281 02C9 2282 02CA 2298 02CE 2306 02CF 2309 02D2 2313 02D5 2315 02D6 2317 02D8 2319 02DA 2321 02DC 2323 02DE 2326 02E1 2330 02E2 2331 02E3 2347 02E4 2349 02E5 2356 02E9 2362 02ED 2418 02CB 2430 0303 2432 02D3 2444 030A 2447 030C 2448 030D 2454 0311 2467 0319 2469 031B 2504 032E 2505 032F 2506 0330 2507 0331 2508 0332 2510 0334 2511 0335 2512 0336 2514 0338 2516 033A 2518 033C 2580 036B 2582 036D 2584 036F 2585 0370 2587 0371 2588 0372 2589 0373 2620 0030 2621 0031 2622 0032 2623 0033 2641 0374 2643 0376 2646 0321 2648 0378 2649 0379 2652 037A 2654 037C 2655 037D 2658 037F 2661 0381 2665 0382 2666 0383 2669 0385 2671 0387 2673 0389 2675 038B 2677 038D 2680 038F 2708 0040 2709 0041 2710 0042 2711 0043 2729 0392 2740 0393 2745 0395 2747 0396 2748 0397 2764 0050 2765 0051 2766 0052 2767 0053 2784 0398 2785 0399 2787 037B 2789 039A 2790 039B 2792 039C 2793 039D 2803 039E 2804 039F 2807 03A1 2811 03A2 2812 03A3 2815 03A5 2818 03A8 2820 03AA 2822 03AC 2824 03AE 2826 03AF 2836 03B3 2838 03B4 2839 03B5 2842 03B7 2843 03B8 2848 03BC 2862 0060 2915 03C0 2917 03C2 2956 03C7 2961 03C9 2963 03CA 2975 03D0 2989 03D4 59 040D 254 0465 262 046B 352 0475 368 047F 370 0481 400 0487 409 048F 417 0496 418 0497 420 0499 421 049A 426 049E 427 049F 429 04A1 430 04A2 458 04B5 463 04B9 468 04BD 473 04C1 478 04C5 483 04C9 488 04CD 493 04D1 498 04D5 503 04D9 508 04DD 513 04E1 518 04E5 523 04E9 528 04ED 533 04F1 554 04F5 562 04F8 564 04FA 573 04FE 574 04FF 575 0500 576 0501 577 0502 578 0503 579 0504 580 0505 581 0506 582 0507 583 0508 584 0509 585 050A 586 050B 587 050C 588 050D 593 050F 595 0511 597 0513 599 0515 601 0517 603 0519 605 051B 607 051D 609 051F 611 0521 613 0523 615 0525 617 0527 619 0529 621 052B 623 052D 644 0533 645 0534 672 053F 673 0540 676 0543 706 054A 707 054B 711 054E 712 054F 714 0551 716 0552 727 0558 728 0559 732 055C 733 055D 735 055F 736 0560 747 0563 758 0567 769 056E 770 056F 779 0575 780 0576 792 0582 793 0583 819 058B 825 058E 827 0590 828 0591 829 0592 831 0593 849 059D 851 059F 852 05A0 853 05A1 854 05A2 861 05A4 873 05AD 875 05AF 876 05B0 877 05B1 878 05B2 886 05B3 887 05B4 888 05B5 889 05B6 890 05B7 903 05C3 905 05C5 907 05C7 911 05CB 913 05CD 915 05CF 1153 05F1 1154 05F2 1162 05F7 1164 05F9 1165 05FA 1215 0609 1217 060B 1219 060D 1232 0615 1234 0617 1236 0619 1238 061B 1240 061D 1241 061E 1242 061F 1243 0620 1244 0621 1246 0623 1248 0625 1250 0627 1256 062D 1257 062E 1260 0631 1294 0637 1295 0638 1298 063B 1299 063C 1302 063F 1303 0640 1306 0643 1307 0644 1310 0647 1311 0648 1312 0649 1313 064A 1314 064B 1315 064C 1316 064D 1317 064E 1319 064F 1320 0650 1321 0651 1322 0652 1323 0653 1324 0654 1325 0655 1326 0656 1327 0657 1328 0658 1329 0659 1330 065A 1364 066B 1366 066D 1367 066E 1368 066F 1369 0670 1370 0671 1410 067F 1411 0680 1413 0682 1422 068B 1427 068D 1434 0693 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 152 PPU3/REV 25 microcode | cross-reference table CSOUT 0002 1261 0122 1399 014E 1416 0158 1417 0159 1932 0229 2025 0255 CSSFO 0000 1155 00FF 1165 0103 1197 010D DPDIR 0016 963 00B0 1675 01CB 2079 026A 2135 027E 1467 06A1 DPOE 0012 934 009C 1485 0176 2064 0261 2078 0269 3012 03D8 3022 03DC 1163 05F8 DPOUT 000B 2863 0061 2881 03BD 2882 03BE 2883 03BF 2896 0071 2918 03C3 2920 03C4 2971 03CD 2973 03CE 2981 076D 2982 076E 2983 076F 2987 03D3 2995 0741 2996 0742 2997 0743 3001 03D6 1416 0685 1417 0686 1418 0687 1419 0688 DPRST 0003 964 00B1 969 00B6 1676 01CC 1684 01D1 2080 026B 2084 026F 2137 0280 2138 0281 2169 0290 2176 0296 1468 06A2 1472 06A6 FPINT 0004 IADR 0009 947 00A6 952 00AA 1547 018D 1715 01D4 2156 07EC 2157 07ED 2158 07EE 2159 07EF 2291 0760 2292 0761 2293 0762 2294 0763 2600 0764 2601 0765 2602 0766 2603 0767 2695 0750 2696 0751 2697 0752 2698 0753 2699 0754 2700 0755 2701 0756 2702 0757 2733 0768 2734 0769 2735 076A 2736 076B 2741 0394 2806 03A0 2835 03B2 2841 03B6 2921 03C5 3003 03D7 1129 05E2 1130 05E3 1131 05E4 1132 05E5 1133 05E6 1134 05E7 1135 05E8 1136 05E9 IMR 0017 1001 00C7 1201 010E 1202 010F 1511 0180 1795 01ED 1847 01F9 1854 01FD 2082 026D 2196 029B 2212 02A4 2413 02F8 2657 037E 2660 0380 2844 03B9 3042 03EB 1272 06F0 1273 06F1 1274 06F2 1275 06F3 1280 06F8 1281 06F9 1282 06FA 1283 06FB 1296 0639 1300 063D 1304 0641 1308 0645 1340 065C 1409 067E 1430 0690 1433 0692 INDX1 0013 930 0099 937 009E 962 00AF 1015 00CA 1047 00DE 1760 01E5 1796 01EE 1876 0209 1883 020E 1918 0222 1931 0228 2014 024F 2024 0254 2478 0320 2494 0325 2549 0350 2557 0357 2565 035E 2572 0364 3025 03DE 3030 03E1 47 0401 59 040D 124 0434 134 0439 144 043F 154 0445 176 0450 186 0456 196 045C 787 057D 1202 0606 INDX2 000D 2411 02F6 2466 0318 2502 032C 2521 033F 2550 0351 2558 0358 2573 0365 49 0403 125 0435 135 043A 145 0440 155 0446 175 044F 185 0455 195 045B 206 0461 269 0471 535 04F3 1111 05D6 1121 05DC 1126 05E0 1193 0604 1263 0634 1461 069E NOP 001F RAM 0001 931 009A 932 009B 938 009F 939 00A0 965 00B2 966 00B3 967 00B4 970 00B7 975 07E0 976 07E1 977 07E2 978 07E3 982 00B9 986 00BC 987 00BD 988 00BE 989 00BF 991 00C0 993 00C1 994 00C2 995 00C3 1037 00D8 1041 00DA 1067 00E0 1086 00EB 1160 0101 1170 0105 1206 0111 1219 0114 1220 0115 1222 0116 1223 0117 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1250 011C 1252 011E 1253 011F 1257 0120 1258 0121 1262 0123 1270 0125 1271 0126 1278 07B1 1279 07B2 1280 07B3 1281 07B4 1288 0129 1290 012B 1298 012E 1312 07A5 1327 0131 1329 0133 1331 0134 1333 0136 1337 0138 1340 013A 1341 013B 1346 013C 1349 013E 1352 0140 1353 0141 1355 0142 1357 0143 1366 0148 1387 07BF 1395 07E7 1400 014F 1401 0150 1406 0153 1410 0154 1419 015A 1420 015B 1422 015D 1424 015E 1437 015F 1446 0166 1473 0170 1480 0173 1483 0174 1519 0181 1520 0182 1533 0184 1539 0186 1563 0791 1564 0792 1565 0793 1566 0794 1567 0795 1568 0796 1569 0797 1578 0192 1579 0193 1585 0197 1593 019C 1594 019D 1601 01A0 1602 01A1 1610 01A6 1617 01AA 1618 01AB 1625 01AE 1628 01B0 1629 01B1 1638 01B7 1646 01BD 1657 01C0 1658 01C1 1660 01C2 1661 01C3 1664 01C4 1670 01C8 1671 01C9 1680 01CE 1685 01D2 1695 0010 1732 01D8 1736 01DB 1739 01DD 1831 01F2 1836 01F5 1840 01F7 1848 01FA 1853 01FC 1867 0202 1872 0206 1875 0208 1880 020B 1902 0216 1904 0218 1906 021A 1910 021C 1934 022A 1935 022B 1936 022C 1937 022D 1939 022F 1987 023F 1998 0244 2000 0246 2027 0256 2028 0257 2029 0258 2030 0259 2031 025A 2033 025C 2045 0771 2049 0775 2051 0777 2073 0265 2074 0266 2085 0270 2087 0271 2089 0272 2090 0273 2105 0274 2111 0278 2114 027A 2115 027B 2120 027C 2121 027D 2164 028B 2165 028C 2166 028D 2167 028E 2168 028F 2171 0291 2173 0293 2174 0294 2175 0295 2191 0298 2231 02AC 2234 02AE 2237 02B0 2238 02B1 2256 02B6 2262 02BA 2263 02BB 2264 02BC 2268 02BE 2269 02BF 2273 02C1 2274 02C2 2276 02C4 2278 02C6 2280 02C8 2285 02CC 2286 02CD 2306 02CF 2307 02D0 2308 02D1 2312 02D4 2313 02D5 2316 02D7 2318 02D9 2320 02DB 2322 02DD 2324 02DF 2325 02E0 2330 02E2 2355 02E8 2357 02EA 2358 02EB 2361 02EC 2363 02EE 2364 02EF 2416 02FB 2418 02CB 2424 02FF 2426 0300 2427 0301 2428 0302 2437 0306 2438 0307 2469 031B 2495 0326 2496 0327 2497 0328 2498 0329 2499 032A 2500 032B 2503 032D 2505 032F 2507 0331 2509 0333 2511 0335 2513 0337 2515 0339 2517 033B 2519 033D 2524 0342 2535 0349 2537 034A 2538 034B 2539 034C 2552 0353 2553 0354 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 153 PPU3/REV 25 microcode | cross-reference table 2554 0355 2555 0356 2560 035A 2561 035B 2562 035C 2563 035D 2567 0360 2568 0361 2569 0362 2570 0363 2575 0367 2576 0368 2577 0369 2578 036A 2581 036C 2583 036E 2646 0321 2648 0378 2649 0379 2658 037F 2661 0381 2666 0383 2668 0384 2670 0386 2672 0388 2674 038A 2676 038C 2678 038E 2682 0390 2683 0391 2745 0395 2747 0396 2787 037B 2789 039A 2803 039E 2804 039F 2812 03A3 2814 03A4 2816 03A6 2817 03A7 2819 03A9 2821 03AB 2823 03AD 2828 03B0 2829 03B1 2838 03B4 2839 03B5 2842 03B7 2845 03BA 2846 03BB 2862 0060 2895 0070 2917 03C2 2955 03C6 2956 03C7 2963 03CA 2975 03D0 2989 03D4 3032 03E2 3033 03E3 3034 03E4 3035 03E5 3036 03E6 3037 03E7 3038 03E8 3039 03E9 58 040C 61 040F 253 0464 261 046A 316 0700 317 0701 318 0702 319 0703 320 0704 321 0705 322 0706 323 0707 324 0708 325 0709 326 070A 327 070B 328 070C 329 070D 330 070E 331 070F 351 0474 367 047E 369 0480 398 0485 399 0486 407 048D 408 048E 415 0494 421 049A 424 049C 430 04A2 457 04B4 462 04B8 467 04BC 472 04C0 477 04C4 482 04C8 487 04CC 492 04D0 497 04D4 502 04D8 507 04DC 512 04E0 517 04E4 522 04E8 527 04EC 532 04F0 549 04F4 554 04F5 561 04F7 563 04F9 565 04FB 643 0532 644 0533 645 0534 671 053E 672 053F 673 0540 676 0543 704 0548 706 054A 712 054F 725 0556 727 0558 733 055D 746 0562 757 0566 767 056C 768 056D 771 0570 791 0581 796 0586 818 058A 820 058C 825 058E 829 0592 831 0593 837 0594 839 0596 840 0597 841 0598 842 0599 849 059D 851 059F 852 05A0 853 05A1 854 05A2 861 05A4 862 05A5 863 05A6 864 05A7 865 05A8 873 05AD 875 05AF 876 05B0 877 05B1 878 05B2 1124 05DE 1128 05E1 1140 05EA 1141 05EB 1142 05EC 1143 05ED 1145 05EE 1153 05F1 1157 05F3 1164 05F9 1203 0607 1215 0609 1216 060A 1219 060D 1240 061D 1241 061E 1242 061F 1243 0620 1246 0623 1249 0626 1252 0629 1295 0638 1297 063A 1299 063C 1301 063E 1303 0640 1305 0642 1307 0644 1309 0646 1310 0647 1311 0648 1312 0649 1313 064A 1314 064B 1315 064C 1316 064D 1317 064E 1319 064F 1320 0650 1321 0651 1322 0652 1323 0653 1324 0654 1325 0655 1326 0656 1327 0657 1328 0658 1329 0659 1330 065A 1422 068B SBCB 0015 943 00A3 1365 0147 1455 016C 1456 016D 1546 018C 1645 01BC 1782 01E8 2464 0317 2468 031A 2526 0344 2545 034E 2643 0376 2740 0393 2784 0398 48 0402 890 05B7 1365 066C 1370 0671 1440 0699 SBHC 0010 1832 01F3 1839 01F6 2460 0314 2461 0315 2620 0030 2621 0031 2622 0032 2623 0033 2708 0040 2709 0041 2710 0042 2711 0043 2764 0050 2765 0051 2766 0052 2767 0053 886 05B3 1366 066D SBHD 000E 1643 01BA 2642 0375 888 05B5 1368 066F SBINT 0006 942 00A2 1743 01DF 1996 0242 2470 031C SBLC 0011 1364 0146 1452 016A 1545 018B 1642 01B9 1781 01E7 2463 0316 2467 0319 2641 0374 2729 0392 2785 0399 887 05B4 1367 066E SBLD 000F 1644 01BB 2644 0377 889 05B6 1369 0670 SBRFI 000A 941 00A1 2376 0020 2377 0021 2378 0022 2379 0023 2380 0024 2381 0025 2382 0026 2383 0027 838 0595 850 059E 855 05A3 1342 065E 1343 065F SBRST 0007 927 0097 2520 033E 3019 03D9 46 0400 1438 0697 SCR0 0005 926 0096 1026 00D1 1028 00D2 1032 00D5 1048 00DF 1094 00F0 1095 00F1 1098 00F2 1107 00F7 1120 00FA 1214 0112 1215 0113 1269 0124 1289 012A 1310 07A3 1319 07AC 1328 0132 1332 0135 1362 0145 1380 07B8 1381 07B9 1382 07BA 1383 07BB 1384 07BC 1385 07BD 1386 07BE 1392 07E4 1393 07E5 1394 07E6 1404 0151 1405 0152 1413 0156 1421 015C 1438 0160 1439 0161 1444 0165 1450 0169 1474 0171 1499 0178 1534 0185 1543 0189 1581 0194 1604 01A2 1631 01B2 1641 01B8 1666 01C5 1674 01CA 1697 0012 1698 0013 1699 0014 1700 0015 1701 0016 1702 0017 1703 0018 1704 0019 1705 001A 1706 001B 1707 001C 1708 001D 1709 001E 1710 001F 1716 01D5 1764 0798 1766 079A 1858 01FF 1865 0201 1870 0204 1878 020A 1882 020D 1889 07E8 1890 07E9 1891 07EA 1892 07EB 1901 0215 1903 0217 1905 0219 1907 021B 1914 0220 1928 0226 1955 0782 1956 0783 1957 0784 1958 0785 1959 0786 1960 0787 1961 0788 1999 0245 2006 0248 2013 024E 2066 025D 2068 0262 2140 0282 2143 0284 2146 0286 2147 0287 2150 0288 2151 0289 2163 028A 2172 0292 2201 029D 2207 02A1 2243 02B2 2244 02B3 2253 02B4 2257 02B7 2260 02B8 2261 02B9 2272 02C0 2275 02C3 2277 02C5 2279 02C7 2281 02C9 2315 02D6 2317 02D8 2319 02DA 2321 02DC 2323 02DE 2347 02E4 2351 02E6 2352 02E7 2356 02E9 2362 02ED 2384 0028 2385 0029 2386 002A 2387 002B 2388 002C 2389 002D 2390 002E 2391 002F 2420 02FC 2504 032E 2506 0330 2508 0332 2510 0334 2512 0336 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 154 PPU3/REV 25 microcode | cross-reference table 2514 0338 2516 033A 2518 033C 2522 0340 2523 0341 2525 0343 2527 0345 2529 030F 2580 036B 2584 036F 2585 0370 2628 0038 2629 0039 2630 003A 2631 003B 2632 003C 2633 003D 2634 003E 2635 003F 2716 0048 2717 0049 2718 004A 2719 004B 2720 004C 2721 004D 2722 004E 2723 004F 2772 0058 2773 0059 2774 005A 2775 005B 2776 005C 2777 005D 2778 005E 2779 005F 2864 0062 2865 0063 2866 0064 2867 0065 2868 0066 2869 0067 2870 0068 2871 0069 2872 006A 2873 006B 2874 006C 2875 006D 2876 006E 2877 006F 2897 0072 2898 0073 2899 0074 2900 0075 2901 0076 2902 0077 2903 0078 2904 0079 2905 007A 2906 007B 2907 007C 2908 007D 2909 007E 2910 007F 2935 0082 2936 0083 2937 0084 2938 0085 2939 0086 2940 0087 2941 0088 2942 0089 2943 008A 2944 008B 2945 008C 2946 008D 2947 008E 2948 008F 3024 03DD 3040 03EA 50 0404 54 0408 60 040E 73 0412 75 0414 78 0417 79 0418 81 041A 83 041C 86 041F 87 0420 98 0423 102 0427 103 0428 104 0429 105 042A 106 042B 107 042C 108 042D 109 042E 110 042F 111 0430 123 0433 132 0438 142 043E 152 0444 162 044A 173 044E 183 0454 193 045A 203 0460 211 0745 212 0746 213 0747 219 0748 221 074A 222 074B 228 074C 229 074D 231 074F 237 0730 238 0731 239 0732 255 0466 263 046C 274 0720 275 0721 276 0722 277 0723 278 0724 279 0725 280 0726 281 0727 282 0728 283 0729 284 072A 285 072B 286 072C 287 072D 288 072E 289 072F 295 0710 296 0711 297 0712 298 0713 299 0714 300 0715 301 0716 302 0717 303 0718 304 0719 305 071A 306 071B 307 071C 308 071D 309 071E 310 071F 349 0472 353 0476 368 047F 372 0483 397 0484 401 0488 403 048A 406 048C 410 0490 412 0492 416 0495 417 0496 419 0498 425 049D 426 049E 428 04A0 440 04A4 459 04B6 464 04BA 469 04BE 474 04C2 479 04C6 484 04CA 489 04CE 494 04D2 499 04D6 504 04DA 509 04DE 514 04E2 519 04E6 524 04EA 529 04EE 534 04F2 562 04F8 564 04FA 573 04FE 594 0510 596 0512 598 0514 600 0516 602 0518 604 051A 606 051C 608 051E 610 0520 612 0522 614 0524 616 0526 618 0528 620 052A 622 052C 624 052E 646 0535 647 0536 651 053A 674 0541 675 0542 677 0544 709 054D 730 055B 748 0564 759 0568 765 056A 773 0572 774 0573 781 0577 782 0578 792 0582 793 0583 795 0585 797 0587 816 0588 817 0589 819 058B 827 0590 828 0591 891 05B8 893 05BA 894 05BB 904 05C4 906 05C6 908 05C8 910 05CA 912 05CC 914 05CE 916 05D0 917 05D1 1118 05DA 1190 0602 1194 0605 1214 0608 1233 0616 1235 0618 1237 061A 1239 061C 1254 062B 1255 062C 1256 062D 1258 062F 1261 0632 1349 0665 1384 067C 1412 0681 1415 0684 1428 068E 1429 068F 1435 0694 1436 0695 1474 06A8 1478 06AC 1479 06AD SCR1 0105 956 00AC 968 00B5 1080 00E9 1119 00F9 1159 0100 1164 0102 1169 0104 1174 0106 1186 0108 1191 010A 1196 010C 1503 017B 1540 0187 1542 0188 1587 0198 1608 01A5 1635 01B5 1696 0011 1896 0211 1897 0212 1898 0213 1899 0214 1913 021F 1941 0230 1972 0234 1973 0235 1974 0236 1975 0237 1976 0238 1977 0239 1979 023A 1981 023B 1982 023C 1986 023E 1992 0240 1993 0241 2002 0247 2011 024C 2582 036D 2587 0371 252 0463 257 0467 260 0469 266 046E 350 0473 355 0477 361 047B 441 04A5 574 04FF 670 053D 766 056B 789 057F 821 058D 826 058F 898 05BF 1107 05D2 1110 05D5 1119 05DB 1168 05FB 1183 05FF 1191 0603 SCR2 0205 957 00AD 971 00B8 1249 011B 1251 011D 1637 01B6 1714 01D3 1868 0203 1911 021D 1942 0231 2012 024D 2046 0772 2047 0773 2588 0372 356 0478 360 047A 442 04A6 575 0500 722 0553 736 0560 790 0580 794 0584 901 05C2 1115 05D8 1116 05D9 1187 0600 1188 0601 1341 065D 1362 0669 1363 066A 1414 0683 1421 068A 1431 0691 1437 0696 1457 069A 1460 069D SCR3 0305 958 00AE 983 00BA 984 00BB 1121 00FB 1130 07D4 1131 07D5 1132 07D6 1135 07D9 1136 07DA 1137 07DB 1224 0118 1272 0127 1282 07B5 1283 07B6 1284 07B7 1295 012C 1307 07A0 1308 07A1 1309 07A2 1311 07A4 1314 07A7 1315 07A8 1318 07AB 1320 07AD 1321 07AE 1322 07AF 1372 014A 1373 014B 1548 018E 1562 0790 1574 0190 1589 0199 1597 019F 1613 01A7 1621 01AD 1653 01BE 1655 01BF 1756 01E3 1825 01F0 1835 01F4 1846 01F8 1857 01FE 1881 020C 1884 020F 1912 021E 1953 0780 2009 024B 2589 0373 2980 076C 2994 0740 443 04A7 576 0501 703 0547 714 0551 723 0554 735 055F 769 056E 770 056F 1154 05F2 1165 05FA SCR4 0405 1014 00C9 1034 00D6 1035 00D7 1225 0119 1783 01E9 1938 022E 2032 025B 444 04A8 577 0502 642 0531 649 0538 650 0539 669 053C 702 0546 711 054E 716 0552 724 0555 732 055C 745 0561 747 0563 756 0565 758 0567 896 05BD 1227 0611 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 155 PPU3/REV 25 microcode | cross-reference table SCR5 0505 955 00AB 1000 00C6 1003 00C8 1106 00F6 445 04A9 578 0503 897 05BE 1228 0612 SCR6 0605 929 0098 1070 00E2 1073 00E4 1076 00E6 1079 00E8 1085 00EA 1103 00F4 3020 03DA 446 04AA 579 0504 899 05C0 1229 0613 SCR7 0705 944 00A4 1742 01DE 1997 0243 2471 031D 447 04AB 580 0505 900 05C1 1230 0614 SCR8 0805 945 00A5 1509 017F 1794 01EC 2081 026C 2192 0299 2195 029A 2210 02A3 2298 02CE 2331 02E3 2412 02F7 2414 02F9 2483 0323 2655 037D 2665 0382 2811 03A2 2843 03B8 17 0001 18 0002 19 0003 20 0004 21 0005 22 0006 23 0007 24 0008 25 0009 26 000A 27 000B 28 000C 29 000D 30 000E 31 000F 448 04AC 581 0506 SCR9 0905 935 009D 1484 0175 2044 0770 2063 0260 2071 0264 2076 0267 2077 0268 3021 03DB 449 04AD 582 0507 1401 0734 1402 0735 1403 0736 1404 0737 SCRA 0A05 1091 00EE 450 04AE 583 0508 1344 0660 1346 0662 1378 0676 1380 0678 SCRB 0B05 1109 00F8 1755 01E2 1765 0799 1767 079B 1770 079E 1771 079F 1824 01EF 1864 0200 1919 0223 1947 0232 1962 0789 1963 078A 1964 078B 1965 078C 1966 078D 1967 078E 1968 078F 2008 024A 2038 025E 2053 0779 2054 077A 2055 077B 2056 077C 2057 077D 2058 077E 2059 077F 2366 02F0 2395 02F1 2396 02F2 2397 02F3 2398 02F4 2399 02F5 2415 02FA 2475 031E 2476 031F 451 04AF 584 0509 SCRC 0C05 2423 02FE 2430 0303 2434 0304 2435 0305 2448 030D 2454 0311 2456 0312 2534 0348 2669 0385 2671 0387 2673 0389 2675 038B 2677 038D 2815 03A5 2818 03A8 2820 03AA 2822 03AC 2824 03AE 2848 03BC 2933 0080 2958 03C8 2964 03CB 2970 03CC 2974 03CF 2976 03D1 452 04B0 585 050A SCRD 0D05 949 00A7 1793 01EB 2482 0322 453 04B1 586 050B SCRE 0E05 950 00A8 2485 0324 454 04B2 587 050C SCRF 0F05 951 00A9 1792 01EA 455 04B3 588 050D 1122 05DD 1125 05DF 1253 062A 1262 0633 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 156 PPU3/REV 25 microcode | cross-reference table H 0002 1220 0115 1233 07C3 1235 07C5 1236 07C6 1239 07C9 1240 07CA 1242 07CC 1271 0126 1279 07B2 1281 07B4 1401 0150 1587 0198 1637 01B6 2585 0370 2981 076D 2987 03D3 2995 0741 3001 03D6 408 048E 426 049E 767 056C 769 056E L 0001 1076 00E6 1079 00E8 1085 00EA 1222 0116 1253 011F 1257 0120 1258 0121 1270 0125 1278 07B1 1280 07B3 1400 014F 1422 015D 1657 01C0 2356 02E9 2362 02ED 399 0486 417 0496 768 056D 770 056F 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 157 PPU3/REV 25 microcode | cross-reference table P 0001 1094 00F0 1095 00F1 1109 00F8 1303 0130 1544 018A 1581 0194 1604 01A2 1631 01B2 1697 0012 1698 0013 1699 0014 1700 0015 1701 0016 1702 0017 1703 0018 1704 0019 1705 001A 1706 001B 1707 001C 1708 001D 1709 001E 1710 001F 1760 01E5 1858 01FF 1872 0206 1875 0208 2074 0266 2137 0280 2192 0299 2217 02A9 2384 0028 2385 0029 2386 002A 2387 002B 2388 002C 2389 002D 2390 002E 2391 002F 2420 02FC 2478 0320 2628 0038 2629 0039 2630 003A 2631 003B 2632 003C 2633 003D 2634 003E 2635 003F 2716 0048 2717 0049 2718 004A 2719 004B 2720 004C 2721 004D 2722 004E 2723 004F 2772 0058 2773 0059 2774 005A 2775 005B 2776 005C 2777 005D 2778 005E 2779 005F 2864 0062 2865 0063 2866 0064 2867 0065 2868 0066 2869 0067 2870 0068 2871 0069 2872 006A 2873 006B 2874 006C 2875 006D 2876 006E 2877 006F 2897 0072 2898 0073 2899 0074 2900 0075 2901 0076 2902 0077 2903 0078 2904 0079 2905 007A 2906 007B 2907 007C 2908 007D 2909 007E 2910 007F 2935 0082 2936 0083 2937 0084 2938 0085 2939 0086 2940 0087 2941 0088 2942 0089 2943 008A 2944 008B 2945 008C 2946 008D 2947 008E 2948 008F 98 0423 99 0424 100 0425 101 0426 126 0436 136 043B 146 0441 156 0447 167 044B 177 0451 187 0457 197 045D 253 0464 261 046A 362 047C 555 04F6 566 04FC 768 056D 838 0595 855 05A3 866 05A9 877 05B1 1107 05D2 1154 05F2 1159 05F4 1168 05FB 1218 060C 1276 06F4 1277 06F5 1278 06F6 1279 06F7 1284 06FC 1285 06FD 1286 06FE 1287 06FF 1342 065E 1461 069E PUSH 0001 971 00B8 1015 00CA 1019 00CC 1022 00CE 1025 00D0 1044 00DC 1047 00DE 1362 0145 1450 0169 1641 01B8 1780 01E6 1880 020B 2049 0775 2051 0777 2069 0263 2141 0283 2210 02A3 2213 02A5 2215 02A7 2524 0342 2551 0352 2559 0359 2566 035F 2574 0366 2581 036C 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 158 PPU3/REV 25 microcode | cross-reference table DB0 0012 1273 0128 1375 014C 1376 014D 1549 018F 1885 0210 1948 0233 2039 025F 2977 03D2 2990 03D5 253 0464 774 0573 1218 060C DB4 0011 1122 00FC 1226 011A 1303 0130 1758 01E4 261 046A 773 0572 INDX 0010 971 00B8 2137 0280 2140 0282 2141 0283 2286 02CD 2729 0392 2829 03B1 17 0001 18 0002 19 0003 126 0436 136 043B 146 0441 156 0447 167 044B 177 0451 187 0457 197 045D NOP 0000 POP 0023 975 07E0 976 07E1 977 07E2 978 07E3 1204 0110 1298 012E 1299 012F 1329 0133 1333 0136 1337 0138 1340 013A 1341 013B 1346 013C 1357 0143 1361 0144 1366 0148 1422 015D 1443 0164 1449 0168 1458 016E 1479 0172 1485 0176 1502 017A 1508 017E 1685 01D2 1716 01D5 1738 01DC 1743 01DF 1796 01EE 1832 01F3 1839 01F6 1907 021B 1931 0228 2024 0254 2085 0270 2200 029C 2206 02A0 2209 02A2 2212 02A4 2214 02A6 2216 02A8 2218 02AA 2351 02E6 2352 02E7 2471 031D 2485 0324 2578 036A 2589 0373 2600 0764 2601 0765 2602 0766 2603 0767 2624 0034 2625 0035 2626 0036 2627 0037 2648 0378 2658 037F 2661 0381 2683 0391 2695 0750 2696 0751 2697 0752 2698 0753 2699 0754 2700 0755 2701 0756 2702 0757 2712 0044 2713 0045 2714 0046 2715 0047 2747 0396 2768 0054 2769 0055 2770 0056 2771 0057 2789 039A 2828 03B0 2846 03BB 2883 03BF 2921 03C5 3003 03D7 102 0427 104 0429 106 042B 108 042D 210 0744 211 0745 212 0746 213 0747 219 0748 220 0749 221 074A 222 074B 228 074C 229 074D 230 074E 231 074F 237 0730 238 0731 239 0732 240 0733 274 0720 275 0721 276 0722 277 0723 278 0724 279 0725 280 0726 281 0727 282 0728 283 0729 284 072A 285 072B 286 072C 287 072D 288 072E 289 072F 295 0710 296 0711 297 0712 298 0713 299 0714 300 0715 301 0716 302 0717 303 0718 304 0719 305 071A 306 071B 307 071C 308 071D 309 071E 310 071F 316 0700 317 0701 318 0702 319 0703 320 0704 321 0705 322 0706 323 0707 324 0708 325 0709 326 070A 327 070B 328 070C 329 070D 330 070E 331 070F 371 0482 625 052F 904 05C4 906 05C6 908 05C8 910 05CA 912 05CC 914 05CE 916 05D0 917 05D1 1225 0610 1233 0616 1235 0618 1237 061A 1239 061C 1245 0622 1251 0628 1258 062F 1261 0632 1264 0635 1349 0665 1350 0666 1376 0674 1384 067C 1385 067D 1414 0683 1422 068B 1431 0691 1440 0699 1459 069C 1462 069F 1478 06AC 1479 06AD SKIP 0013 924 0095 997 00C4 1016 00CB 1020 00CD 1023 00CF 1029 00D3 1031 00D4 1039 00D9 1042 00DB 1045 00DD 1068 00E1 1071 00E3 1074 00E5 1077 00E7 1083 00C5 1089 00EC 1092 00EF 1101 00F3 1104 00F5 1126 07D0 1127 07D1 1128 07D2 1129 07D3 1133 07D7 1134 07D8 1140 07DE 1141 07DF 1159 0100 1164 0102 1169 0104 1174 0106 1186 0108 1191 010A 1196 010C 1217 00ED 1277 07B0 1293 00FD 1296 012D 1313 07A6 1316 07A9 1317 07AA 1338 0139 1347 013D 1350 013F 1370 0149 1408 0137 1411 0155 1414 0157 1440 0162 1447 0167 1453 016B 1471 016F 1477 0163 1497 0177 1500 0179 1506 017C 1531 0183 1537 017D 1576 0191 1579 0193 1582 0195 1591 019A 1593 019C 1599 019B 1602 01A1 1605 01A3 1615 01A8 1617 01AA 1623 01A9 1625 01AE 1626 01AF 1629 01B1 1632 01B3 1655 01BF 1658 01C1 1668 01C6 1678 01CD 1727 01C7 1729 01D6 1730 01D7 1733 01D9 1735 01DA 1753 01E0 1768 079C 1826 01F1 1829 01E1 1831 01F2 1851 01FB 1853 01FC 1870 0204 1873 0207 1916 0221 1923 0205 1925 0224 1926 0225 1929 0227 1954 0781 1990 023D 2006 0248 2016 0249 2018 0250 2019 0251 2022 0253 2048 0774 2050 0776 2068 0262 2106 0275 2108 0276 2109 0277 2112 0279 2135 027E 2138 0281 2144 0285 2189 0297 2198 027F 2204 029E 2207 02A1 2232 02AD 2235 02AF 2241 029F 2251 02AB 2254 02B5 2265 02BD 2282 02CA 2309 02D2 2326 02E1 2349 02E5 2418 02CB 2421 02FD 2432 02D3 2439 0308 2441 0309 2444 030A 2445 030B 2447 030C 2451 030E 2453 0310 2458 0313 2529 030F 2532 0347 2543 034D 2646 0321 2652 037A 2654 037C 2680 038F 2745 0395 2748 0397 2787 037B 2790 039B 2792 039C 2793 039D 2807 03A1 2826 03AF 2836 03B3 2915 03C0 2934 0081 2953 03C1 2961 03C9 3040 03EA 51 0405 55 0409 59 040D 72 0411 74 0413 76 0415 77 0416 80 0419 82 041B 84 041D 85 041E 110 042F 131 0437 141 043D 151 0443 161 0449 172 044D 182 0453 192 0459 202 045F 254 0465 257 0467 262 046B 267 046F 352 0475 361 047B 370 0481 400 0487 402 0489 409 048F 411 0491 418 0497 420 0499 427 049F 429 04A1 458 04B5 463 04B9 468 04BD 473 04C1 478 04C5 483 04C9 488 04CD 493 04D1 498 04D5 503 04D9 508 04DD 513 04E1 518 04E5 523 04E9 528 04ED 533 04F1 554 04F5 565 04FB 593 050F 595 0511 597 0513 599 0515 601 0517 603 0519 605 051B 607 051D 609 051F 611 0521 613 0523 615 0525 1BTI PPU ASSEMBLER 18-JUL-91 18:34 PAGE 159 PPU3/REV 25 microcode | cross-reference table 617 0527 619 0529 621 052B 623 052D 644 0533 645 0534 650 0539 672 053F 673 0540 676 0543 707 054B 712 054F 728 0559 733 055D 747 0563 758 0567 772 0571 779 0575 780 0576 783 0579 784 057A 785 057B 794 0584 826 058F 847 059B 849 059D 871 05AB 873 05AD 892 05B9 903 05C3 905 05C5 907 05C7 909 05C9 911 05CB 913 05CD 915 05CF 1108 05D3 1116 05D9 1119 05DB 1125 05DF 1151 05EF 1153 05F1 1160 05F5 1162 05F7 1164 05F9 1173 05FD 1188 0601 1191 0603 1217 060B 1224 060F 1232 0615 1234 0617 1236 0619 1238 061B 1244 0621 1248 0625 1250 0627 1256 062D 1257 062E 1260 0631 1262 0633 1294 0637 1298 063B 1302 063F 1306 0643 1345 0661 1347 0663 1348 0664 1364 066B 1375 0673 1379 0677 1383 067B 1410 067F 1411 0680 1413 0682 1427 068D 1434 0693 1458 069B 1460 069D 1475 06A9 1476 06AA 1477 06AB