1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 1 PPU microcode TITLE.MAC MACRO DEFINITION File# 0 1 TITLE PPU microcode TITLE.MAC MACRO DEFINITION 2 3 SET LEVELSTRING,26 4 5 NOLIST MACROS 6 NOLIST MACINSTR 9 10 ***************************************************************************************************** 11 * This macro is for setting a new title string and starting a new page. * 12 ***************************************************************************************************** 13 14 EXPAND ON 15 SET TITLESTRING,PPU5/REV 26 microcode 16 EXPAND OFF 17 18 MACRO ,,PARAMETER 19 NAME TITLE.MAC 20 TITLE $TITLESTRING 21 TITLE2 $PARAMETER 22 EJECT 23 EMAC 24 TITLE.MAC TITLE PAGE 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 2 PPU5/REV 26 microcode File# 0 TITLE PAGE 25 26 27 28 29 30 31 * ......... BBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 32 * ................. BBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 33 * ..........##......... BBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 34 * ............##........... BBBBBB BBBBBB TTTTTT TTTTTT TTTTTT IIIIII 35 * .............##............ BBBBBB BBBBBB TTTTT TTTTTT TTTTT IIIIII 36 * .............##............ BBBBBB BBBBBBB TTTT TTTTTT TTTT IIIIII 37 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 38 * ..............##............. BBBBBBBBBBBBBBBBB TTTTTT IIIIII 39 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 40 * .............##.............. BBBBBB BBBBBB TTTTTT IIIIII 41 * ...........##.............. BBBBBB BBBBBB TTTTTT IIIIII 42 * ..........##............... BBBBBB BBBBBB TTTTTT IIIIII 43 * ........##............... BBBBBB BBBBBBB TTTTTT IIIIII 44 * .....##.............. BBBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 45 * ................. BBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 46 * ......... BBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 47 * 48 * 49 * ****** Copyright 1986, 1990, 1991 BTI Computer Systems ****** 50 * 51 * This document and the program it describes are the exclusive property 52 * of and proprietary to BTI Computer Systems. No use, reproduction or 53 * disclosure of this document or its contents, either in full or in part, 54 * by any means whatsoever regardless of purpose may be made without the 55 * prior written consent of BTI Computer Systems. 56 * 57 * BTI Computer Systems 58 * Sunnyvale, California 94086 59 60 61 62 63 64 * PPPPPP PPPPPP UU UU CCCCC OOOOO DDDDDD EEEEEEE 65 * PPPPPPP PPPPPPP UU UU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 66 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 67 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 68 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 69 * PPPPPPP PPPPPPP UU UU UU UU CC OO OO DD DD EEEEEEE 70 * PPPPPP PPPPPP UU UU UU UU ---- CC OO OO DD DD EEEEEEE 71 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 72 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 73 * PP PP UU UU UU UU CC OO OO DD DD EE 74 * PP PP UU UU UU CC OO OO DD DD EE 75 * PP PP UU UU UU CC OO OO DD DD EE 76 * PP PP UUUUUUU UUUU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 77 * PP PP UUUUU UU CCCCC OOOOO DDDDDD EEEEEEE 78 79 80 TITLE.MAC TITLE PAGE 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 3 PPU5/REV 26 microcode File# 0 TITLE PAGE 81 82 83 84 85 86 87 * ......... BBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 88 * ................. BBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 89 * ..........##......... BBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 90 * ............##........... BBBBBB BBBBBB TTTTTT TTTTTT TTTTTT IIIIII 91 * .............##............ BBBBBB BBBBBB TTTTT TTTTTT TTTTT IIIIII 92 * .............##............ BBBBBB BBBBBBB TTTT TTTTTT TTTT IIIIII 93 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 94 * ..............##............. BBBBBBBBBBBBBBBBB TTTTTT IIIIII 95 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 96 * .............##.............. BBBBBB BBBBBB TTTTTT IIIIII 97 * ...........##.............. BBBBBB BBBBBB TTTTTT IIIIII 98 * ..........##............... BBBBBB BBBBBB TTTTTT IIIIII 99 * ........##............... BBBBBB BBBBBBB TTTTTT IIIIII 100 * .....##.............. BBBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 101 * ................. BBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 102 * ......... BBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 103 * 104 * 105 * ****** Copyright 1986, 1990, 1991 BTI Computer Systems ****** 106 * 107 * This document and the program it describes are the exclusive property 108 * of and proprietary to BTI Computer Systems. No use, reproduction or 109 * disclosure of this document or its contents, either in full or in part, 110 * by any means whatsoever regardless of purpose may be made without the 111 * prior written consent of BTI Computer Systems. 112 * 113 * BTI Computer Systems 114 * Sunnyvale, California 94086 115 116 117 118 119 120 * PPPPPP PPPPPP UU UU CCCCC OOOOO DDDDDD EEEEEEE 121 * PPPPPPP PPPPPPP UU UU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 122 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 123 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 124 * PP PP PP PP UU UU UU UU CC OO OO DD DD EE 125 * PPPPPPP PPPPPPP UU UU UU UU CC OO OO DD DD EEEEEEE 126 * PPPPPP PPPPPP UU UU UU UU ---- CC OO OO DD DD EEEEEEE 127 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 128 * PP PP UU UU UUUUUUU CC OO OO DD DD EE 129 * PP PP UU UU UU UU CC OO OO DD DD EE 130 * PP PP UU UU UU CC OO OO DD DD EE 131 * PP PP UU UU UU CC OO OO DD DD EE 132 * PP PP UUUUUUU UUUU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 133 * PP PP UUUUU UU CCCCC OOOOO DDDDDD EEEEEEE 134 135 136 TITLE.MAC Revision Log 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 4 PPU5/REV 26 microcode File# 0 Revision Log 137 ***************************************************************************************************** 138 * * 139 * LOG OF CHANGES * 140 * * 141 * * 142 * Revision 13 Mar, 1985 * 143 * -------- -- ---- ---- * 144 * * 145 * Initial release of PPU5 ucode. Primary changes from * 146 * PPU3 are the addition of triple word transfer logic. * 147 * * 148 * * 149 * Revision 14 Mar, 1986 ECN 1627 * 150 * -------- -- ---- ---- --- ---- * 151 * * 152 * Previously, if an output transfer that ended on an even * 153 * address were followed by an address that returned abnormal * 154 * data, a memory parity error might have been erroneously * 155 * reported in the port status. This bug has been fixed in * 156 * this release. * 157 * * 158 * This version delays releasing the controllers until * 159 * near the end of the selftest. This prevents BSEs asserted * 160 * by other bus devices (specificly, PPU3s) from causing disk * 161 * controllers to fail their selftest. * 162 * * 163 * * 164 * Revision 16 Dec, 1986 ECN 1644 * 165 * -------- -- ---- ---- --- ---- * 166 * * 167 * If an output transfer ended on an even word that * 168 * returned abnormal data flags, then the most significant * 169 * two bytes of the last word were not output to the * 170 * controller (only the least significant two bytes were * 171 * output). This bug has been fixed in this release. * 172 * * 173 * Occasionally, when running in the offline environment * 174 * which polls for interrupts, the 'BCROLL' bit in the port * 175 * status register was missed by the software. This caused * 176 * erroneous byte count not ready errors. This bug has been * 177 * fixed in this release. * 178 * * 179 * A minor enhancement in the CPU read processor section of * 180 * the microcode allows port status read requests to return two * 181 * bus ticks earlier. * 182 * * 183 * * 184 * Revision 18 Feb, 1990 ECN 1716 * 185 * -------- -- ---- ---- --- ---- * 186 * * 187 * Major modifications to the byte count rollover logic. * 188 * Previous versions would set an error and terminate the * 189 * transfer if a primary byte count rolled over and the next * 190 * secondary byte count was not ready yet. This, in general, * 191 * is not needed, since the peripheral controllers will detect * 192 * an overrun/underrun situation. In the case of asyncronous * 193 * controllers, particularly very fast ones, this feature * 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 5 PPU5/REV 26 microcode File# 0 Revision Log 194 * caused needless transfer aborts. This has been changed so * 195 * that the port just waits for the secondary count to be * 196 * loaded and then continues the transfer. * 197 * * 198 * Modifications to the idle loop EOR processor and the * 199 * CPU write processor to free up SCR4 to be used in port * 200 * timing functions. Timing functions modified so that the * 201 * controllers get about 15 ms to answer a request. * 202 * * 203 * Modifications to the selftest code to release the * 204 * controllers 1.00 sec after the start of the selftest. This * 205 * ensures that no controller is running while BSE is being * 206 * exercised on the superbus. * 207 * * 208 * * 209 * Revision 26 Jul, 1991 ECN 1725 * 210 * -------- -- ---- ---- --- ---- * 211 * * 212 * Revision levels now in decimal in documentation. * 213 * * 214 * Bug fix in secondary byte count loader where interrupts * 215 * were enabled improperly such that a byte count rollover * 216 * interrupt could be lost. * 217 * * 218 * Modifications to the WTFORBUS subroutine to ensure * 219 * that it does not time out if the data channels are continuously * 220 * requesting interrupt. * 221 * * 222 * Changed the I to IP on quite a large number of POP * 223 * instructions. The I...POP construct caused stack overflows * 224 * in rare cases of worst case interrupt timing. * 225 * * 226 * Modified the call back needed processor to skip fetching * 227 * the second bus word on a single word transfer. * 228 * * 229 ***************************************************************************************************** 230 TITLE.MAC MACRO definitions 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 6 PPU5/REV 26 microcode File# 0 MACRO definitions 231 ***************************************************************************************************** 232 * * 233 * The main purpose of most of these macros is to efficiently use the * 234 * PROM space. Since PPU5 now has more PROM space than the old PPU3 that * 235 * these macros were copied from, space savings is not as big a concern, * 236 * so the macros have been changed so that they don't reclaim 1 word * 237 * chunks. This should allow a little bit better readability of the * 238 * microcode for debugging. The addresses of skips and their targets is now * 239 * in the order of the addresses instead of skipping around a lot like the * 240 * space reclaiming macros did. The main changes are the replacement of the * 241 * STARTSKP macro with another one (the old one is still here but commented * 242 * out in case it is needed in the future) and the addition of macros * 243 * called ODD and EVEN to ORG to odd or even addresses. The macros still * 244 * count any wasted space for reporting at the end of the assembly. The * 245 * 'WASTE' macro now also puts a HALT (using the 'HALT' macro) into the * 246 * wasted words. * 247 * * 248 ***************************************************************************************************** 249 250 >>>>>>>>>>>>>>>>>>>>> 251 > MACRO ,, 252 > NAME SKIPORG, NOLIST DETAIL 253 > NAME EVEN, NOLIST DETAIL 254 > IF (* BAND 1) EQ 0, GOTO .EXIT1 255 > 256 > NAME WASTE, NOLIST DETAIL 257 >WSTE$WSTECNTR HALT ****** wasted ****** 258 >WSTECNTR REEQU WSTECNTR+1 259 >.EXIT1 260 > LIST DETAIL 261 > EMAC 262 >>>>>>>>>>>>>>>>>>>>> 263 264 >>>>>>>>>>>>>>>>>>>>> 265 > MACRO ,, 266 > NAME STARTSKP, NOLIST DETAIL 267 > NAME ODD, NOLIST DETAIL 268 > IF (* BAND 1) NE 0, GOTO .EXIT2 269 > WASTE 270 >.EXIT2 271 > LIST DETAIL 272 > EMAC 273 >>>>>>>>>>>>>>>>>>>>> 274 275 >>>>>>>>>>>>>>>>>>>>> 0000 276 >MEMORY EQU 0 0000 277 >REMEMBER EQU 0 0000 278 >WSTECNTR EQU 0 0000 279 >WSTEPNTR EQU 0 280 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 7 PPU5/REV 26 microcode File# 0 MACRO definitions 282 ***************************************************************************************************** 283 * * 284 * This is the old STARTSKP macro that reclaimed wasted space. * 285 * * 286 ** LBOX * 287 ** MACRO ,, * 288 ** NAME STARTSKP, NOLIST DETAIL * 289 ** IF (* BAND 1) EQ 1, GOTO .EXIT2 * 290 ** IF WSTEPNTR GE WSTECNTR, GOTO .IFBLOCK * 291 **MEMORY REEQU * * 292 ** ORG WSTE$WSTEPNTR * 293 **WSTEPNTR REEQU WSTEPNTR+1 * 294 **.READQ RESET Q+ * 295 ** LIST MACROS * 296 **$Q * 297 ** NOLIST MACROS * 298 ** ORG MEMORY * 299 ** LIST DETAIL * 300 ** EXIT * 301 ** * 302 **.IFBLOCK IF BLOCKON EQ 0, GOTO .HERE * 303 **MEMORY REEQU * * 304 ** ORG REMEMBER * 305 **REMEMBER REEQU REMEMBER+1 * 306 ** GOTO .READQ * 307 ** * 308 **.HERE RESET Q+ * 309 ** LIST MACROS * 310 **$Q * 311 ** NOLIST MACROS * 312 ** WASTE * 313 **.EXIT2 * 314 ** LIST DETAIL * 315 ** EMAC * 316 ** ELBOX * 317 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 8 PPU5/REV 26 microcode File# 0 MACRO definitions 319 ***************************************************************************************************** 320 * * 321 * The macros BLOCK and ENDBLOCK are used to get into the block * 322 * structures used for multiway branches. They ORG to an appropriate * 323 * address to do a multiway branch from and also provide a convenient * 324 * constant to OR into a scratch register if you are not doing a full 16 * 325 * way branch. * 326 * * 327 ***************************************************************************************************** 328 329 >>>>>>>>>>>>>>>>>>>>> 330 > MACRO ,,PARAMS 331 > NAME BLOCK, NOLIST MACROS 332 > IF BLOCKON, ENDBLOCK 333 >REMEMBER REEQU * 334 >BLK.SIZE REEQU $PARAMS(1) 335 > IF BLK.SIZE EQ 4, GOTO .BLOCK4 336 > IF BLK.SIZE EQ 8, GOTO .BLOCK8 337 > IF BLK.SIZE EQ 16, GOTO .BLOCK16 338 > Bad Call 339 > GOTO .EXIT 340 > 341 >.BLOCK4 IF B4.USED LT 4, GOTO .BLOCK4A 342 >B4.USED REEQU 0 343 >B4.ORG REEQU BLOCKORG 344 >BLOCKORG REEQU BLOCKORG-16 345 >.BLOCK4A ORG B4.ORG 346 >B4.ORG REEQU B4.ORG+4 347 >$PARAMS(2) EQU (B4.USED*4) BAND #C 348 >B4.USED REEQU B4.USED+1 349 > GOTO .EXIT 350 > 351 >.BLOCK8 IF B8.USED LT 2, GOTO .BLOCK8A 352 >B8.USED REEQU 0 353 >B8.ORG REEQU BLOCKORG 354 >BLOCKORG REEQU BLOCKORG-16 355 >.BLOCK8A ORG B8.ORG 356 >B8.ORG REEQU B8.ORG+8 357 >$PARAMS(2) EQU (B8.USED*8) BAND #8 358 >B8.USED REEQU B8.USED+1 359 > GOTO .EXIT 360 > 361 >.BLOCK16 ORG BLOCKORG 362 >BLOCKORG REEQU BLOCKORG-16 363 >.EXIT 364 >BLOCKADD REEQU * 365 >*BLOCKON REEQU 1 366 > LIST MACROS 367 > EMAC 368 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 9 PPU5/REV 26 microcode File# 0 MACRO definitions 370 >>>>>>>>>>>>>>>>>>>>> 371 > MACRO 372 > NAME ENDBLOCK, NOLIST MACROS 373 > IF BLOCKADD+BLK.SIZE GE *, GOTO .BLK.REP 374 > Size Exceeded 375 > GOTO .GO.BACK 376 > 377 >.BLK.REP REP BLOCKADD+BLK.SIZE-*,N 378 > WASTE 379 >.GO.BACK ORG REMEMBER 380 >BLOCKON REEQU 0 381 > LIST MACROS 382 > EMAC 383 > 0000 384 >BLK.SIZE EQU 0 0EE0 385 >BLOCKORG EQU #EE0 0000 386 >BLOCKON EQU 0 0004 387 >B4.USED EQU 4 0002 388 >B8.USED EQU 2 389 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 10 PPU5/REV 26 microcode File# 0 MACRO definitions 391 ***************************************************************************************************** 392 * * 393 * The VECTOR and ENDVECTOR macros are used to make interrupt vectors. * 394 * They ORG the assembler's location counter to an appropriate address for * 395 * an interrupt vector. * 396 * * 397 ***************************************************************************************************** 398 399 >>>>>>>>>>>>>>>>>>>>> 400 > MACRO ,, 401 > NAME VECTOR, NOLIST MACROS 402 > IF VECTORON, ENDVECTOR 403 >REMEMBER REEQU * 404 > ORG VECTORORG 405 > IF VECTORORG GE #1000,Too many vectors ----- out of PROM space. 406 >VECTORORG REEQU VECTORORG+16 407 >VECTORADD REEQU * 408 >VECTORON REEQU 1 409 > LIST MACROS 410 > EMAC 411 > 412 > MACRO 413 > NAME ENDVECTOR, NOLIST MACROS 414 > IF VECTORADD+16 GE *, GOTO .VEC.REP 415 > Size Exceeded 416 > GOTO .GO.BACK1 417 > 418 >.VEC.REP REP VECTORADD+16-*,N 419 > WASTE 420 >.GO.BACK1 ORG REMEMBER 421 >VECTORON REEQU 0 422 > LIST MACROS 423 > EMAC 424 > 0F00 425 >VECTORORG EQU #F00 0000 426 >VECTORON EQU 0 427 >>>>>>>>>>>>>>>>>>>>> 429 >>>>>>>>>>>>>>>>>>>>> 430 > MACRO ,,N 431 > NAME REP, NOLIST MACROS 432 >REP.RPT REEQU $N(1) 433 >REP.LST REEQU '$N(2)' NE 'N' 434 > RESET N+ 435 >.REP01 IF REP.RPT LE 0, GOTO .EXIT3 436 > IF REP.LST, LIST MACROS 437 >$N 438 > NOLIST MACROS 439 >REP.RPT REEQU REP.RPT-1 440 > GOTO .REP01 441 >.EXIT3 LIST MACROS 442 > EMAC 443 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 11 PPU5/REV 26 microcode File# 0 MACRO definitions 445 ***************************************************************************************************** 446 * * 447 * MACRO HALT * 448 * * 449 * This macro is used to make a PPU halt. It puts the address of * 450 * the HALT into SCR1F for inclusion in WRU 14. * 451 ***************************************************************************************************** 452 453 >>>>>>>>>>>>>>>>>>>>> 454 > MACRO LABEL,,COMMENT 455 > NAME HALT, NOLIST DETAIL 456 > LIST MACINSTR 457 > LIST MACROS 458 >$LABEL LIT SCR1F * * $COMMENT 459 > NOLIST MACINSTR 460 > NOLIST MACROS 461 > LIST DETAIL 462 > EMAC 463 >>>>>>>>>>>>>>>>>>>>> 464 TITLE.MAC RAM allocation 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 12 PPU5/REV 26 microcode File# 0 RAM allocation 0000 465 ORG #000 466 * RAM allocation 467 000 468 NEXTPORT BSS 4 number of next port to service 469 004 470 PBITLOW BSS 4 2^(port #) 008 471 PBITHIGH BSS 4 2^(port # + 4) 00C 472 PBITIM BSS 4 port interrupt mask bit 473 010 474 FLAGS BSS 4 command/status I/O control flags 014 475 PRTST BSS 4 port's internal status 476 018 477 EORTIMER BSS 4 timer used by EOR processing 478 01C 479 CLKFIX BSS 4 used by clock correction function 480 020 481 TYPECKSM BSS 4 C/S type/byte count and checksum 024 482 CNTDOWN BSS 4 C/S time-out counter 028 483 ADDRESS BSS 4 C/S address 02C 484 HWORD BSS 4 C/S high order word 030 485 LWORD BSS 4 C/S low order word 034 486 RESPTO BSS 4 slot awaiting response / bus control bits 487 038 488 HSW1 BSS 4 controller's high order status word one 03C 489 LSW1 BSS 4 controller's low order status word one 040 490 HSW2 BSS 4 controller's high order status word two 044 491 LSW2 BSS 4 controller's low order status word two 492 048 493 BCOVERUN BSS 4 byte count overrun detector 04C 494 CORBC BSS 4 byte count correction factor, BC:=BCNT+LAST+CORBC 495 050 496 SLOT BSS 4 memory slot / bus control flags / pair one 054 497 BCNT BSS 4 DMA byte count as a multiple of four or eight / pair one 058 498 LAST BSS 4 DMA byte count with LAST bit and residual / pair one 05C 499 HADDR BSS 4 high order memory address / bus command / pair one 060 500 LADDR BSS 4 low order memory address / pair one 501 064 502 SLOT2 BSS 4 memory slot / bus control flags / pair two 068 503 BCNT2 BSS 4 DMA byte count as a multiple of four or eight / pair two 06C 504 LAST2 BSS 4 DMA byte count with LAST bit and residual / pair two 070 505 HADDR2 BSS 4 high order memory address / bus command / pair two 074 506 LADDR2 BSS 4 low order memory address / pair two 507 078 508 BIHC BSS 4 bus input data / high order command word 07C 509 BILC BSS 4 bus input data / low order command word 080 510 BIHD BSS 4 bus input data / high order data word 084 511 BILD BSS 4 bus input data / low order data word 088 512 BIFT BSS 4 bus input data / FROM-TO register 08C 513 BIST BSS 4 bus input status 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 13 PPU5/REV 26 microcode File# 0 RAM allocation 090 515 WRURES1A BSS 4 These 32 locations hold the WRU responses 094 516 WRURES1B BSS 4 098 517 WRURES2A BSS 4 09C 518 WRURES2B BSS 4 0A0 519 WRURES3A BSS 4 0A4 520 WRURES3B BSS 4 0A8 521 WRURES4A BSS 4 0AC 522 WRURES4B BSS 4 523 524 * The following two temps may not be used by interrupt routines 0B0 525 TEMP BSS 4 may not be used by interrupt routines 0B4 526 TEMP2 BSS 4 used only by the WTFORBUS routine 527 0B8 528 OLDBCNT BSS 4 used for timeout checking of bus output logic 529 TITLE.MAC EQU & Register definitions 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 14 PPU5/REV 26 microcode File# 0 EQU & Register definitions 0000 530 ORG #000 531 532 EXPAND ON 001A 533 LEVEL EQU 26 microcode revision level 534 * change this constant by changing the LEVELSTRING constant 535 * on page 1 536 EXPAND OFF 537 0004 538 NUMPORTS EQU 4 number of ports connected: numbered 0 to NUMPORTS-1 539 FFFF 540 CM EQU -1 CM-x is read "complement of" x 541 542 ***************************************************************************************************** 543 * * 544 * Time-out Constants * 545 * The timeout constants named TIM* are used to control the * 546 * timer that deadmans the PPU to controller communications. This * 547 * timer is a counter that counts the number of times through the * 548 * IDLE loop, but the counter (SCR4) needs to be incremented by * 549 * any work that significantly slows down the progress through the * 550 * IDLE loop. * 551 * TIMBYTC, TIMBYRD, and TIMBYWR are used to control the * 552 * counter increment that adjusts for the (considerable) overhead * 553 * of actually transferring data to or from a channel. This overhead * 554 * must be allocated approximately as incurred, so the idle loop * 555 * checks for TIMBYTC bytes to be transferred, then uses one of the * 556 * other values to adjust the timeout counter. * 557 * * 558 ***************************************************************************************************** 559 560 * These first constants are counts 'through the idle loop' 561 * (between 10.3 and 11.2 microseconds) 562 053C 563 TIMECNST EQU 1340 time-out counter constant (C/S) = 15 msec 0001 564 TIMIDLE EQU 1 number of counts added each time through idle loop 0004 565 TIMECSIN EQU 4 fudge for each word sent by controller 0001 566 TIMERSPX EQU 1 fudge for each word returned to CPU 0003 567 TIMERW EQU 3 fudge for each word requested by CPU from controller 0006 568 TIMEWW EQU 6 fudge for each word written by CPU to controller 569 0200 570 TIMBYTC EQU 512 bytes of I/O equivalent to TIMBYRD or TIMBYWR counts 0018 571 TIMBYRD EQU 24 counts for read of TIMBYTC bytes 000C 572 TIMBYWR EQU 12 counts for write of TIMBYTC bytes 573 574 * Other timeout values 575 007D 576 CBNTO EQU 125 time-out counter constant (CBN) =.1 msec 000C 577 BUSTO EQU 12 time-out counter constant (Idle Loop monitor) >=.1 msec 007D 578 BUSTO2 EQU 125 time-out counter constant (EOR processor) >=.1msec 579 * WFBTO and WFBTO2 are used in the WaitForBus routine in a loop 580 * consisting of 3 T4 instructions (.8 usec) 0064 581 WFBTO EQU 100 time-out counter constant (Waiting for the BUS) >= 80 usec 04E2 582 WFBTO2 EQU 1250 time-out counter constant (Waiting for the BUS) >= 1 msec 583 * CTMTO is used in the Bus error routine in a loop 584 * consisting of 3 T4 instructions (.8 usec) 007D 585 CTMTO EQU 125 time-out counter constant (Copy to Me) =.1 msec 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 15 PPU5/REV 26 microcode File# 0 EQU & Register definitions 587 ***************************************************************************************************** 588 * * 589 * PPU Internal Status Bits Definitions (SCR6) * 590 * * 591 * The low order byte of SCR6 is used as a timer for BUS transfers * 592 * * 593 ***************************************************************************************************** 0100 595 SOPPFW EQU #0100 We have seen PFW asserted 0200 596 SOPBTO EQU #0200 We are timing a BUS transfer 1000 597 SOPDDW EQU #1000 set if we are in double data word write mode 598 599 ***************************************************************************************************** 600 * * 601 * Command/Status byte definitions * 602 * These are definitions for the first byte transmitted * 603 * on the command/status path (between PPU and controller). * 604 * * 605 ***************************************************************************************************** 606 000E 607 ACK EQU #0E C/S acknowledge code 00F8 608 NAK EQU #F8 C/S negative acknowledge code 609 0050 610 INTR EQU #50 C/S interrupt request from controller 0054 611 INTRS EQU #54 C/S interrupt request with status from controller 00C4 612 LS1 EQU #C4 C/S load controller status word one transmission 0034 613 LS2 EQU #34 C/S load controller status word two transmission 0060 614 GO EQU #60 C/S controller requests data from PPU 0090 615 EOR EQU #90 C/S end of record code from controller 00A4 616 RESP EQU #A4 C/S response from controller 617 0062 618 CTLRRD EQU #62 C/S read command to controller 0096 619 CTLRWR EQU #96 C/S write command to controller 620 621 ***************************************************************************************************** 622 * * 623 * These values are used to initialize the TYPECKSM * 624 * variable when a transmission on the C/S path is * 625 * initiated. * 626 * * 627 ***************************************************************************************************** 628 8000 629 CRDTEST EQU #8000 used in read/write test 809D 630 CRDSTART EQU (CTLRRD BXOR #FF)+CRDTEST controller read start value 0069 631 CWRSTART EQU (CTLRWR BXOR #FF) controller write start value 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 16 PPU5/REV 26 microcode File# 0 EQU & Register definitions 633 ***************************************************************************************************** 634 * * 635 * Definitions for FLAGS * 636 * also note that the lower 8 bits of FLAGS are used a follows: * 637 * Bits 7-4 number representing the state of the C/S handshake * 638 * BITS 3-0 I/O retry count * 639 * * 640 ***************************************************************************************************** 641 0100 642 DOINGINP EQU #0100 C/S Input transfer in progress 0200 643 DOINGOUT EQU #0200 C/S Output transfer in progress 0400 644 TIMING EQU #0400 C/S Timing on port in progress 0800 645 WAITING EQU #0800 C/S Waiting for response on this port 1000 646 RGOB EQU #1000 C/S GO-byte received on this port 2000 647 REOR EQU #2000 C/S EOR-byte received on this port 4000 648 PORTDEAD EQU #4000 C/S port DEAD 8000 649 TIMEDOUT EQU #8000 C/S port has been timed-out 650 40C0 651 SETDEAD EQU PORTDEAD+#C0 C0D0 652 SETIMED EQU TIMEDOUT+PORTDEAD+#D0 653 FC00 654 CLRFLAGS EQU #FF00-DOINGOUT-DOINGINP F3FF 655 CLRWAIT EQU CM-WAITING-TIMING F4FF 656 CSFREE EQU CM-WAITING-DOINGOUT-DOINGINP 657 0520 658 STARTINP EQU TIMING+DOINGINP+#20 0070 659 SENDRESP EQU #70 660 0080 661 RESTRDWR EQU #80 0681 662 STARTWR EQU TIMING+DOINGOUT+RESTRDWR+1 0E81 663 STARTRD EQU STARTWR+WAITING 00F0 664 RECVRESP EQU #F0 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 17 PPU5/REV 26 microcode File# 0 EQU & Register definitions 666 ***************************************************************************************************** 667 * * 668 * Port Status Bits * 669 * These are definitions for the bits that are retrieved * 670 * from the port logic using a PTST op-code. * 671 * * 672 ***************************************************************************************************** 673 4000 674 PRTPON EQU #4000 Controller status: PON+ de-asserted 2000 675 PRTCI EQU #2000 Command path status: Command.In 1000 676 PRTFREE EQU #1000 Command path status: path Free 0800 677 PRTINT EQU #0800 Data path status: no FIFO interrupt pending 0400 678 PRTPE EQU #0400 Data path status: input parity error 0200 679 PRTHIGH EQU #0200 Data path status: FIFO has a high byte 0100 680 PRTLOW EQU #0100 Data path status: FIFO has a low byte FCFF 681 PRTEMPTY EQU CM-PRTHIGH-PRTLOW port empty mask 682 0000 683 BLANKS EQU #0000 odd byte transfer fill characters 685 ***************************************************************************************************** 686 * * 687 * port command bits * 688 * * 689 ***************************************************************************************************** 690 0000 691 DIRINP EQU 0 port direction is INPUT 0001 692 DIROUT EQU 1 port direction is OUTPUT 694 ***************************************************************************************************** 695 * * 696 * Port DPRST constant definitions * 697 * * 698 * The default condition to reset the ports into when they are not in * 699 * use is direction in and single data word transfer mode. The ports logic * 700 * is only set for direction out when an output transfer is started (first * 701 * byte count is written). The port logic will only be set for double data * 702 * word transfers to memory when a transfer is started (1st byte count * 703 * written) and the PPU is set to the double data word transfer to memory. * 704 * The ports are set to the default condition (direction in, single data * 705 * word xfer) when the PPU is initialized (master clear or end of * 706 * selftest), when a transfer ends (byte count overrun, EOR received, or * 707 * bytecount exhausted), and when an abort or reset is done to a port. * 708 * * 709 ***************************************************************************************************** 710 0001 711 DPRST1IN EQU 1 constant for single data word transfer to memory 0000 712 DPRST2IN EQU 0 constant for double data word transfer to memory 0001 713 DPRSTOUT EQU 1 constant for double data word read from memory 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 18 PPU5/REV 26 microcode File# 0 EQU & Register definitions 715 ***************************************************************************************************** 716 * * 717 * Port & Interrupt Control * 718 * Definitions for the interrupt control, etc. * 719 * * 720 ***************************************************************************************************** 721 0003 722 PRTNUMMASK EQU NUMPORTS-1 used by interrupt routine to mask off port number 723 0001 724 PORTLOW EQU 2^0 port zero low bit 0010 725 PORTHIGH EQU 2^4 port zero high bit 726 0020 727 IBFIM EQU 2^5 input buffer full interrupt mask bit 0010 728 CBNIM EQU 2^4 call back needed interrupt mask 0008 729 PORT3IM EQU 2^3 port three interrupt mask 0004 730 PORT2IM EQU 2^2 0002 731 PORT1IM EQU 2^1 0001 732 PORT0IM EQU 2^0 port zero interrupt mask 733 FFCF 734 INITINTS EQU CM-IBFIM-CBNIM initial interrupt mask - Input Buffer Full & Call 735 736 ***************************************************************************************************** 737 * * 738 * Interrupt address pointer definitions. * 739 * These are the values that go into the RAM address field when * 740 * using the IADR destination to set up the interrupt vectors. * 741 * * 742 * Input Buffer Full (IBF) vector handling * 743 * The way this interrupt vector is handled is as follows: * 744 * This interrupt vector is initialized to TWOWORDS and * 745 * stays there except for those few cases (primarily end * 746 * of odd length transfers, etc) where an alternate routine * 747 * is needed. In those cases, right after the read command * 748 * is output to the bus (SBCB op-code), IBFIADR is changed * 749 * to the desired interrupt routine. * 750 * No other channel is allowed to interrupt (hardware disable) * 751 * until the bus is not busy, then the IBF interrupt has the * 752 * priority. This ensures that the channel that set up the * 753 * alternate routine is the only one that uses it. * 754 * This interrupt routine then changes IBFIADR back to TWOWORDS * 755 * before it exits or gets into an interruptable part. * 756 * * 757 ***************************************************************************************************** 758 0020 759 IBFIADR EQU 2*2^4 system bus IBF interrupt address pointer 0030 760 CBNIADR EQU 3*2^4 call back needed interrupt address pointer 0040 761 PRT3IADR EQU 4*2^4 port three interrupt address pointer 0050 762 PRT2IADR EQU 5*2^4 0060 763 PRT1IADR EQU 6*2^4 0070 764 PRT0IADR EQU 7*2^4 port zero interrupt address pointer 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 19 PPU5/REV 26 microcode File# 0 EQU & Register definitions 766 ***************************************************************************************************** 767 * * 768 * System Bus Status Definitions * 769 * These are the definitions of the bus status retrieved * 770 * with the SBST source. * 771 * * 772 ***************************************************************************************************** 773 8000 774 PFWNOT EQU #8000 system bus status input--power fail warning (active 4000 775 BPE EQU #4000 system bus status input--BUS parity error 0800 776 RTOIN EQU #0800 system bus status input--request to output 0400 777 CBN EQU #0400 system bus status input--call back needed 0200 778 RFRIN EQU #0200 system bus status input--ready for response 0100 779 RFIIN EQU #0100 system bus status input--ready for input 0080 780 DWTIN EQU #0080 system bus status input--double word transfer 0040 781 IBF EQU #0040 system bus status input--input buffer full F5BF 782 BUSFREE EQU CM-RTOIN-RFRIN-IBF flags for checking if the BUS is free F5FF 783 BUSACTIV EQU CM-RTOIN-RFRIN flags for checking if the BUS has timed-out 784 785 ***************************************************************************************************** 786 * * 787 * System Bus Flag Definitions * 788 * The bus flags appear in various two bit fields in both * 789 * the SBST source and the SBCB destination. These are the * 790 * various definitions for the flag values. * 791 * * 792 ***************************************************************************************************** 793 0000 794 FLAGSAB EQU 0 tags for abnormal data (memory parity error) 0001 795 FLAGSDATA EQU 1 tags for normal data 0002 796 FLAGSCOMM EQU 2 tags for command word 797 7030 798 FLAGMASK EQU BPE+#3030 mask for input flags 1000 799 WORD1DATA EQU FLAGSDATA*#1000 value for data flags for word 1 only 2020 800 COMMCOMM EQU FLAGSCOMM*#1000+FLAGSCOMM*#10 value for single word command 2010 801 COMMDATA EQU FLAGSCOMM*#1000+FLAGSDATA*#10 value for double word command 1010 802 DATADATA EQU FLAGSDATA*#1000+FLAGSDATA*#10 value for single word data 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 20 PPU5/REV 26 microcode File# 0 EQU & Register definitions 804 ***************************************************************************************************** 805 * * 806 * System Bus Command Definitions * 807 * These are the definitions for use with the SBCB destination. * 808 * * 809 ***************************************************************************************************** 810 8000 811 HPR EQU #8000 system bus control output--high priority request 812 * EQU #4000 system bus control output--force bus parity error 2000 813 BSE EQU #2000 system bus control output--bus error 1000 814 TWT EQU #1000 system bus control output--triple word transfer 0008 815 RFROUT EQU #0008 system bus control output--ready for response 0004 816 RFR2OUT EQU #0004 system bus control output--ready for response/secon 0004 817 RFIOUT EQU #0004 system bus control output--ready for input 0002 818 DWTOUT EQU #0002 system bus control output--double word transfer 0001 819 RTOOUT EQU #0001 system bus control output--request to output 820 0011 821 RTODATA EQU FLAGSDATA*#10+RTOOUT respond to CPU 0010 822 ADATAXOR EQU (FLAGSDATA BXOR FLAGSAB)*#10 XOR to change Good Data to Abn 0004 823 XORFF1W EQU RFR2OUT XOR to change Double Read to S 1000 824 XORSLOT2W EQU TWT XOR to change Single data writ 009B 825 COPYTOME EQU FLAGSCOMM*#40+FLAGSDATA*#10+DWTOUT+RTOOUT+RFROUT copy output to input 826 827 * For use with the SBINT destination. 0001 828 INT EQU #0001 system bus control output--interrupt 829 830 ***************************************************************************************************** 831 * * 832 * System Bus Command Definitions * 833 * READBITS, and WRITBITS are composites of a bus command (SBHC) * 834 * and the bus control bits (SBCB). They are set up this way for * 835 * convenience of use in the code. * 836 * * 837 ***************************************************************************************************** 838 2000 839 READ1W EQU #2000 system bus single word read 3000 840 READ2W EQU #3000 system bus double word read 0000 841 WRITE EQU #0000 system bus write 7000 842 WRITE2W EQU #7000 system bus 2 data word write 843 B02D 844 READBITS EQU HPR+READ2W+FLAGSCOMM*#10+RFROUT+RFR2OUT+RTOOUT read from memory 8063 845 WRITBITS EQU HPR+WRITE+FLAGSDATA*#40+FLAGSCOMM*#10+DWTOUT+RTOOUT write into memory 846 1000 847 XORCF1W EQU READ1W BXOR READ2W XOR to change Double Read to S 7000 848 XORHADDR2W EQU WRITE BXOR WRITE2W XOR to change Single data writ 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 21 PPU5/REV 26 microcode File# 0 EQU & Register definitions 850 ***************************************************************************************************** 851 * * 852 * Internal Port Status (PRTST) Bit Definitions * 853 * * 854 ***************************************************************************************************** 855 0001 856 DMADIR EQU #0001 DMA direction, 1=write, 0=read (CPU perspective) 0002 857 PPUINTR EQU #0002 PPU requests CPU to interrupt 0004 858 DMAOE EQU #0004 DMA output to controller enabled 0008 859 CTLRINTR EQU #0008 controller requests CPU to interrupt 0010 860 BCROLL EQU #0010 byte count rollover 0020 861 BCLAST EQU #0020 last byte count processed 0040 862 BCNRDY EQU #0040 waiting for next byte count 0080 863 DMANBZ EQU #0080 DMA not busy 0100 864 MPECODE EQU #0100 memory parity error 0200 865 BCINT EQU #0200 cause PPUINTR on BCROLL 0400 866 COCKPIT EQU #0400 PPU is in strange state / must do an ABORT 0800 867 CTLRINTE EQU #0800 controller allowed to interrupt CPU 1000 868 PPUINTE EQU #1000 PPU allowed to interrupt CPU 2000 869 DPPE EQU #2000 data path parity error 4000 870 EXTRA EQU #4000 unexpected input received on data path 8000 871 BTWREC EQU #8000 between records (set by EOR from controller) 873 ***************************************************************************************************** 874 * * 875 * PSEUDO ADDRESS DEFINITIONS * 876 * * 877 ***************************************************************************************************** 878 3000 879 PPUTYPE EQU #3000 type code for a PPU 880 0200 881 CBIT EQU #0200 command word bit that says "to controller" 882 883 * We interpret this bit from the SBLC source in the 884 * Set Triple Word Transfer pseudo-address write. 0001 885 DOUBWRTBIT EQU #0001 this bit turns on double data word writes 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 22 PPU5/REV 26 microcode File# 0 EQU & Register definitions 887 888 ***************************************************************************************************** 889 * * 890 * Combined status bits: * 891 * LASTBC bits set by last byte count being completed * 892 * BCRATEOR bits set when BC rollover occurs at EOR * 893 * EORINTR bits set when EOR processing is completed * 894 * OVRRUN bits set when next byte count isn't ready on time * 895 * CONFUSED bits set when something is wrong * 896 * CTLRINT if all these bits are on then do interrupt * 897 * PPUINT if all these bits are on then do interrupt * 898 * INTCLR bits cleared when WRU gets interrupting port number * 899 * PRTINIT initial status of port on power-up * 900 * ENDWRITE bits set when EOR terminates write * 901 * GOODBITS bits that may be changed by CPU * 902 * STSCLBTS bits cleared by reading status * 903 * BC1CLR bits cleared by loading byte count one * 904 * ABTCLR bits cleared by ABORT * 905 * ABTSET bits set by ABORT * 906 * * 907 ***************************************************************************************************** 908 00B2 909 LASTBC EQU BCLAST+DMANBZ+BCROLL+PPUINTR 0092 910 BCRATEOR EQU DMANBZ+PPUINTR+BCROLL 0082 911 EORINTR EQU DMANBZ+PPUINTR 0050 912 OVRRUN EQU BCNRDY+BCROLL 0402 913 CONFUSED EQU COCKPIT+PPUINTR 0808 914 CTLRINT EQU CTLRINTE+CTLRINTR 1002 915 PPUINT EQU PPUINTE+PPUINTR E7FF 916 INTCLR EQU CM-PPUINTE-CTLRINTE 8080 917 PRTINIT EQU DMANBZ+BTWREC 7FFB 918 BTWRECOE EQU CM-BTWREC-DMAOE 8082 919 ENDWRITE EQU BTWREC+DMANBZ+PPUINTR 1A01 920 GOODBITS EQU PPUINTE+CTLRINTE+BCINT+DMADIR FFE5 921 STSCLBTS EQU CM-BCROLL-CTLRINTR-PPUINTR 1E0B 922 BC1CLR EQU CM-EXTRA-BTWREC-DPPE-MPECODE-DMANBZ-BCNRDY-BCLAST-BCROLL-DMAOE 9A89 923 ABTCLR EQU CM-EXTRA-COCKPIT-DMAOE-PPUINTR-BCROLL-BCLAST-BCNRDY-MPECODE-DPPE 8080 924 ABTSET EQU BTWREC+DMANBZ 925 8000 926 LASTBIT EQU #8000 bit in a byte count that says it is the last one 927 TITLE.MAC Scratch Register usage 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 23 PPU5/REV 26 microcode File# 0 Scratch Register usage 929 ***************************************************************************************************** 930 * * 931 * Scratch Register Usage: * 932 * * 933 * SCR n USE * 934 * ----- ------------------------------------------------------ * 935 * 0 IDLE loop scratch * 936 * 1 IDLE loop scratch * 937 * 2 IDLE loop scratch * 938 * 3 IDLE loop scratch * 939 * * 940 * 4 timer. Ticks about every 155 bus clocks. * 941 * 5 current idle loop port number * 942 * 6 PPU Internal Status & BUS RTO timer (low byte) * 943 * 7 the current Interrupt Poll response - high bytes * 944 * * 945 * 8 interrupt mask * 946 * 9 FIFO output enable flags * 947 * A BUS transfer timer scratch (used to store last value of SCRB that caused * 948 * RTO timer to be reset) * 949 * B BUS transfer counter (incremented by routines that do bus transfers) * 950 * (also used for BUS errors) * 951 * * 952 * C FIFO & IBF interrupt scratch * 953 * D the number of IBF's to process * 954 * E index for the next empty IBF (input to ring) * 955 * F index for the next available IBF (ring output) * 956 * * 957 * 10 Call Back Needed Interrupt handler scratch * 958 * 11 Used by FIFO output IBF routines for memory parity error checking * 959 * * 960 * 1F Passes the last halt address from the halt to the initialization code * 961 * * 962 ***************************************************************************************************** 963 TITLE.MAC Power-up initialization 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 24 PPU5/REV 26 microcode File# 0 Power-up initialization 964 ***************************************************************************************************** 965 * * 966 * INITIALIZE * 967 * * 968 * The PPU performs the following tasks upon initialization. * 969 * -It first waits for the PFW signal to become inactive before continuing. * 970 * -The BUSER signal is then cleared. * 971 * -PPU internal status (SCR6) is cleared. * 972 * -Assert that the self-test hasn't been run yet. * 973 * -Clear data output enables, and enable flags (SCR9). * 974 * -WRU 0 is set up. This is the device type and micro-code level. * 975 * -RFI, INT, all bus control bits, and the interrupt poll response, are * 976 * cleared. * 977 * -The interrupt mask is loaded with an initial value of 11001111. * 978 * -Load the memory fetch interrupt address in the interrupt vector buffer at * 979 * memory location 111. * 980 * -The interrupt address for CBN's is loaded into the interrupt vector buffer * 981 * at memory location 011. * 982 * -The following tasks are performed on each PPU port starting with port 0. * 983 * 1) The port flags are cleared * 984 * 2) Both the initial port status and status2 are set to their initial * 985 * condition * 986 * 3) PBITLOW, and PBITHIGH are set. They are used to mask out three of * 987 * the four ports during either a disable handshake, or a controller * 988 * reset respectively. * 989 * 4) Set up the interrupt masks for each port. * 990 * 5) initialize the port priority scheme with the following order. 3,0,1,2 * 991 * - The idle loop is invoked at this point. * 992 * * 993 ***************************************************************************************************** 994 0000 995 ORG #000 996 000 D8311C00633F00001001 997 NOP START wait for things to se 998 001 D8311C00633F00001002 999 START NOP 002 58311C00633F00001003 1000 NOP 003 D8311C00633F00001004 1001 NOP 004 58311C00633F00001005 1002 NOP 005 D8311C00633F00001008 1003 PFWCHECK 1004 STARTSKP 006 4FF31C00637900061006 1004$ WSTE0000 LIT SCR1F * * ****** wasted ****** 007 D8130F0072FF80001008 1005 PFWSTILL SCR0 AND LIT PFWNOT SKIP PFWCHECK Wait for PFW to go aw 1006 >>>>>>>>>>>>>>>>>>>>> 008 58331C00653900001007 1007 >PFWCHECK SBST SCR0 PFWSTILL still PFW, check again 009 58331C00633B0000100A 1008 > T4 SBRST clear BUS logic 1009 >>>>>>>>>>>>>>>>>>>>> 00A 48311C0063740000100B 1010 LIT RADR 0 init RAM ADDR reg 00B D9931C0063790000100C 1011 ZERO SCR6 clear PPU Internal St 00C C8311C0063730003100D 1012 LIT INDX1 3 and setup WRU #15 00D F8131C2A63780000100E 1013 X1 ZERO RAM WRURES4A 00E 78131FAB63780000100F 1014 X1 ONES RAM WRURES4B =>SELF-TEST not ru 1015 00F 6FF30C2862F800001010 1016 X1 SCR1F RAM WRURES3A store last halt addre 010 78131C29637800001011 1017 X1 ZERO RAM WRURES3B for WRU #14 1018 011 58101C00637200001012 1019 ZERO DPOE clear the data output 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 25 PPU5/REV 26 microcode File# 0 Power-up initialization 012 5A531C00637900001013 1020 ZERO SCR9 and the data enable f 013 48311C00637300001014 1022 RESTART LIT INDX1 0 setup WRU #0 014 68331C24637830001015 1023 X1 LIT RAM WRURES1A PPUTYPE PPU Type 015 68331C256378001A1016 1024 X1 LIT RAM WRURES1B LEVEL and Micro-code Lev 016 58101C00636A00001017 1026 ZERO SBRFI clear RFI, 017 58101C00636600001018 1027 ZERO SBINT and INT, 018 58101C00637500001019 1028 ZERO SBCB clear all bus control, 019 D9D31C0063790000101A 1029 ZERO SCR7 the Interrupt Poll re 01A 4A331C006379FFCF101B 1030 LIT SCR8 INITINTS and the interrupt mask 1031 01B 48331C08637A0F70101C 1032 LIT IADR IBFIADR TWOWORDS set the memory fetch 1033 01C 5B531C0063790000101D 1034 ZERO SCRD initialize IBF parame 01D 5B931C0063790000101E 1035 ZERO SCRE 01E 5BD31C0063790000101F 1036 ZERO SCRF 01F C8331C0C637A0F101020 1037 LIT IADR CBNIADR CBNINT and set CBN interrupt 1038 1039 020 D8131C00637900001021 1040 ZERO SCR0 initialize port zero 021 C8731C00637900011022 1041 LIT SCR1 PORTLOW 022 48B31C00637900101023 1042 LIT SCR2 PORTHIGH 023 C8F31C00637900031024 1043 LIT SCR3 NUMPORTS-1 INITLOOP next port index 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 26 PPU5/REV 26 microcode File# 0 Power-up initialization 024 48310C0062F300001025 1046 INITLOOP SCR0 INDX1 address the port 025 48310C0062ED00001026 1047 SCR0 INDX2 address RBIR 026 C8331C00637C00001027 1048 X2 LIT RBIR 0 init RBIR 027 E8311C00637600001028 1049 X1 LIT DPDIR DIRINP set direction to INPUT 028 F8311C00632300001029 1050 X1 DPRST reset the Data port 029 F8131C0463780000102A 1051 X1,T4 ZERO RAM FLAGS clear the port flags 02A E8331C0563788080102B 1052 X1 LIT RAM PRTST PRTINIT set the initial port 02B E8730C0162F80000102C 1053 X1 SCR1 RAM PBITLOW setup the 'port bit' 02C 78530D8162D90000102D 1054 X1 SCR1 ADD RAM SCR1 PBITLOW (shift left 1) 02D E8311C0063630001102E 1055 X1 LIT DPRST DPRST1IN (reset the Data port 02E 68301C00637F0001102F 1056 X1,T3 LIT DPRST1IN (repeat constant for 02F 68B30C0262F800001030 1057 X1,T4 SCR2 RAM PBITHIGH 030 F893018272D900315EE0 1058 X1 SCR2 ADD RAM SCR2 PBITHIGH *+1,PUSH INDX SETPRTIM and 'interrupt mask 1059 1060 BLOCK 4,SETIMIOR 1061 >>>>>>>>>>>>>>>>>>>>> EE0 68331C03637800019EF0 1062 >SETPRTIM X1 LIT RAM PBITIM PORT0IM POP DIDNTPOP EE1 68331C03637800029EF0 1063 > X1 LIT RAM PBITIM PORT1IM POP DIDNTPOP EE2 68331C03637800049EF0 1064 > X1 LIT RAM PBITIM PORT2IM POP DIDNTPOP EE3 68331C03637800089EF0 1065 > X1 LIT RAM PBITIM PORT3IM POP DIDNTPOP 1066 >>>>>>>>>>>>>>>>>>>>> 1067 ENDBLOCK 1068 031 E8F30C0062F800001032 1069 X1 SCR3 RAM NEXTPORT set the 'next port' a 032 D8D30D8062F900011033 1070 SCR3 ADD LIT SCR3 1 increment 'next port' 033 D8D30F0062F900031034 1071 SCR3 AND LIT SCR3 NUMPORTS-1 and make wrap back to 1072 034 78131C0E637800001035 1073 X1 ZERO RAM HSW1 clear the saved port 035 F8131C0F637800001036 1074 X1 ZERO RAM LSW1 036 F8131C10637800001037 1075 X1 ZERO RAM HSW2 037 78131C11637800001038 1076 X1 ZERO RAM LSW2 1077 038 F8131C12637800001039 1078 X1 ZERO RAM BCOVERUN set the overrun detec 1079 039 78131C1563780000103A 1080 X1 ZERO RAM BCNT initialize BCNT 03A 78131C2E63780000103B 1081 X1 ZERO RAM OLDBCNT initialize old BCNT ( 03B 68331C076378FFFF103C 1082 X1 LIT RAM CLKFIX #FFFF deactivate the clock 1083 03C 58130F0072FF0003103E 1084 SCR0 AND LIT NUMPORTS-1 SKIP NOTDONE done all the ports? 1085 SKIPORG 03D 4FF31C006379003D103D 1085$ WSTE0001 LIT SCR1F * * ****** wasted ****** 1086 >>>>>>>>>>>>>>>>>>>>> 03E D8130D8062F900011024 1087 >NOTDONE SCR0 ADD LIT SCR0 1 INITLOOP no, inc index and con 03F 4A310C0062F700001040 1088 > SCR8 IMR yes, allow interrupts 1089 >>>>>>>>>>>>>>>>>>>>> 040 C9731C00637900031041 1090 LIT SCR5 NUMPORTS-1 IDLE setup the index & go 1091 TITLE.MAC IDLE loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 27 PPU5/REV 26 microcode File# 0 IDLE loop 1092 ***************************************************************************************************** 1093 * The IDLE loop * 1094 * The PPU spends all of its time here in the idle loop * 1095 * looking for things to do. All processing routines are * 1096 * called from here except for the interrupt routines which * 1097 * interrupt the idle loop to service the request. * 1098 ***************************************************************************************************** 1099 041 D9130D8062F900013042 1100 IDLE I SCR4 ADD LIT SCR4 TIMIDLE make the clock tick 042 C9700C0062F300437074 1101 I SCR5 INDX1 *+1,PUSH DOPORT process C/S port 043 F8131E84735FFBFF3044 1102 I,X1 LIT IOR RAM FLAGS CM-TIMING SKIP IDTIMING timing this port? 1103 SKIPORG 1104 >>>>>>>>>>>>>>>>>>>>> 044 D8301C00633F004570DF 1105 >IDTIMING I *+1,PUSH CKTIMOUT yes, check if time-out 045 78131E84735FEFFF3046 1106 > I,X1 LIT IOR RAM FLAGS CM-RGOB SKIP GO-byte received this 1107 >>>>>>>>>>>>>>>>>>>>> 1108 >>>>>>>>>>>>>>>>>>>>> 046 58301C00633F004770EF 1109 > I *+1,PUSH CKFIFOBZ yes, check for FIFO b 047 F8131E84735FDFFF3048 1110 > I,X1 LIT IOR RAM FLAGS CM-REOR SKIP EOR received this por 1111 >>>>>>>>>>>>>>>>>>>>> 1112 >>>>>>>>>>>>>>>>>>>>> 048 58301C00633F004970F9 1113 > I *+1,PUSH CKRUNING yes, check if FIFO ru 049 70331C1563590000304A 1114 > I,X1 RAM SCR0 BCNT get current byte count 1115 >>>>>>>>>>>>>>>>>>>>> 1116 >>>>>>>>>>>>>>>>>>>>> 04A F8130D0762D90000304B 1117 > I,X1 SCR0 SUB RAM SCR0 CLKFIX less clock fix value 04B 58130E8072FF7FFF304C 1118 > I SCR0 IOR LIT #7FFF SKIP check for fixin' need 1119 >>>>>>>>>>>>>>>>>>>>> 1120 >>>>>>>>>>>>>>>>>>>>> 04C 78131F05735F0001304E 1121 > I,X1 LIT AND RAM PRTST DMADIR SKIP CLKDIRT test direction for fi 04D F8331C00613900003051 1122 >CLKLFX I,X1 PTST SCR0 CKFORDPE no clk fix, get data 1123 >>>>>>>>>>>>>>>>>>>>> 1124 >>>>>>>>>>>>>>>>>>>>> 04E 59130D8062F900183050 1125 >CLKDIRT I SCR4 ADD LIT SCR4 TIMBYRD CLKQFX overhead count for re 04F 59130D8062F9000C3050 1126 > I SCR4 ADD LIT SCR4 TIMBYWR CLKQFX overhead count for wr 1127 >>>>>>>>>>>>>>>>>>>>> 050 78131C8763580200304D 1128 CLKQFX I,X1 LIT RSUB RAM RAM CLKFIX TIMBYTC CLKLFX bytes accounted for 1129 STARTSKP 051 58130E8072FFFBFF3052 1130 CKFORDPE I SCR0 IOR LIT CM-PRTPE SKIP ISDPE port Parity Error? 1131 >>>>>>>>>>>>>>>>>>>>> 052 78131E85635820003053 1132 >ISDPE I,X1 LIT IOR RAM RAM PRTST DPPE yes, record it 053 D9D30E8072FF00003055 1133 > I SCR7 IOR LIT 0 SKIP *+2 is interrupt already 1134 >>>>>>>>>>>>>>>>>>>>> 1135 >>>>>>>>>>>>>>>>>>>>> 054 D8301C00633F005571A7 1136 > I *+1,PUSH CKBCINT no, check for INT 055 DB530E8072FF00003056 1137 > I SCRD IOR LIT 0 SKIP BUS input ready? 1138 >>>>>>>>>>>>>>>>>>>>> 1139 >>>>>>>>>>>>>>>>>>>>> 056 CBF00C0062F3005771B3 1140 > I SCRF INDX1 *+1,PUSH CKLEGAL yes, go process 057 58331C00653900001058 1141 > SBST SCR0 CKBUSACT get the S-BUS status 1142 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 28 PPU5/REV 26 microcode File# 0 IDLE loop 1144 ***************************************************************************************************** 1145 * This routine checks out bus activity. If SCRB (the bus transfer * 1146 * counter) value is different than the value saved in SCRA the last time * 1147 * the subroutine ran, then the RTO timer is reset. Also, if the byte * 1148 * count (BCNT) for the current port is different than the value copied * 1149 * into OLDBCNT the last time this subroutine ran, then the RTO timer will * 1150 * be reset. If all the BUSACTIV bits (RTO and RFR) are clear, then this * 1151 * subroutine will exit immediately after turning off the RTO timer. If * 1152 * the RTO timer times out, then this subroutine will jump to the proper * 1153 * error routine. If the RTO timer is active, it will be decremented by * 1154 * this subroutine once for each time this subroutine runs until it is * 1155 * either turned off, reset, or timed out. * 1156 ***************************************************************************************************** 1157 058 EAF30C2C62F800003059 1158 CKBUSACT I,X1 SCRB RAM TEMP save the current BUS 059 D8130E8072FFF5FF305B 1159 I SCR0 IOR LIT BUSACTIV SKIP ISBUSACT is the BUS active? 1160 SKIPORG 1161 >>>>>>>>>>>>>>>>>>>>> 05A 59930F0062F9FD00306C 1162 > I SCR6 AND LIT SCR6 #FF00-SOPBTO GETBSTAT no, clear any timer 05B D9934F0072FF0200105C 1163 >ISBUSACT STC SCR6 AND LIT SOPBTO SKIP NOTIMING yes, are we timing ye 1164 >>>>>>>>>>>>>>>>>>>>> 1165 >>>>>>>>>>>>>>>>>>>>> 05C 59930E8062F9020C3066 1166 >NOTIMING I SCR6 IOR LIT SCR6 SOPBTO+BUSTO NOBUSTO no, start one and exit 05D 3A938D2C72DF0000105E 1167 > TWC,CST,X1 SCRA SUB RAM TEMP #0000 SKIP NEWTRANS new transfer yet? 1168 >>>>>>>>>>>>>>>>>>>>> 1169 >>>>>>>>>>>>>>>>>>>>> 05E C9B31C002379000C3066 1170 >NEWTRANS I LIT SCR6,L BUSTO NOBUSTO yes, reset the time-o 05F F8131F05735F80003061 1171 > I,X1 LIT AND RAM PRTST BTWREC SKIP CKBCACTV is port active ? 1172 >>>>>>>>>>>>>>>>>>>>> 1173 >>>>>>>>>>>>>>>>>>>>> 060 59930D8022F9FFFF3063 1174 > I SCR6 ADD LIT SCR6,L -1 CKBUSTO no, check time-out 061 F0735C15635900001062 1175 >CKBCACTV X1,STC RAM SCR1 BCNT yes, what about BC ? 1176 >>>>>>>>>>>>>>>>>>>>> 062 B8538D2E72DF00001065 1177 TWC,CST,X1 SCR1 SUB RAM OLDBCNT #0000 SKIP BCACTIV any BC changes ? 063 59930F0072FF00FF3066 1178 CKBUSTO I SCR6 AND LIT #FF SKIP NOBUSTO time-out? 1179 SKIPORG 1180 >>>>>>>>>>>>>>>>>>>>> 064 59930D8022F9FFFF3063 1181 > I SCR6 ADD LIT SCR6,L -1 CKBUSTO no, check timeout 065 E8730C2E62F80000305E 1182 >BCACTIV I,X1 SCR1 RAM OLDBCNT NEWTRANS yes, save BC 'state' 1183 >>>>>>>>>>>>>>>>>>>>> 1184 SKIPORG 1185 >>>>>>>>>>>>>>>>>>>>> 066 F2B31C2C63590000306C 1186 >NOBUSTO I,X1 RAM SCRA TEMP GETBSTAT save the current coun 067 D8130F0072FF08001068 1187 > SCR0 AND LIT RTOIN SKIP yes, RTO? 1188 >>>>>>>>>>>>>>>>>>>>> 1189 >>>>>>>>>>>>>>>>>>>>> 068 58331C006539006B5308 1190 > SBST SCR0 RESERR,P RESGODIE Response time-out, go 069 D8331C006539006A5307 1191 > SBST SCR0 RTOERR,P RTOGODIE RTO time-out, go DIE! 1192 >>>>>>>>>>>>>>>>>>>>> 1193 1194 RTOERR HALT Bus Timer Routine Detected a RTO time-out Error 06A 4FF31C006379006A106A 1194$ RTOERR LIT SCR1F * * Bus Timer Routine Det 1195 RESERR HALT Bus Timer Routine Detected a Response time-out Error 06B 4FF31C006379006B106B 1195$ RESERR LIT SCR1F * * Bus Timer Routine Det 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 29 PPU5/REV 26 microcode File# 0 IDLE loop 06C D8331C0065390000306D 1197 GETBSTAT I SBST SCR0 get the S-BUS status 06D 58130F0072FF8000306E 1198 I SCR0 AND LIT PFWNOT SKIP ISPFW and check for PFW 1199 SKIPORG 1200 >>>>>>>>>>>>>>>>>>>>> 06E D9930E8062F901003070 1201 >ISPFW I SCR6 IOR LIT SCR6 SOPPFW *+2 yes, note it 06F 59930F0072FF01003070 1202 > I SCR6 AND LIT SOPPFW SKIP has it happened alrea 1203 >>>>>>>>>>>>>>>>>>>>> 1204 >>>>>>>>>>>>>>>>>>>>> 070 71731C00635900003041 1205 > I,X1 RAM SCR5 NEXTPORT IDLE no, get next port & l 071 D8331C00653900001072 1206 > SBST SCR0 yes, get status & go 1207 >>>>>>>>>>>>>>>>>>>>> 072 DAD31C0063790073533E 1208 ZERO SCRB PFWWAIT,P SAVEIBF signal no error 1209 1210 PFWWAIT HALT Waiting for PFW to go away 073 4FF31C00637900731073 1210$ PFWWAIT LIT SCR1F * * Waiting for PFW to go 1211 TITLE.MAC Command/Status Port processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 30 PPU5/REV 26 microcode File# 0 Command/Status Port processor 1212 ***************************************************************************************************** 1213 * The timer in SCR1 has the effect of limiting the number of times * 1214 * this subroutine will loop before returning back to the idle loop. * 1215 * This subroutine is responsible for (amongst other things) timing * 1216 * how long before the CBN interrupts will be turned back on. * 1217 ***************************************************************************************************** 1218 074 48731C00637900053075 1219 DOPORT I LIT SCR1 5 counter for fast C/S 075 F8331C00613900003076 1220 DOPORT1 I,X1 PTST SCR0 get the port status 076 F0F31C04635900003077 1221 I,X1 RAM SCR3 FLAGS and the C/S state 077 C8F3040072FF00003ED0 1222 I SCR3 DB4 DOPORTAB then branch 1224 BLOCK 16 1225 >>>>>>>>>>>>>>>>>>>>> ED0 78130F0072FF20003078 1226 >DOPORTAB I,X1 SCR0 AND LIT PRTCI SKIP NEWNOTCI got a byte coming in? ED1 78130F0072FF2000307B 1227 > I,X1 SCR0 AND LIT PRTCI SKIP NEWISCI new byte input comple ED2 F8130F0072FF2000307C 1228 > I,X1 SCR0 AND LIT PRTCI SKIP NOTCI next byte starting? ED3 F8130F0072FF2000307F 1229 > I,X1 SCR0 AND LIT PRTCI SKIP ISCI next byte input compl 1230 > HALT should never get here ED4 4FF31C0063790ED41ED4 1230$> LIT SCR1F * * should never get here 1231 > HALT should never get here ED5 4FF31C0063790ED51ED5 1231$> LIT SCR1F * * should never get here 1232 > HALT should never get here ED6 4FF31C0063790ED61ED6 1232$> LIT SCR1F * * should never get here ED7 F8130F0072FF10003080 1233 > I,X1 SCR0 AND LIT PRTFREE SKIP RESBUSY response completed? ED8 78130F0072FF10003082 1234 > I,X1 SCR0 AND LIT PRTFREE SKIP BUSY ready to output anoth 1235 > HALT should never get here ED9 4FF31C0063790ED91ED9 1235$> LIT SCR1F * * should never get here 1236 > HALT should never get here EDA 4FF31C0063790EDA1EDA 1236$> LIT SCR1F * * should never get here 1237 > HALT should never get here EDB 4FF31C0063790EDB1EDB 1237$> LIT SCR1F * * should never get here EDC 58311C00633F00003089 1238 > I DOPEXIT1 port DEAD EDD 58311C00633F00003089 1239 > I DOPEXIT1 port TIMED-OUT EDE F8130F0072FF20003085 1240 > I,X1 SCR0 AND LIT PRTCI SKIP RESISCI response input comple EDF F8130F0072FF20003086 1241 > I,X1 SCR0 AND LIT PRTCI SKIP RESNOTCI response coming in? 1242 >>>>>>>>>>>>>>>>>>>>> 1243 ENDBLOCK 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 31 PPU5/REV 26 microcode File# 0 Command/Status Port processor 1245 ***************************************************************************************************** 1246 * * 1247 * Input States * 1248 * * 1249 ***************************************************************************************************** 1251 SKIPORG 1252 >>>>>>>>>>>>>>>>>>>>> 078 58311C00633F00003089 1253 >NEWNOTCI I DOPEXIT1 not yet, wait 079 F8311C0063210000108B 1254 > X1 CSSFO NXTSTATE set FLAG OUT & inc st 1255 >>>>>>>>>>>>>>>>>>>>> 1257 >>>>>>>>>>>>>>>>>>>>> 07A D8530D8072F9FFFF3088 1258 > I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wa 07B F8131E0463580010308C 1259 >NEWISCI I,X1 LIT XOR RAM RAM FLAGS #10 CSINPRDY completed, go process 1260 >>>>>>>>>>>>>>>>>>>>> 1262 >>>>>>>>>>>>>>>>>>>>> 07C D8530D8072F9FFFF3088 1263 >NOTCI I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not yet, wait 07D F8311C0063210000108B 1264 > X1 CSSFO NXTSTATE set FLAG OUT & inc st 1265 >>>>>>>>>>>>>>>>>>>>> 1267 >>>>>>>>>>>>>>>>>>>>> 07E D8530D8072F9FFFF3088 1268 > I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wa 07F 78131E046358001030A0 1269 >ISCI I,X1 LIT XOR RAM RAM FLAGS #10 INPISRDY completed, go process 1270 >>>>>>>>>>>>>>>>>>>>> 1272 >>>>>>>>>>>>>>>>>>>>> 080 D8530D8072F9FFFF3088 1273 >RESBUSY I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wa 081 D8311C00633F000030A5 1274 > I ENDINP completed, go clean up 1275 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 32 PPU5/REV 26 microcode File# 0 Command/Status Port processor 1277 ***************************************************************************************************** 1278 * * 1279 * Output States * 1280 * * 1281 ***************************************************************************************************** 1283 >>>>>>>>>>>>>>>>>>>>> 082 D8530D8072F9FFFF3088 1284 >BUSY I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wa 083 58311C00633F000030C7 1285 > I CKCREAD controller read or wr 1286 >>>>>>>>>>>>>>>>>>>>> 1288 >>>>>>>>>>>>>>>>>>>>> 084 D8530D8072F9FFFF3088 1289 > I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not completed yet, wa 085 D8311C00633F000030CF 1290 >RESISCI I ENDOUT completed, go check r 1291 >>>>>>>>>>>>>>>>>>>>> 1293 >>>>>>>>>>>>>>>>>>>>> 086 D8530D8072F9FFFF3088 1294 >RESNOTCI I SCR1 ADD LIT SCR1 -1 SKIP DOPEXIT not yet, wait 087 F8311C0063210000108B 1295 > X1 CSSFO NXTSTATE set FLAG OUT & inc st 1296 >>>>>>>>>>>>>>>>>>>>> 1298 >>>>>>>>>>>>>>>>>>>>> 088 4A310C0062F700001075 1299 >DOPEXIT SCR8 IMR DOPORT1 update CBN int mask-t 089 4A310C0062F70000108A 1300 >DOPEXIT1 SCR8 IMR C/S port too slow - t 1301 >>>>>>>>>>>>>>>>>>>>> 08A D8301C00633F00009EF0 1302 POP DIDNTPOP insure no ints after 1303 08B 78131E04635800103074 1304 NXTSTATE I,X1 LIT XOR RAM RAM FLAGS #10 DOPORT increment C/S state & 1305 TITLE.MAC Command/Status Input processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 33 PPU5/REV 26 microcode File# 0 Command/Status Input processor 1306 ***************************************************************************************************** 1307 * A new byte is available on the CS path. Read it in * 1308 * and set up the state to indicate that we are inputting. * 1309 ***************************************************************************************************** 1310 08C 78331C0061B90000108D 1311 CSINPRDY X1 CSIN SCR0 read byte into scratch 08D 78130F00E2F900FF308F 1312 I,X1 SCR0 AND,X LIT SCR0 #FF CKTIMER (hold index for CSIN) 1313 STARTSKP 08E 4FF31C006379008E108E 1313$ WSTE0002 LIT SCR1F * * ****** wasted ****** 08F F8131F04735F04003090 1314 CKTIMER I,X1 LIT AND RAM FLAGS TIMING SKIP TIMEROFF Now timing? 1315 >>>>>>>>>>>>>>>>>>>>> 090 F9130D8962F8053C3091 1316 >TIMEROFF I,X1 SCR4 ADD LIT RAM CNTDOWN TIMECNST no, set one up 091 F8131E84435805203092 1317 > I,X1 LIT IOR RAM RAM,H FLAGS STARTINP set C/S state and DOI 1318 >>>>>>>>>>>>>>>>>>>>> 092 E8331C04237805203093 1319 I,X1 LIT RAM,L FLAGS STARTINP 093 78130EACE2F800003094 1320 I,X1 SCR0 IOR,X LIT RAM TEMP 0 & check for legal 1st 094 F0F31C2C635900003095 1321 I,X1 RAM SCR3 TEMP 095 D9130D8062F900043096 1322 I SCR4 ADD LIT SCR4 TIMECSIN bump clock for overhe 096 48F3040072FF00003EC0 1323 I SCR3 DB4 CK1STBYT 1325 BLOCK 16 1326 >>>>>>>>>>>>>>>>>>>>> EC0 D8311C00633F0000309C 1327 >CK1STBYT I SENDNAK illegal: send NAK EC1 D8311C00633F0000309C 1328 > I SENDNAK illegal: send NAK EC2 D8311C00633F0000309C 1329 > I SENDNAK illegal: send NAK EC3 F8130D8842F80100309B 1330 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: load status two EC4 D8311C00633F0000309C 1331 > I SENDNAK illegal: send NAK EC5 F8130D8842F801003097 1332 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INTREQ legal: interrupt requ EC6 F8130D8842F80100309B 1333 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: start data tra EC7 D8311C00633F0000309C 1334 > I SENDNAK illegal: send NAK EC8 D8311C00633F0000309C 1335 > I SENDNAK illegal: send NAK EC9 F8130D8842F80100309B 1336 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: end of record ECA F8130D8842F80100309B 1337 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: response to us ECB D8311C00633F0000309C 1338 > I SENDNAK illegal: send NAK ECC F8130D8842F80100309B 1339 > I,X1 SCR0 ADD LIT RAM,H TYPECKSM #100 INPISLEG legal: load status one ECD D8311C00633F0000309C 1340 > I SENDNAK illegal: send NAK ECE D8311C00633F0000309C 1341 > I SENDNAK illegal: send NAK ECF D8311C00633F0000309C 1342 > I SENDNAK illegal: send NAK 1343 >>>>>>>>>>>>>>>>>>>>> 1344 ENDBLOCK 1345 097 F0B31C0E635900003098 1346 INTREQ I,X1 RAM SCR2 HSW1 fix up for INTR (no s 098 E8B30C0B62F800003099 1347 I,X1 SCR2 RAM HWORD 099 F0B31C0F63590000309A 1348 I,X1 RAM SCR2 LSW1 09A E8B30C0C62F80000309B 1349 I,X1 SCR2 RAM LWORD 09B 78130F08A2F8FF003074 1350 INPISLEG I,X1 SCR0 AND,X LIT RAM,L TYPECKSM #FF00 DOPORT set count & start che 1351 1352 SKIPORG 1353 >>>>>>>>>>>>>>>>>>>>> 09C 68331C08237800F8309E 1354 >SENDNAK I,X1 LIT RAM,L TYPECKSM NAK SACKNAK 09D 68331C082378000E309E 1355 > I,X1 LIT RAM,L TYPECKSM ACK SACKNAK 1356 >>>>>>>>>>>>>>>>>>>>> 1357 09E 78101F08634200FF109F 1358 SACKNAK X1 LIT AND RAM CSOUT TYPECKSM #FF send response, 09F F8131E84635800703074 1359 I,X1 LIT IOR RAM RAM FLAGS SENDRESP DOPORT change I/O state & re 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 34 PPU5/REV 26 microcode File# 0 Command/Status Input processor 1361 ***************************************************************************************************** 1362 * An input character has become available on the C/S path. * 1363 ***************************************************************************************************** 1364 0A0 F8331C0061B9000010A1 1365 INPISRDY X1 CSIN SCR0 read input byte, 0A1 78130E0822D8000030A2 1366 I,X1 SCR0 XOR RAM RAM,L TYPECKSM fix checksum, 0A2 F8131D884358FF0030A3 1367 I,X1 LIT ADD RAM RAM,H TYPECKSM #FF00 decrement byte count & 0A3 F8D31E88E359000030A4 1368 I,X1 LIT IOR,X RAM SCR3 TYPECKSM IBIOR*2^8 branch 0A4 C8F3080072FF00003EB0 1369 I SCR3 DB0 CSIBYTE 1371 BLOCK 8,IBIOR 1372 >>>>>>>>>>>>>>>>>>>>> EB0 78131F08735F00FF309C 1373 >CSIBYTE I,X1 LIT AND RAM TYPECKSM #FF SKIP SENDNAK done, checksum OK? EB1 68330C0C22F800003074 1374 > I,X1 SCR0 RAM,L LWORD DOPORT store 4th byte & exit EB2 F8130F0CC2F8FFFF3074 1375 > I,X1 SCR0 AND,X LIT RAM,H LWORD #FFFF DOPORT store 3rd byte & exit EB3 E8330C0B22F800003074 1376 > I,X1 SCR0 RAM,L HWORD DOPORT store 2nd byte & exit EB4 78130F0BC2F8FFFF3074 1377 > I,X1 SCR0 AND,X LIT RAM,H HWORD #FFFF DOPORT store 1st byte & exit 1378 > HALT should never get here EB5 4FF31C0063790EB51EB5 1378$> LIT SCR1F * * should never get here 1379 > HALT should never get here EB6 4FF31C0063790EB61EB6 1379$> LIT SCR1F * * should never get here 1380 > HALT should never get here EB7 4FF31C0063790EB71EB7 1380$> LIT SCR1F * * should never get here 1381 >>>>>>>>>>>>>>>>>>>>> 1382 ENDBLOCK 0A5 78131F046358FC0030A6 1384 ENDINP I,X1 LIT AND RAM RAM FLAGS CLRFLAGS signal no activity th 0A6 78131F08635900FF30A7 1385 I,X1 LIT AND RAM SCR0 TYPECKSM #FF get the response we s 0A7 78130DAC62F8FFF230A8 1386 I,X1 SCR0 ADD LIT RAM TEMP -ACK & check it 1387 0A8 F8131EAC735F000030AB 1388 I,X1 LIT IOR RAM TEMP 0 SKIP CKWAIT did we send ACK or NA 1389 SKIPORG 0A9 4FF31C00637900A910A9 1389$ WSTE0003 LIT SCR1F * * ****** wasted ****** 1390 >>>>>>>>>>>>>>>>>>>>> 0AA F8D31F08E359FF0030AE 1391 > I,X1 LIT AND,X RAM SCR3 TYPECKSM #FF00 GOCKRESP ACK, good transfer-pr 0AB F8131F04735F080030AC 1392 >CKWAIT I,X1 LIT AND RAM FLAGS WAITING SKIP NOWAIT NAK, bad transfer-wai 1393 >>>>>>>>>>>>>>>>>>>>> 1394 >>>>>>>>>>>>>>>>>>>>> 0AC 78121F046358FBFFBEF0 1395 >NOWAIT IP,X1 LIT AND RAM RAM FLAGS CM-TIMING POP DIDNTPOP no, clear time-out & 0AD D8321C00633F0000BEF0 1396 > IP POP DIDNTPOP yes, just exit 1397 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 35 PPU5/REV 26 microcode File# 0 Command/Status Input processor 0AE 48F3040072FF00AB7EA0 1399 GOCKRESP I SCR3 CKWAIT,P DB4 CKRESP ACK, good transfer-pr 1401 BLOCK 16 1402 >>>>>>>>>>>>>>>>>>>>> 1403 >CKRESP HALT should never get here EA0 4FF31C0063790EA01EA0 1403$>CKRESP LIT SCR1F * * should never get here 1404 > HALT should never get here EA1 4FF31C0063790EA11EA1 1404$> LIT SCR1F * * should never get here 1405 > HALT should never get here EA2 4FF31C0063790EA21EA2 1405$> LIT SCR1F * * should never get here EA3 F0331C0B6359000030B2 1406 > I,X1 RAM SCR0 HWORD RLSW2 load status word #2 1407 > HALT should never get here EA4 4FF31C0063790EA41EA4 1407$> LIT SCR1F * * should never get here EA5 F8131E85635800083EAC 1408 > I,X1 LIT IOR RAM RAM PRTST CTLRINTR LDSTATUS controller int, load EA6 78131E85735F7FFB30B6 1409 > I,X1 LIT IOR RAM PRTST #FFFF BAND BTWRECOE SKIP ISBTWREC GO-byte, OK? 1410 > HALT should never get here EA7 4FF31C0063790EA71EA7 1410$> LIT SCR1F * * should never get here 1411 > HALT should never get here EA8 4FF31C0063790EA81EA8 1411$> LIT SCR1F * * should never get here EA9 F8131E85735F7FFF30BA 1412 > I,X1 LIT IOR RAM PRTST #FFFF BAND (CM-BTWREC) SKIP NOTBTREC EOR, OK? EAA 78131F04735F080030C2 1413 > I,X1 LIT AND RAM FLAGS WAITING SKIP RESPONSE response, waiting for 1414 > HALT should never get here EAB 4FF31C0063790EAB1EAB 1414$> LIT SCR1F * * should never get here EAC F0331C0B6359000030AF 1415 >LDSTATUS I,X1 RAM SCR0 HWORD RLSW1 load status word #1 1416 > HALT should never get here EAD 4FF31C0063790EAD1EAD 1416$> LIT SCR1F * * should never get here 1417 > HALT should never get here EAE 4FF31C0063790EAE1EAE 1417$> LIT SCR1F * * should never get here 1418 > HALT should never get here EAF 4FF31C0063790EAF1EAF 1418$> LIT SCR1F * * should never get here 1419 >>>>>>>>>>>>>>>>>>>>> 1420 ENDBLOCK 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 36 PPU5/REV 26 microcode File# 0 Command/Status Input processor 0AF E8330C0E62F8000030B0 1422 RLSW1 I,X1 SCR0 RAM HSW1 0B0 70331C0C6359000030B1 1423 I,X1 RAM SCR0 LWORD 0B1 68320C0F62F80000BEF0 1424 I,X1 SCR0 RAM LSW1 POP DIDNTPOP 0B2 E8330C1062F8000030B3 1426 RLSW2 I,X1 SCR0 RAM HSW2 0B3 70331C0C6359000030B4 1427 I,X1 RAM SCR0 LWORD 0B4 68320C1162F80000BEF0 1428 I,X1 SCR0 RAM LSW2 POP DIDNTPOP 1430 SKIPORG 0B5 4FF31C00637900B510B5 1430$ WSTE0004 LIT SCR1F * * ****** wasted ****** 1431 >>>>>>>>>>>>>>>>>>>>> 0B6 78121E8563580402BEF0 1432 >ISBTWREC I,X1 LIT IOR RAM RAM PRTST CONFUSED POP DIDNTPOP no, cockpit error 0B7 78131F05735F000130B8 1433 > I,X1 LIT AND RAM PRTST DMADIR SKIP yes, is read or write? 1434 >>>>>>>>>>>>>>>>>>>>> 1435 >>>>>>>>>>>>>>>>>>>>> 0B8 78121E8563580402BEF0 1436 > I,X1 LIT IOR RAM RAM PRTST CONFUSED POP DIDNTPOP read, cockpit error 0B9 78121E8463581000BEF0 1437 > I,X1 LIT IOR RAM RAM FLAGS RGOB POP DIDNTPOP set for processing & 1438 >>>>>>>>>>>>>>>>>>>>> 1440 SKIPORG 1441 >>>>>>>>>>>>>>>>>>>>> 0BA 78121E8563580402BEF0 1442 >NOTBTREC I,X1 LIT IOR RAM RAM PRTST CONFUSED POP DIDNTPOP no, cockpit error 0BB F8131F05735F000130BC 1443 > I,X1 LIT AND RAM PRTST DMADIR SKIP ISEOREAD OK, end of read? 1444 >>>>>>>>>>>>>>>>>>>>> 1445 >>>>>>>>>>>>>>>>>>>>> 0BC F8131E856358800030C1 1446 >ISEOREAD I,X1 LIT IOR RAM RAM PRTST BTWREC SETREOR yes, set status 0BD 78131F05735F008030BE 1447 > I,X1 LIT AND RAM PRTST DMANBZ SKIP STILLBZ write, is DMA still b 1448 >>>>>>>>>>>>>>>>>>>>> 1449 >>>>>>>>>>>>>>>>>>>>> 0BE 78131E856358808230C0 1450 >STILLBZ I,X1 LIT IOR RAM RAM PRTST ENDWRITE *+2 yes, DMA was busy 0BF 78131E856358800030C0 1451 > I,X1 LIT IOR RAM RAM PRTST BTWREC no, DMA wasn't busy 1452 >>>>>>>>>>>>>>>>>>>>> 0C0 F8131F056358FFFB3247 1453 I,X1 LIT AND RAM RAM PRTST CM-DMAOE ABORTPRT clear output enable s 0C1 78121E8463582000BEF0 1455 SETREOR I,X1 LIT IOR RAM RAM FLAGS REOR POP DIDNTPOP set for EOR processing 1457 SKIPORG 1458 >>>>>>>>>>>>>>>>>>>>> 0C2 D8321C00633F0000BEF0 1459 >RESPONSE IP POP DIDNTPOP no, ignore response 0C3 F0331C0B635900C471C2 1460 > I,X1 RAM SCR0 HWORD *+1,PUSH WTFORBUS yes, wait for BUS & 1461 >>>>>>>>>>>>>>>>>>>>> 0C4 70301C0C6351000010C5 1462 X1 RAM SBLC LWORD respond to CPU 0C5 F0311C0D6355000010C6 1463 X1 RAM SBCB RESPTO 0C6 F8131F046358F3FF9EF0 1464 X1 LIT AND RAM RAM FLAGS CLRWAIT POP DIDNTPOP signal not waiting & 1465 TITLE.MAC Command/Status output 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 37 PPU5/REV 26 microcode File# 0 Command/Status output 1466 STARTSKP 0C7 78131F08735F800030C8 1467 CKCREAD I,X1 LIT AND RAM TYPECKSM CRDTEST SKIP NOTCREAD controller read or w 1468 >>>>>>>>>>>>>>>>>>>>> 0C8 F8D31E88E359080030CA 1469 >NOTCREAD I,X1 LIT IOR,X RAM SCR3 TYPECKSM CWIOR*2^8 *+2 Write 0C9 78D31E88E359040030CB 1470 > I,X1 LIT IOR,X RAM SCR3 TYPECKSM CRIOR*2^8 *+2 Read 1471 >>>>>>>>>>>>>>>>>>>>> 0CA 48F3080072FF00003EB8 1472 I SCR3 DB0 CWRTAB 0CB 48F3080072FF00003EE4 1473 I SCR3 DB0 CRDTAB 1475 BLOCK 8,CWIOR 1476 >>>>>>>>>>>>>>>>>>>>> EB8 78131F0A635900FF30CC 1477 >CWRTAB I,X1 LIT AND RAM SCR0 ADDRESS #FF INCSTATE transmit address EB9 78131F0BE359FF0030CC 1478 > I,X1 LIT AND,X RAM SCR0 HWORD #FF00 INCSTATE transmit byte 0 EBA F8131F0B635900FF30CC 1479 > I,X1 LIT AND RAM SCR0 HWORD #FF INCSTATE transmit byte 1 EBB F8131F0CE359FF0030CC 1480 > I,X1 LIT AND,X RAM SCR0 LWORD #FF00 INCSTATE transmit byte 2 EBC 78131F0C635900FF30CC 1481 > I,X1 LIT AND RAM SCR0 LWORD #FF INCSTATE transmit byte 3 EBD 58131C006379000030CC 1482 > I ZERO SCR0 INCSTATE transmit zero EBE F8131F08635900FF30CC 1483 > I,X1 LIT AND RAM SCR0 TYPECKSM #FF INCSTATE transmit checksum EBF 78131E84635800F03074 1484 > I,X1 LIT IOR RAM RAM FLAGS RECVRESP DOPORT change state to accep 1485 >>>>>>>>>>>>>>>>>>>>> 1486 ENDBLOCK 1488 BLOCK 4,CRIOR 1489 >>>>>>>>>>>>>>>>>>>>> EE4 78131F0A635900FF30CC 1490 >CRDTAB I,X1 LIT AND RAM SCR0 ADDRESS #FF INCSTATE transmit address EE5 58131C006379000030CC 1491 > I ZERO SCR0 INCSTATE transmit zero EE6 F8131F08635900FF30CC 1492 > I,X1 LIT AND RAM SCR0 TYPECKSM #FF INCSTATE transmit checksum EE7 78131E84635800F03074 1493 > I,X1 LIT IOR RAM RAM FLAGS RECVRESP DOPORT change state to accep 1494 >>>>>>>>>>>>>>>>>>>>> 1495 ENDBLOCK 0CC E8310C0062E2000010CD 1497 INCSTATE X1 SCR0 CSOUT send byte, 0CD 78130E0822D8000030CE 1498 I,X1 SCR0 XOR RAM RAM,L TYPECKSM fix checksum, 0CE 78131D88435801003074 1499 I,X1 LIT ADD RAM RAM,H TYPECKSM #100 DOPORT inc output state & re 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 38 PPU5/REV 26 microcode File# 0 Command/Status output 0CF F8331C0061B9000010D0 1501 ENDOUT X1 CSIN SCR0 get response 0D0 78130F0062F900FF30D1 1502 I,X1 SCR0 AND LIT SCR0 #FF (need to hold X1 for 0D1 F8130DAC62F8FFF230D2 1503 I,X1 SCR0 ADD LIT RAM TEMP -ACK & check for ACK 0D2 F8131EAC735F000030D5 1504 I,X1 LIT IOR RAM TEMP 0 SKIP WASNAK ACK or NAK? 1505 SKIPORG 0D3 4FF31C00637900D310D3 1505$ WSTE0005 LIT SCR1F * * ****** wasted ****** 1506 >>>>>>>>>>>>>>>>>>>>> 0D4 F8131F046358FC0030AB 1507 > I,X1 LIT AND RAM RAM FLAGS CLRFLAGS CKWAIT ACK, clear activity t 0D5 78131E84735FFFF030D7 1508 >WASNAK I,X1 LIT IOR RAM FLAGS #FFF0 SKIP YESRETRY NAK, any retries left? 1509 >>>>>>>>>>>>>>>>>>>>> 1510 >>>>>>>>>>>>>>>>>>>>> 0D6 F0331C046359000030DE 1511 > I,X1 RAM SCR0 FLAGS SETPDEAD no, port DEAD- save F 0D7 F8131F08735F800030D8 1512 >YESRETRY I,X1 LIT AND RAM TYPECKSM CRDTEST SKIP ISWRITE yes, read? 1513 >>>>>>>>>>>>>>>>>>>>> 1514 >>>>>>>>>>>>>>>>>>>>> 0D8 68311C006362009610DA 1515 >ISWRITE X1 LIT CSOUT CTLRWR *+2 no, restart write 0D9 68311C006362006210DB 1516 > X1 LIT CSOUT CTLRRD *+2 yes, restart read 1517 >>>>>>>>>>>>>>>>>>>>> 0DA 68331C086378006930DC 1518 I,X1 LIT RAM TYPECKSM CWRSTART *+2 0DB 68331C086378809D30DC 1519 I,X1 LIT RAM TYPECKSM CRDSTART 0DC F8131F046359000F30DD 1520 I,X1 LIT AND RAM SCR0 FLAGS #F decrement the retry c 0DD F8120D8422F8007FBEF0 1521 I,X1 SCR0 ADD LIT RAM,L FLAGS RESTRDWR-1 POP DIDNTPOP setup the handshake s 0DE 68331C04637840C030E7 1523 SETPDEAD I,X1 LIT RAM FLAGS SETDEAD CKINPTO set DEAD & check for 1524 TITLE.MAC Timer processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 39 PPU5/REV 26 microcode File# 0 Timer processor 1525 ***************************************************************************************************** 1526 * * 1527 * Check Time Out routine. * 1528 * This routine decrements the timeout count for the indexed port. * 1529 * We set up to return abnormal data if the bus timed out, except for * 1530 * the device ID entry which just returns a zero to indicate no * 1531 * device. * 1532 * * 1533 ***************************************************************************************************** 1534 0DF F9130E2C62F8FFFF30E0 1535 CKTIMOUT I,X1 SCR4 XOR LIT RAM TEMP -1 make one comp of curr 0E0 F0331C2C6359000030E1 1536 I,X1 RAM SCR0 TEMP and copy to scratch r 0E1 F8130D8962D9000030E2 1537 I,X1 SCR0 ADD RAM SCR0 CNTDOWN compare to time out v 0E2 D8130F0072FF800030E4 1538 I SCR0 AND LIT #8000 SKIP NOTIMOUT now check sign of res 1539 SKIPORG 0E3 4FF31C00637900E310E3 1539$ WSTE0006 LIT SCR1F * * ****** wasted ****** 1540 >>>>>>>>>>>>>>>>>>>>> 0E4 D8321C00633F0000BEF0 1541 >NOTIMOUT IP POP DIDNTPOP no,return 0E5 70331C046359000030E6 1542 > I,X1 RAM SCR0 FLAGS yes, save flags, 1543 >>>>>>>>>>>>>>>>>>>>> 1544 >>>>>>>>>>>>>>>>>>>>> 0E6 68331C046378C0D030E7 1545 > I,X1 LIT RAM FLAGS SETIMED clear I/O & set timed 0E7 D8130F0072FF080030E8 1546 >CKINPTO I SCR0 AND LIT WAITING SKIP NOTINPTO were we doing a read? 1547 >>>>>>>>>>>>>>>>>>>>> 1548 >>>>>>>>>>>>>>>>>>>>> 0E8 D8321C00633F0000BEF0 1549 >NOTINPTO IP POP DIDNTPOP no, return 0E9 58131C00637900EA71C2 1550 > I ZERO SCR0 *+1,PUSH WTFORBUS yes, clear response & 1551 >>>>>>>>>>>>>>>>>>>>> 1552 >>>>>>>>>>>>>>>>>>>>> 0EA 58131C006371000010EB 1553 > ZERO SBLC send to the CPU 0EB F8131E8A735F000010EC 1554 > X1 LIT IOR RAM ADDRESS 0 SKIP PPU's "Read Device ID 1555 >>>>>>>>>>>>>>>>>>>>> 1556 >>>>>>>>>>>>>>>>>>>>> 0EC 78101E0D6355001010EE 1557 > X1 LIT XOR RAM SBCB RESPTO ADATAXOR RTODELAY no, send Abnormal Data 0ED F0311C0D6355000010EE 1558 > X1 RAM SBCB RESPTO yes, send Good Data 0EE D8301C00633F00009EF0 1559 >RTODELAY POP DIDNTPOP delay for RTO, then e 1560 >>>>>>>>>>>>>>>>>>>>> 1561 TITLE.MAC GO-byte processing 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 40 PPU5/REV 26 microcode File# 0 GO-byte processing 1562 ***************************************************************************************************** 1563 * * 1564 * Check go-byte processing * 1565 * This routine looks to see if the FIFO is busy. This code * 1566 * looks like we wait until the FIFO is full then start the * 1567 * data going out to the controller. * 1568 * * 1569 ***************************************************************************************************** 1570 1571 STARTSKP 0EF 78131E85735FFF7F30F0 1572 CKFIFOBZ I,X1 LIT IOR RAM PRTST CM-DMANBZ SKIP FIFONBZ is FIFO busy? 1573 >>>>>>>>>>>>>>>>>>>>> 0F0 F8131F046358EFFF30F6 1574 >FIFONBZ I,X1 LIT AND RAM RAM FLAGS CM-RGOB LETGO no, let output go 0F1 78331C006139000030F3 1575 > I,X1 PTST SCR0 CKFULL yes, get the data por 1576 >>>>>>>>>>>>>>>>>>>>> 1577 STARTSKP 0F2 4FF31C00637900F210F2 1577$ WSTE0007 LIT SCR1F * * ****** wasted ****** 0F3 58130F0072FF080030F4 1578 CKFULL I SCR0 AND LIT PRTINT SKIP NOTFULL FIFO full yet? 1579 >>>>>>>>>>>>>>>>>>>>> 0F4 D8321C00633F0000BEF0 1580 >NOTFULL IP POP DIDNTPOP no, return 0F5 F8131F046358EFFF30F6 1581 > I,X1 LIT AND RAM RAM FLAGS CM-RGOB LETGO yes, let output go 1582 >>>>>>>>>>>>>>>>>>>>> 1583 0F6 F8131E856358000430F7 1584 LETGO I,X1 LIT IOR RAM RAM PRTST DMAOE set output enabled st 0F7 FA530E8162D9000030F8 1585 I,X1 SCR9 IOR RAM SCR9 PBITLOW enable data output 0F8 CA700C0062F200009EF0 1586 SCR9 DPOE POP DIDNTPOP & return 1587 TITLE.MAC End-Of-Record processing 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 41 PPU5/REV 26 microcode File# 0 End-Of-Record processing 1588 ***************************************************************************************************** 1589 * * 1590 * The PPU comes here from the idle loop after an * 1591 * End-Of-Record character is received from the port currently * 1592 * being checked by the idle loop. The REOR (received end of * 1593 * record) flag is only set for a port doing input (from * 1594 * controller to memory). * 1595 * * 1596 ***************************************************************************************************** 1597 1598 STARTSKP 0F9 78131F05735F008030FA 1599 CKRUNING I,X1 LIT AND RAM PRTST DMANBZ SKIP ISRUNING is FIFO running? 1600 >>>>>>>>>>>>>>>>>>>>> 0FA F8331C006139000030FE 1601 >ISRUNING I,X1 PTST SCR0 CKGOING yes, get the port sta 0FB F8131F05735F004030FD 1602 > I,X1 LIT AND RAM PRTST BCNRDY SKIP *+2 no, waiting for BCNT? 1603 >>>>>>>>>>>>>>>>>>>>> 1604 >>>>>>>>>>>>>>>>>>>>> 0FC D8321C00633F0000BEF0 1605 > IP POP DIDNTPOP yes, wait until avail 0FD 78531D96635980003111 1606 > I,X1 LIT ADD RAM SCR1 LAST -LASTBIT CUCKDONE no,do cleanup 1607 >>>>>>>>>>>>>>>>>>>>> 0FE 58130F0072FF08003100 1608 CKGOING I SCR0 AND LIT PRTINT SKIP ISGOING still interrupting? 1609 SKIPORG 0FF 4FF31C00637900FF10FF 1609$ WSTE0008 LIT SCR1F * * ****** wasted ****** 1610 >>>>>>>>>>>>>>>>>>>>> 100 D8321C00633F0000BEF0 1611 >ISGOING IP POP DIDNTPOP yes, wait till it fin 101 FA130E8362D900001102 1612 > X1 SCR8 IOR RAM SCR8 PBITIM no, disallow interrup 1613 >>>>>>>>>>>>>>>>>>>>> 102 4A310C0062F700001103 1614 SCR8 IMR 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 42 PPU5/REV 26 microcode File# 0 End-Of-Record processing 1616 ***************************************************************************************************** 1617 * * 1618 * If we get to here, the whole word part of the byte count was not * 1619 * exhausted, otherwise the FIFO input processor would have set DMANBZ (in * 1620 * PRTST) and turned off the interrupts itself. If we get to here, the * 1621 * transfer is over (EOR received) and there are not enough bytes in the * 1622 * FIFO to cause a port interrupt (i.e. less than 4 bytes in single word * 1623 * store mode or less than 8 bytes in double word store mode). This is * 1624 * sort of important, because after this we just assume there are not * 1625 * enough words in the FIFO to cause an interrupt. This assumption is used * 1626 * in a couple of places after this. * 1627 * * 1628 * If we are in single word store mode, we need to make the LAST count * 1629 * equal to 3 (the greatest number of possible bytes left in the FIFO) and * 1630 * readjust BCNT so CORBC + LAST + BCNT will still reflect the correct byte * 1631 * count. (Note that there is still a remaining number of whole words, or * 1632 * else we would have skipped over this part.) * 1633 * * 1634 * If we are in double word store mode, we need to make the LAST count * 1635 * equal to the greater of either the remaining byte count or 7 (the * 1636 * greatest number of possible bytes left in the FIFO) and readjust BCNT so * 1637 * that CORBC + LAST + BCNT will still reflect the correct byte count. * 1638 * * 1639 ***************************************************************************************************** 1640 103 F8131F13735F00081105 1641 X1 LIT AND RAM CORBC 8 SKIP EORNOT2WMODE single or double 1642 1643 SKIPORG 1644 >>>>>>>>>>>>>>>>>>>>> 104 F8131F1663597FFF3109 1645 > I,X1 LIT AND RAM SCR0 LAST #FFFF-LASTBIT EORCK2WBCNT double,calculate r 105 78131F16635900033106 1646 >EORNOT2WMODE I,X1 LIT AND RAM SCR0 LAST #0003 single,SCR0 <- residue 1647 >>>>>>>>>>>>>>>>>>>>> 1648 106 F8130D9562D800003107 1649 I,X1 SCR0 ADD RAM RAM BCNT add to BCNT 107 F8131D956358FFFD3108 1650 I,X1 LIT ADD RAM RAM BCNT -3 BCNT now correct 108 78131E96635800033113 1651 I,X1 LIT IOR RAM RAM LAST #0003 CUNDONE LAST <- 3,go finish 1652 109 F8130D9562D90000310A 1653 EORCK2WBCNT I,X1 SCR0 ADD RAM SCR0 BCNT finish calculating... 10A 78130D9362D90000310B 1654 I,X1 SCR0 ADD RAM SCR0 CORBC ...the remaining BCNT 10B F8130E8072FF0007310C 1655 I,X1 SCR0 IOR LIT 7 SKIP EOR2WBCNTGT7 remaining BCNT >7? 1656 1657 SKIPORG 1658 >>>>>>>>>>>>>>>>>>>>> 10C 68335C1623780007110F 1659 >EOR2WBCNTGT7 STC,X1 LIT RAM,L LAST #0007 EOR2WN1L yes,LAST <- 7 10D E8330C1622F80000310E 1660 > I,X1 SCR0 RAM,L LAST no,LAST <- residue 1661 >>>>>>>>>>>>>>>>>>>>> 1662 10E 68331C156378FFF83113 1663 I,X1 LIT RAM BCNT -8 CUNDONE correct BCNT,go finish 1664 10F 38138D1362D900001110 1665 EOR2WN1L TWC,CST,X1 SCR0 SUB RAM SCR0 CORBC calculate new BCNT 110 78130D9562F8FFF93113 1666 I,X1 SCR0 ADD LIT RAM BCNT -7 CUNDONE BCNT now correct,go f 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 43 PPU5/REV 26 microcode File# 0 End-Of-Record processing 1668 ***************************************************************************************************** 1669 * The PPU gets here when End-Of-Record has been received on * 1670 * this port AND there is no byte count overrun on this port AND * 1671 * FIFO not running status (DMANBZ) has been set in PRTST (i.e. * 1672 * bit 7 = 1). * 1673 ***************************************************************************************************** 1674 1675 STARTSKP 111 D8530E8072FF00003113 1676 CUCKDONE I SCR1 IOR LIT 0 SKIP CUNDONE already done? 1677 >>>>>>>>>>>>>>>>>>>>> 112 F8131E85635800B23194 1678 > I,X1 LIT IOR RAM RAM PRTST LASTBC CUCKEXT yes, check for extra 113 78331C00613900003115 1679 >CUNDONE I,X1 PTST SCR0 CUCKMT no, get the port stat 1680 >>>>>>>>>>>>>>>>>>>>> 1681 STARTSKP 114 4FF31C00637901141114 1681$ WSTE0009 LIT SCR1F * * ****** wasted ****** 115 D8130E8072FFFCFF3117 1682 CUCKMT I SCR0 IOR LIT PRTEMPTY SKIP CUNOTMT and check for FIFO em 1683 >>>>>>>>>>>>>>>>>>>>> 116 F8131E85635800823197 1684 > I,X1 LIT IOR RAM RAM PRTST EORINTR CUEXIT yes,set interrupt&exit 117 78531F1463590F003118 1685 >CUNOTMT I,X1 LIT AND RAM SCR1 SLOT #0F00 not MT,need to fetch 1686 >>>>>>>>>>>>>>>>>>>>> 118 58530E8062F980293119 1687 I SCR1 IOR LIT SCR1 (#80FB BAND READBITS) SCR1<-SBCB read comma 119 F8131E9763592000311A 1688 I,X1 LIT IOR RAM SCR0 HADDR READ1W SCR0 will go into SBHC 11A 58301C00633F011B71C2 1689 I CUNOTMTA,P WTFORBUS wait for bus free 11B 70211C1863510000111C 1690 CUNOTMTA X1,P RAM SBLC LADDR 11C 68710C0062F50000111D 1691 X1 SCR1 SBCB initiate transfer 11D C8331C08637A0F00111E 1692 LIT IADR IBFIADR EORIBF set IBF intrpt addr 11E 78D31E9663590000111F 1693 X1 LIT IOR RAM SCR3 LAST EORIOR set up for branch 11F C8F3080072FF00001E90 1694 SCR3 DB0 EORBLOCK on bytes remaining 1696 ***************************************************************************************************** 1697 * * 1698 * At this point, SCR0 <> 0 (until bus transfer completes), * 1699 * SCR1 and SCR2 are the high and low input data buffer, EORTIMER * 1700 * is the bus timer, SCR3 will be port status. The >3 byte * 1701 * branches are used when "EOR is received and no more input" * 1702 * before the byte count is exhausted (i.e. we ran through * 1703 * address ISGOING+1). * 1704 * * 1705 ***************************************************************************************************** 1706 1707 BLOCK 8,EORIOR 1708 >>>>>>>>>>>>>>>>>>>>> 1709 >EORBLOCK HALT 0 bytes,bad branch E90 4FF31C0063790E901E90 1709$>EORBLOCK LIT SCR1F * * 0 bytes,bad branch E91 68331C066378007D3120 1710 > I,X1 LIT RAM EORTIMER BUSTO2 EOR1MORE 1 bytes,set up timer E92 68331C066378007D312A 1711 > I,X1 LIT RAM EORTIMER BUSTO2 EOR2MORE 2 bytes,set up timer E93 E8331C066378007D313A 1712 > I,X1 LIT RAM EORTIMER BUSTO2 EOR3MORE 3 bytes,set up timer E94 E8331C066378007D314D 1713 > I,X1 LIT RAM EORTIMER BUSTO2 EOR4MORE >3 bytes,set up timer E95 E8331C066378007D314D 1714 > I,X1 LIT RAM EORTIMER BUSTO2 EOR4MORE >3 bytes,set up timer E96 E8331C066378007D314D 1715 > I,X1 LIT RAM EORTIMER BUSTO2 EOR4MORE >3 bytes,set up timer E97 E8331C066378007D314D 1716 > I,X1 LIT RAM EORTIMER BUSTO2 EOR4MORE >3 bytes,set up timer 1717 >>>>>>>>>>>>>>>>>>>>> 1718 ENDBLOCK 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 44 PPU5/REV 26 microcode File# 0 End-Of-Record processing 120 F8F31C00613900003121 1720 EOR1MORE I,X1 PTST SCR3 EOR1M1 get port status 1721 STARTSKP 121 58D30E8072FFFEFF3122 1722 EOR1M1 I SCR3 IOR LIT CM-PRTLOW SKIP EOR1M2 at least 2 bytes? 1723 >>>>>>>>>>>>>>>>>>>>> 122 78131E85635840003123 1724 >EOR1M2 I,X1 LIT IOR RAM RAM PRTST EXTRA >=2 bytes,set extra i 123 78131D867358FFFF3125 1725 >EOR1M3 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 1726 >>>>>>>>>>>>>>>>>>>>> 1727 >>>>>>>>>>>>>>>>>>>>> 124 D8331C00653901295308 1728 > SBST SCR0 EORRESERR1,P RESGODIE yes, go die 125 58130E8072FF00003126 1729 >EOR1M4 I,T4 SCR0 IOR LIT #0 SKIP EOR1M5 no,input yet? 1730 >>>>>>>>>>>>>>>>>>>>> 1731 >>>>>>>>>>>>>>>>>>>>> 126 58331C00633F00003123 1732 >EOR1M5 I,T4 EOR1M3 no,continue timing 127 E8331C2C637800013128 1733 > I,X1 LIT RAM TEMP 1 indicate 1 byte 1734 >>>>>>>>>>>>>>>>>>>>> 128 F8731C0040F900001184 1735 X1 DPIN SCR1,H CUNOTMT3 get byte,go do write 1736 1737 EORRESERR1 HALT Response Time-Out Detected by End-Of-Record Processor 129 4FF31C00637901291129 1737$ EORRESERR1 LIT SCR1F * * Response Time-Out Det 12A F8F31C0061390000312B 1739 EOR2MORE I,X1 PTST SCR3 EOR2M1 get port status 1740 STARTSKP 12B 58D30E8072FFFEFF312D 1741 EOR2M1 I SCR3 IOR LIT CM-PRTLOW SKIP EOR2M2 at least 2 bytes? 1742 >>>>>>>>>>>>>>>>>>>>> 12C 78131D867358FFFF3125 1743 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 12D F8331C2C60F80000112E 1744 >EOR2M2 X1 DPIN RAM TEMP >=2 bytes,read 2 bytes 1745 >>>>>>>>>>>>>>>>>>>>> 12E 78311C00633F0000312F 1746 I,X1 hold X1 & wait 1 inst 12F F8F31C00613900001131 1747 X1 PTST SCR3 EOR2M7 get port status 1748 STARTSKP 130 4FF31C00637901301130 1748$ WSTE0010 LIT SCR1F * * ****** wasted ****** 131 58D30E8072FFFCFF3132 1749 EOR2M7 I SCR3 IOR LIT PRTEMPTY SKIP EOR2M8 FIFO empty? 1750 >>>>>>>>>>>>>>>>>>>>> 132 F8131E85635840003133 1751 >EOR2M8 I,X1 LIT IOR RAM RAM PRTST EXTRA no,set extra input 133 F8131D867358FFFF3135 1752 >EOR2M3 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR2M4 yes,time out? 1753 >>>>>>>>>>>>>>>>>>>>> 1754 >>>>>>>>>>>>>>>>>>>>> 134 58331C00653901395308 1755 > SBST SCR0 EORRESERR2,P RESGODIE yes, go die 135 D8130E8072FF00003136 1756 >EOR2M4 I,T4 SCR0 IOR LIT #0 SKIP EOR2M5 no,input yet? 1757 >>>>>>>>>>>>>>>>>>>>> 1758 >>>>>>>>>>>>>>>>>>>>> 136 D8331C00633F00003133 1759 >EOR2M5 I,T4 EOR2M3 no,continue timing 137 70731C2C635900003138 1760 > I,X1 RAM SCR1 TEMP yes,2 bytes for output 1761 >>>>>>>>>>>>>>>>>>>>> 138 E8331C2C637800023184 1762 I,X1 LIT RAM TEMP 2 CUNOTMT3 indicate 2 byte,go do 1763 1764 EORRESERR2 HALT Response Time-Out Detected by End-Of-Record Processor 139 4FF31C00637901391139 1764$ EORRESERR2 LIT SCR1F * * Response Time-Out Det 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 45 PPU5/REV 26 microcode File# 0 End-Of-Record processing 13A 78F31C0061390000313B 1766 EOR3MORE I,X1 PTST SCR3 EOR3M1 get port status 1767 STARTSKP 13B D8D30E8072FFFEFF313D 1768 EOR3M1 I SCR3 IOR LIT CM-PRTLOW SKIP EOR3M2 at least 2 bytes? 1769 >>>>>>>>>>>>>>>>>>>>> 13C 78131D867358FFFF3125 1770 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 13D 78331C2C60F80000113E 1771 >EOR3M2 X1 DPIN RAM TEMP >=2 bytes,read 2 bytes 1772 >>>>>>>>>>>>>>>>>>>>> 13E F8311C00633F0000313F 1773 I,X1 hold X1 & wait 1 inst 13F 78F31C00613900001141 1774 X1 PTST SCR3 EOR3M7 get port status 1775 STARTSKP 140 4FF31C00637901401140 1775$ WSTE0011 LIT SCR1F * * ****** wasted ****** 141 58D30E8072FFFCFF3143 1776 EOR3M7 I SCR3 IOR LIT PRTEMPTY SKIP EOR3M8 FIFO empty? 1777 >>>>>>>>>>>>>>>>>>>>> 142 F8131D867358FFFF3135 1778 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR2M4 yes,time out? 143 58D30E8072FFFEFF3144 1779 >EOR3M8 I SCR3 IOR LIT CM-PRTLOW SKIP EOR3M3 no,at least 2 bytes? 1780 >>>>>>>>>>>>>>>>>>>>> 1781 >>>>>>>>>>>>>>>>>>>>> 144 78131E85635840003145 1782 >EOR3M3 I,X1 LIT IOR RAM RAM PRTST EXTRA 2 bytes,set extra inp 145 F8131D867358FFFF3147 1783 >EOR3M6 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR3M4 1 byte,time out? 1784 >>>>>>>>>>>>>>>>>>>>> 1785 >>>>>>>>>>>>>>>>>>>>> 146 D8331C006539014C5308 1786 > SBST SCR0 EORRESERR3,P RESGODIE yes, go die 147 D8130E8072FF00003148 1787 >EOR3M4 I,T4 SCR0 IOR LIT #0 SKIP EOR3M5 no,input yet? 1788 >>>>>>>>>>>>>>>>>>>>> 1789 >>>>>>>>>>>>>>>>>>>>> 148 58331C00633F00003145 1790 >EOR3M5 I,T4 EOR3M6 no,continue timing 149 70731C2C63590000314A 1791 > I,X1 RAM SCR1 TEMP yes,2 bytes for output 1792 >>>>>>>>>>>>>>>>>>>>> 14A F8B31C0040F90000114B 1793 X1 DPIN SCR2,H 3rd byte for output 14B 68331C2C637800033184 1794 I,X1 LIT RAM TEMP 3 CUNOTMT3 indicate 3 byte,go do 1795 1796 EORRESERR3 HALT Response Time-Out Detected by End-Of-Record Processor 14C 4FF31C006379014C114C 1796$ EORRESERR3 LIT SCR1F * * Response Time-Out Det 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 46 PPU5/REV 26 microcode File# 0 End-Of-Record processing 14D F8F31C0061390000314E 1798 EOR4MORE I,X1 PTST SCR3 get port status 14E D8D30E8072FFFEFF3151 1799 I SCR3 IOR LIT CM-PRTLOW SKIP EOR4M2 at least 2 bytes? 1800 SKIPORG 14F 4FF31C006379014F114F 1800$ WSTE0012 LIT SCR1F * * ****** wasted ****** 1801 >>>>>>>>>>>>>>>>>>>>> 150 78131D867358FFFF3125 1802 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR1M4 1 byte,time out? 151 78331C2C60F800001152 1803 >EOR4M2 X1 DPIN RAM TEMP >=2 bytes,read 2 bytes 1804 >>>>>>>>>>>>>>>>>>>>> 152 F8311C00633F00003153 1805 I,X1 hold X1 & wait 1 inst 153 F8F31C00613900001154 1806 X1 PTST SCR3 get port status 154 58D30E8072FFFCFF3157 1807 I SCR3 IOR LIT PRTEMPTY SKIP EOR4M8 FIFO empty? 1808 SKIPORG 155 4FF31C00637901551155 1808$ WSTE0013 LIT SCR1F * * ****** wasted ****** 1809 >>>>>>>>>>>>>>>>>>>>> 156 F8131D867358FFFF3135 1810 > I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR2M4 yes,time out? 157 D8D30E8072FFFEFF3158 1811 >EOR4M8 I SCR3 IOR LIT CM-PRTLOW SKIP EOR4M3 no,at least 2 bytes? 1812 >>>>>>>>>>>>>>>>>>>>> 1813 >>>>>>>>>>>>>>>>>>>>> 158 78131D867358FFFF315B 1814 >EOR4M3 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR4M4 2 bytes,time out? 159 F8131D867358FFFF3147 1815 >EOR4M6 I,X1,T4 LIT ADD RAM RAM EORTIMER -1 SKIP EOR3M4 1 byte,time out? 1816 >>>>>>>>>>>>>>>>>>>>> 1817 >>>>>>>>>>>>>>>>>>>>> 15A 58331C00653901655308 1818 > SBST SCR0 EORRESERR4,P RESGODIE yes, go die 15B D8130E8072FF0000315C 1819 >EOR4M4 I,T4 SCR0 IOR LIT #0 SKIP EOR4M5 no,input yet? 1820 >>>>>>>>>>>>>>>>>>>>> 1821 >>>>>>>>>>>>>>>>>>>>> 15C D8331C00633F00003159 1822 >EOR4M5 I,T4 EOR4M6 no,continue timing 15D F0331C176359015E71C2 1823 > I,X1 RAM SCR0 HADDR *+1,PUSH WTFORBUS yes,wait for BUS free 1824 >>>>>>>>>>>>>>>>>>>>> 1825 15E F0211C1863510000115F 1826 X1,P RAM SBLC LADDR 15F F0301C2C634E00001160 1827 X1 RAM SBHD TEMP 2 bytes for output 160 F8313C0060EF00001161 1828 X1,C,T2 DPIN SBLD next 2 bytes for outp 161 70311C14635500001162 1829 X1 RAM SBCB SLOT 162 F8031D98635800011163 1830 X1,P LIT ADD RAM RAM LADDR 1 calculate new address 163 78131D966358FFFC3164 1831 I,X1 LIT ADD RAM RAM LAST -4 calculate new byte co 164 78131E96735F80003166 1832 X1,I LIT IOR RAM LAST LASTBIT SKIP EOR4NOTZERO LAST = 0? 1834 EORRESERR4 HALT Response Time-Out Detected by End-Of-Record Processor 165 4FF31C00637901651165 1834$ EORRESERR4 LIT SCR1F * * Response Time-Out Det 1836 SKIPORG 1837 >>>>>>>>>>>>>>>>>>>>> 166 78331C00613900003115 1838 >EOR4NOTZERO I,X1 PTST SCR0 CUCKMT more left,get port st 167 F8531F1663597FFF3168 1839 > I,X1 LIT AND RAM SCR1 LAST #FFFF-LASTBIT LAST = 0,calculate... 1840 >>>>>>>>>>>>>>>>>>>>> 168 78530D9362D900003169 1841 I,X1 SCR1 ADD RAM SCR1 CORBC ...the real total... 169 F8530D9572D90000316A 1842 I,X1 SCR1 ADD RAM SCR1 BCNT 0 SKIP EOR4BCNOTZ ...BCNT,BCNT=0? 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 47 PPU5/REV 26 microcode File# 0 End-Of-Record processing 1844 SKIPORG 1845 >>>>>>>>>>>>>>>>>>>>> 16A F8131E85635800823197 1846 >EOR4BCNOTZ I,X1 LIT IOR RAM RAM PRTST EORINTR CUEXIT BCNT<>0,set interrupt 16B F8131F16735F8000316D 1847 > I,X1 LIT AND RAM LAST LASTBIT SKIP EOR4NOTLAST BCNT=0,is it last? 1848 >>>>>>>>>>>>>>>>>>>>> 1849 >>>>>>>>>>>>>>>>>>>>> 16C F8131E85635800B23194 1850 > I,X1 LIT IOR RAM RAM PRTST LASTBC CUCKEXT yes,say so&check for 16D 78131E92735F0000316F 1851 >EOR4NOTLAST I,X1 LIT IOR RAM BCOVERUN 0 SKIP EORNEXTBC not last, overrun? 1852 >>>>>>>>>>>>>>>>>>>>> 1853 1854 >>>>>>>>>>>>>>>>>>>>> 16E 78121E8563580050BEF0 1855 > I,X1 LIT IOR RAM RAM PRTST OVRRUN POP DIDNTPOP not ready, wait for it 16F 78131E85635800103170 1856 >EORNEXTBC I,X1 LIT IOR RAM RAM PRTST BCROLL no, signal BC rollover 1857 >>>>>>>>>>>>>>>>>>>>> 170 F8131C12637800003171 1858 I,X1 ZERO RAM BCOVERUN set overrun detector, 171 70331C1C635900003172 1859 I,X1 RAM SCR0 HADDR2 and move the rest of 172 68230C1762F800003173 1860 I,X1,P SCR0 RAM HADDR the parameters over 173 F0331C1D635900003174 1861 I,X1 RAM SCR0 LADDR2 174 68230C1862F800003175 1862 I,X1,P SCR0 RAM LADDR 175 F0331C19635900003176 1863 I,X1 RAM SCR0 SLOT2 176 68330C1462F800003177 1864 I,X1 SCR0 RAM SLOT 177 F0331C1B635900003178 1865 I,X1 RAM SCR0 LAST2 178 68330C1662F800003179 1866 I,X1 SCR0 RAM LAST 179 F0331C1A63590000317A 1867 I,X1 RAM SCR0 BCNT2 17A F8130D9562F8FFFC317B 1868 I,X1 SCR0 ADD LIT RAM BCNT -4 correct it for CORBC=8 1869 17B F8531F1663597FFF317C 1870 I,X1 LIT AND RAM SCR1 LAST #FFFF-LASTBIT calculate the... 17C 78530D9362D90000317D 1871 I,X1 SCR1 ADD RAM SCR1 CORBC ...real total... 17D 78530D9562D90000317E 1872 I,X1 SCR1 ADD RAM SCR1 BCNT ...byte count 1873 17E F8530E8072FF00033181 1874 I,X1 SCR1 IOR LIT 3 SKIP EORROLLGT3 BCNT >3? 1875 1876 SKIPORG 17F 4FF31C006379017F117F 1876$ WSTE0014 LIT SCR1F * * ****** wasted ****** 1877 >>>>>>>>>>>>>>>>>>>>> 180 D8311C00633F00003113 1878 > I CUNDONE BCNT <=3,finish proce 181 E8335C16237800031182 1879 >EORROLLGT3 STC,X1 LIT RAM,L LAST #0003 BCNT >3, LAST <- 3 1880 >>>>>>>>>>>>>>>>>>>>> 1881 182 B8538D1362D900001183 1882 X1,TWC,CST SCR1 SUB RAM SCR1 CORBC calculate new BCNT 183 78530D9562F8FFFD3113 1883 I,X1 SCR1 ADD LIT RAM BCNT -3 CUNDONE BCNT now correct,go f 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 48 PPU5/REV 26 microcode File# 0 End-Of-Record processing 184 F0331C176359018571C2 1885 CUNOTMT3 I,X1 RAM SCR0 HADDR *+1,PUSH WTFORBUS wait for BUS free 185 70211C18635100001186 1886 X1,P RAM SBLC LADDR 186 48700C0062EE00001187 1887 SCR1 SBHD 187 C8B00C0062EF00001188 1888 SCR2 SBLD 188 70311C14635500001189 1889 X1 RAM SBCB SLOT 189 78031D9863580001118A 1890 X1,P LIT ADD RAM RAM LADDR 1 make sure the address 1892 ***************************************************************************************************** 1893 * At this point, TEMP contains the number of bytes that must be * 1894 * subtracted from the bytecount to get the correct byte count. * 1895 ***************************************************************************************************** 1896 18A 70F35C2C63590000118B 1897 STC,X1 RAM SCR3 TEMP calculate the new... 18B B8D38C9662D80000118C 1898 X1,TWC,CST SCR3 RSUB RAM RAM LAST ...value of LAST 1899 18C F8D31F1663597FFF318D 1900 I,X1 LIT AND RAM SCR3 LAST #FFFF-LASTBIT calculate the... 18D F8D30D9362D90000318E 1901 I,X1 SCR3 ADD RAM SCR3 CORBC ...real new value of. 18E 78D30D9572D900003190 1902 I,X1 SCR3 ADD RAM SCR3 BCNT 0 SKIP CUBCNEQ BCNT, BCNT=0? 1903 1904 SKIPORG 18F 4FF31C006379018F118F 1904$ WSTE0015 LIT SCR1F * * ****** wasted ****** 1905 >>>>>>>>>>>>>>>>>>>>> 190 F8131E85635800823197 1906 >CUBCNEQ I,X1 LIT IOR RAM RAM PRTST EORINTR CUEXIT BCNT<>0,set interrupt 191 F8131F16735880003193 1907 > I,X1 LIT AND RAM RAM LAST LASTBIT SKIP CUBCNLAS BCNT=0, was LAST? 1908 >>>>>>>>>>>>>>>>>>>>> 1909 >>>>>>>>>>>>>>>>>>>>> 192 F8131E85635800B23197 1910 > I,X1 LIT IOR RAM RAM PRTST LASTBC CUEXIT yes, say so & exit 193 78131E85635800923197 1911 >CUBCNLAS I,X1 LIT IOR RAM RAM PRTST BCRATEOR CUEXIT no, set PPU interrupt 1912 >>>>>>>>>>>>>>>>>>>>> 194 F8331C00613900003195 1914 CUCKEXT I,X1 PTST SCR0 get the port status 195 D8130E8072FFFCFF3196 1915 I SCR0 IOR LIT PRTEMPTY SKIP CUEXTRA extra input? 1916 SKIPORG 1917 >>>>>>>>>>>>>>>>>>>>> 196 78131E85635840003197 1918 >CUEXTRA I,X1 LIT IOR RAM RAM PRTST EXTRA yes, say so 197 78131C12637800003198 1919 >CUEXIT I,X1 ZERO RAM BCOVERUN set overrun detector 1920 >>>>>>>>>>>>>>>>>>>>> 198 F8331C00613900003199 1922 I,X1 PTST SCR0 get port status 199 68311C0063760000119A 1923 X1 LIT DPDIR DIRINP reset data path, 19A 78311C0063230000119B 1924 X1 DPRST reset Data port 19B F8130F0072FF0400119D 1925 X1,T4 SCR0 AND LIT PRTPE SKIP EORNPE port parity error? 1926 SKIPORG 1927 >>>>>>>>>>>>>>>>>>>>> 19C 78131E8563582000319D 1928 > I,X1 LIT IOR RAM RAM PRTST DPPE yes, set error 19D 58301C00633F0000319E 1929 >EORNPE I,T3 1930 >>>>>>>>>>>>>>>>>>>>> 19E D8301C00633F0000319F 1931 I,T3 19F 68311C006363000111A0 1932 X1 LIT DPRST DPRST1IN (reset Data port agai 1A0 68301C006363000111A1 1933 X1,T3 LIT DPRST DPRST1IN (NEED CONSTANT FOR DP 1A1 78121F046358DFFFBEF0 1934 IP,X1 LIT AND RAM RAM FLAGS CM-REOR POP DIDNTPOP clear REOR & exit 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 49 PPU5/REV 26 microcode File# 0 End-Of-Record processing 1936 ***************************************************************************************************** 1937 * * 1938 * End-Of-Record processor IBF interrupt vector. * 1939 * * 1940 ***************************************************************************************************** 1941 VECTOR 1942 >>>>>>>>>>>>>>>>>>>>> F00 78131E85635801001F01 1943 >EORIBF X1 LIT IOR RAM RAM PRTST MPECODE BPE*, RTO* but Abnorm F01 78731C0065F9000011A3 1944 > X1 SBHC SCR1 EORIBF1 BPE*, RTO* and Normal F02 58331C00653901A25306 1945 > SBST SCR0 MEM4ERR,P BFGODIE BPE*, RTO* but Comman F03 58331C00653901A25306 1946 > SBST SCR0 MEM4ERR,P BFGODIE BPE*, RTO* but Illega F04 58331C00653901A25309 1947 > SBST SCR0 MEM4ERR,P CONGODIE BPE* but RTO! go F05 58331C00653901A25309 1948 > SBST SCR0 MEM4ERR,P CONGODIE BPE* but RTO! go F06 58331C00653901A25309 1949 > SBST SCR0 MEM4ERR,P CONGODIE BPE* but RTO! go F07 58331C00653901A25309 1950 > SBST SCR0 MEM4ERR,P CONGODIE BPE* but RTO! go F08 58331C00653901A25305 1951 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F09 58331C00653901A25305 1952 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F0A 58331C00653901A25305 1953 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F0B 58331C00653901A25305 1954 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F0C 58331C00653901A25305 1955 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F0D 58331C00653901A25305 1956 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F0E 58331C00653901A25305 1957 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go F0F 58331C00653901A25305 1958 > SBST SCR0 MEM4ERR,P PEGODIE BUS Parity Error, go 1959 >>>>>>>>>>>>>>>>>>>>> 1960 ENDVECTOR 1962 MEM4ERR HALT Bad Flags, Bus Parity Error, or RTO Set on End-Of-Record IBF Interrupt 1A2 4FF31C00637901A211A2 1962$ MEM4ERR LIT SCR1F * * Bad Flags, Bus Parity 1A3 D8B31C006679000011A4 1964 EORIBF1 SBLC SCR2 1A4 48331C08637A0F7011A5 1965 LIT IADR IBFIADR TWOWORDS restore IBFIADR 1A5 D8121C0063790000BEF0 1966 I ZERO SCR0 POP DIDNTPOP signal xfer done&exit 1967 TITLE.MAC CPU Interrupt processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 50 PPU5/REV 26 microcode File# 0 CPU Interrupt processor 1968 ***************************************************************************************************** 1969 * This routine is called from the IDLE loop and it tests * 1970 * for any of the reasons that PPUs interrupt. If any such * 1971 * condition exists, we generate the IPOLL response and set * 1972 * up the interrupt condition on the superbus. * 1973 ***************************************************************************************************** 1974 1975 STARTSKP 1A6 4FF31C00637901A611A6 1975$ WSTE0016 LIT SCR1F * * ****** wasted ****** 1A7 78131F05735F020031A8 1976 CKBCINT I,X1 LIT AND RAM PRTST BCINT SKIP NOTBCINT should BCROLL cause I 1977 >>>>>>>>>>>>>>>>>>>>> 1A8 78131F05735F100231AC 1978 >NOTBCINT I,X1 LIT AND RAM PRTST PPUINT SKIP NOTPPUIN no, check interrupts 1A9 78131F05735F001031AB 1979 > I,X1 LIT AND RAM PRTST BCROLL SKIP CKINT yes, rollover? 1980 >>>>>>>>>>>>>>>>>>>>> 1981 >>>>>>>>>>>>>>>>>>>>> 1AA 78131E856358000231AB 1982 > I,X1 LIT IOR RAM RAM PRTST PPUINTR yes, set int request 1AB 78131F05735F100231AC 1983 >CKINT I,X1 LIT AND RAM PRTST PPUINT SKIP NOTPPUIN PPU to interrupt? 1984 >>>>>>>>>>>>>>>>>>>>> 1985 >>>>>>>>>>>>>>>>>>>>> 1AC F8131F05735F080831AE 1986 >NOTPPUIN I,X1 LIT AND RAM PRTST CTLRINT SKIP NOTCTRIN no, controller? 1AD 79530F2C62F8000331B0 1987 > I,X1 SCR5 AND LIT RAM TEMP PRTNUMMASK SETINT yes, set INT (save po 1988 >>>>>>>>>>>>>>>>>>>>> 1989 >>>>>>>>>>>>>>>>>>>>> 1AE D8321C00633F0000BEF0 1990 >NOTCTRIN IP POP DIDNTPOP no, return 1AF 79530F2C62F8000331B0 1991 > I,X1 SCR5 AND LIT RAM TEMP PRTNUMMASK SETINT yes, set INT (save po 1992 >>>>>>>>>>>>>>>>>>>>> 1993 1B0 79D31EAC6359800031B1 1994 SETINT I,X1 LIT IOR RAM SCR7 TEMP #8000 construct the INT POL 1B1 C8321C0063660001BEF0 1995 IP LIT SBINT INT POP DIDNTPOP set INT bit 1996 TITLE.MAC CPU Request processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 51 PPU5/REV 26 microcode File# 0 CPU Request processor 1997 ***************************************************************************************************** 1998 * We come here if there is bus input ready to process. * 1999 * The idle loop code will have loaded SCRF (the counter for * 2000 * bus input store locations) into INDX1. * 2001 ***************************************************************************************************** 2002 2003 STARTSKP 1B2 4FF31C00637901B211B2 2003$ WSTE0017 LIT SCR1F * * ****** wasted ****** 1B3 F8131E9E735F7FFF31B4 2004 CKLEGAL I,X1 LIT IOR RAM BIHC #7FFF SKIP NOTLEGAL assigned command? 2005 >>>>>>>>>>>>>>>>>>>>> 1B4 CAF31C006379300011B7 2006 >NOTLEGAL LIT SCRB #3000 BADCOMM no, assert BE & die! 1B5 78D31E9EE359800031B6 2007 > I,X1 LIT IOR,X RAM SCR3 BIHC IRIOR*2^12 yes, go process 2008 >>>>>>>>>>>>>>>>>>>>> 1B6 C8F3040072FF00003E98 2009 I SCR3 DB4 BIRTAB 2010 1B7 CBF00C0062F301B85345 2011 BADCOMM SCRF INDX1 BADINP,P WTFORPON bad command or bad da 2012 2013 BADINP HALT Bad Command or Data Input 1B8 4FF31C00637901B811B8 2013$ BADINP LIT SCR1F * * Bad Command or Data I 2014 2015 BLOCK 8,IRIOR 2016 >>>>>>>>>>>>>>>>>>>>> E98 78131F1E63590FFF3225 2017 >BIRTAB I,X1 LIT AND RAM SCR0 BIHC #0FFF BIWRITE was WRITE- known port? E99 CAF31C006379300011B7 2018 > LIT SCRB #3000 BADCOMM Read-Modify-Write: er E9A F8131F22E359000F31EF 2019 > I,X1 LIT AND,X RAM SCR0 BIFT #000F BIREAD was READ - get FROM s E9B CAF31C006379300011B7 2020 > LIT SCRB #3000 BADCOMM Double-Word-Read: err E9C 78131E9F735F000F31D6 2021 > I,X1 LIT IOR RAM BILC #000F SKIP WRULEGAL was WRU - legal addr E9D D8311C00633F00001450 2022 > SELFTEST Self-Test E9E 4AF31C006379400011B7 2023 > LIT SCRB #4000 BADCOMM bad address on INT PO E9F CAF31C006379300011B7 2024 > LIT SCRB #3000 BADCOMM Double-Word-Write: er 2025 >>>>>>>>>>>>>>>>>>>>> 2026 ENDBLOCK 2027 2028 ***************************************************************************************************** 2029 * We come here with a response set up in SCR0 (high) * 2030 * and SCR1 (low) and the bus control bits in SCR2. * 2031 ***************************************************************************************************** 2032 1B9 D8301C00633F01BA71C2 2033 RESPEXIT I *+1,PUSH WTFORBUS wait for BUS to be fr 1BA C8700C0062F1000011BB 2034 SCR1 SBLC and do output 1BB 48B10C0062F5000011BC 2035 SCR2 SBCB set control bits 1BC D9130D8062F9000111BD 2036 SCR4 ADD LIT SCR4 TIMERSPX DECIBF bump timer, delay for 2037 2038 ***************************************************************************************************** 2039 * We come here when one of the words in the input * 2040 * buffer (the PPU can buffer up to four communications * 2041 * from CPUs) has been read. We advance the pointers and * 2042 * exit. * 2043 ***************************************************************************************************** 2044 1BD DBD30D8062F9000131BE 2045 DECIBF I SCRF ADD LIT SCRF 1 increment the IBF poi 1BE DB530D8062F9FFFF11BF 2046 SCRD ADD LIT SCRD -1 decrement the count, 1BF DA130F0062F9FFEF11C0 2047 SCR8 AND LIT SCR8 CM-CBNIM and turn on RFI 1C0 CA310C0062F7000011C1 2048 SCR8 IMR (i.e. allow CBN inter 1C1 49720C0062F30000BEF0 2049 IP SCR5 INDX1 POP DIDNTPOP restore index & conti 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 52 PPU5/REV 26 microcode File# 0 CPU Request processor 2051 ***************************************************************************************************** 2052 * This subroutine waits for the bus logic to become free * 2053 * (i.e. NOT rto AND NOT rfr AND NOT ibf). When the bus logic * 2054 * gets free, SCR0 is stored into SBHC, so the caller of this * 2055 * subroutine must put what he wants in SBHC into SCR0 before * 2056 * calling this subroutine. This subroutine also times the wait. * 2057 * This subroutine checks immediately to see if the bus is * 2058 * free for a minimum delay path through the code. If the bus * 2059 * is busy when first entered, a time out timer is set up and * 2060 * a loop waits for a short while (80 usec) to see if the bus * 2061 * will become available even with the data channel interrupts * 2062 * enabled. This is to protect any syncronous devices that * 2063 * are present by ensuring that no such device has a request * 2064 * outstanding. If the bus doesn't become free before the * 2065 * timeout, then we assume that the load is caused by asyncronous * 2066 * data channel devices that can swamp the PPU to memory channel. * 2067 * We disable data channel interrupts (but we must still allow * 2068 * IBF interrupts) and wait again for the bus to become free. * 2069 * This, if effect, forces the data channels to give up a * 2070 * transfer slot. It is possible for a syncronous device to * 2071 * be hurt badly if a lower priority asyncronous device steals * 2072 * any remaining cycles and forces the code here to steal one. * 2073 * If the bus doesn't become free before this time-out, then * 2074 * the PPU is in a confused state with respect to its bus logic. * 2075 ***************************************************************************************************** 2076 1C2 5AD30D8062F9000131C3 2077 WTFORBUS I SCRB ADD LIT SCRB 1 indicate 'New BUS Tra 1C3 58F31C006539000031C4 2078 I SBST SCR3 load current bus stat 1C4 58D30E8072FFF5BF11CB 2079 SCR3 IOR LIT BUSFREE SKIP WFBNAVAL skip if available imm 2080 2081 STARTSKP 1C5 D8D30E8072FFF5BF11C6 2082 WFBCKFRE SCR3 IOR LIT BUSFREE SKIP check bus available 2083 >>>>>>>>>>>>>>>>>>>>> 1C6 78131DAD7358FFFF31C8 2084 > I,X1 LIT ADD RAM RAM TEMP2 -1 SKIP WFBGSTAT bus busy, time-out? 1C7 48330C0062F000009EF0 2085 > SCR0 SBHC POP DIDNTPOP yes, start output and 2086 >>>>>>>>>>>>>>>>>>>>> 2087 >>>>>>>>>>>>>>>>>>>>> 1C8 D8F31C006539000031C5 2088 >WFBGSTAT I SBST SCR3 WFBCKFRE no, wait for bus 1C9 7A130EAD62F8001F31CC 2089 > I,X1 SCR8 IOR LIT RAM TEMP2 #001F WFBSTG2 copy int mask, no cha 2090 >>>>>>>>>>>>>>>>>>>>> 2091 >>>>>>>>>>>>>>>>>>>>> 1CA 48330C0062F000009EF0 2092 >WFBOUTS SCR0 SBHC POP DIDNTPOP yes, start output and 1CB E8331C2D6378006431C8 2093 >WFBNAVAL I,X1 LIT RAM TEMP2 WFBTO WFBGSTAT busy, set up a time-o 2094 >>>>>>>>>>>>>>>>>>>>> 2095 2096 * Bus logic has remained busy for at least 80 usec. Turn off data 2097 * channel interrupts to force us to get a bus transfer. 2098 1CC F0F31C2D6359000011CD 2099 WFBSTG2 X1 RAM SCR3 TEMP2 copy altered imr to r 1CD 48F10C0062F7000011CE 2100 SCR3 IMR dis-allow any channel 1CE E8331C2D637804E211D2 2101 X1 LIT RAM TEMP2 WFBTO2 WFBSTG2Y set up a time-out 2102 2103 STARTSKP 1CF 58D30E8072FFF5BF11D0 2104 WFBSTG2Q SCR3 IOR LIT BUSFREE SKIP check bus available 2105 >>>>>>>>>>>>>>>>>>>>> 1D0 F8131DAD7358FFFF31D2 2106 > I,X1 LIT ADD RAM RAM TEMP2 -1 SKIP WFBSTG2Y bus busy, time-out? 1D1 4A310C0062F7000011CA 2107 > SCR8 IMR WFBOUTS restore channel inter 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 53 PPU5/REV 26 microcode File# 0 CPU Request processor 2108 >>>>>>>>>>>>>>>>>>>>> 2109 >>>>>>>>>>>>>>>>>>>>> 1D2 D8F31C006539000031CF 2110 >WFBSTG2Y I SBST SCR3 WFBSTG2Q no, wait for bus 1D3 D8331C00653901D45309 2111 > SBST SCR0 WFBERR,P CONGODIE timeout, go DIE! 2112 >>>>>>>>>>>>>>>>>>>>> 2113 2114 WFBERR HALT Waiting for BUS time-out 1D4 4FF31C00637901D411D4 2114$ WFBERR LIT SCR1F * * Waiting for BUS time- 2115 TITLE.MAC CPU WRU processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 54 PPU5/REV 26 microcode File# 0 CPU WRU processor 2116 SKIPORG 1D5 4FF31C00637901D511D5 2116$ WSTE0018 LIT SCR1F * * ****** wasted ****** 2117 >>>>>>>>>>>>>>>>>>>>> 1D6 4AF31C006379400011B7 2118 >WRULEGAL LIT SCRB #4000 BADCOMM illegal address, asse 1D7 78131F22E359000F31D8 2119 > I,X1 LIT AND,X RAM SCR0 BIFT #000F get FROM slot # 2120 >>>>>>>>>>>>>>>>>>>>> 1D8 78130EAC62F8001131D9 2121 I,X1 SCR0 IOR LIT RAM TEMP RTODATA 1D9 70B31C2C6359000031DA 2122 I,X1 RAM SCR2 TEMP (save RESPTO data) 1DA 78131E9F7359000031DC 2123 I,X1 LIT IOR RAM SCR0 BILC 0 SKIP WRUNOT0 WRU #0? 2124 SKIPORG 1DB 4FF31C00637901DB11DB 2124$ WSTE0019 LIT SCR1F * * ****** wasted ****** 2125 >>>>>>>>>>>>>>>>>>>>> 1DC E8330C2C62F801E171EB 2126 >WRUNOT0 I,X1 SCR0 RAM TEMP DOWRU,P SHIFTL4 no, shift address lef 1DD D9D30E8072FF000031DF 2127 > I SCR7 IOR LIT 0 SKIP *+2 yes, are we interrupt 2128 >>>>>>>>>>>>>>>>>>>>> 2129 >>>>>>>>>>>>>>>>>>>>> 1DE E8330C2C62F801E171EB 2130 > I,X1 SCR0 RAM TEMP DOWRU,P SHIFTL4 no, shift address lef 1DF C8311C006373000031E0 2131 > I LIT INDX1 0 yes, say so. 2132 >>>>>>>>>>>>>>>>>>>>> 1E0 78131EA46359040031E7 2133 I,X1 LIT IOR RAM SCR0 WRURES1A #400 DOWRU1 set the interrupt bit 1E1 E8330C2C62F801E271ED 2135 DOWRU I,X1 SCR0 RAM TEMP *+1,PUSH SHIFTL2 1E2 F8D31F1F6359000331E3 2136 I,X1 LIT AND RAM SCR3 BILC #0003 use the 2 LSB's for b 1E3 D8130F00E2F9030031E4 2137 I SCR0 AND,X LIT SCR0 #0300 and the 2 MSB's for i 1E4 48310C0062F3000031E5 2138 I SCR0 INDX1 1E5 58D30E8062F9000831E6 2139 I SCR3 IOR LIT SCR3 WRUIOR 1E6 48F3080072FF00003EE8 2140 I SCR3 DB0 WRUTABLE 2142 BLOCK 4,WRUIOR 2143 >>>>>>>>>>>>>>>>>>>>> EE8 F0331C246359000031E7 2144 >WRUTABLE I,X1 RAM SCR0 WRURES1A DOWRU1 EE9 70331C266359000031E8 2145 > I,X1 RAM SCR0 WRURES2A DOWRU2 EEA 70331C286359000031E9 2146 > I,X1 RAM SCR0 WRURES3A DOWRU3 EEB F0331C2A6359000031EA 2147 > I,X1 RAM SCR0 WRURES4A DOWRU4 2148 >>>>>>>>>>>>>>>>>>>>> 2149 ENDBLOCK 2150 1E7 70731C256359000031B9 2151 DOWRU1 I,X1 RAM SCR1 WRURES1B RESPEXIT 1E8 F0731C276359000031B9 2152 DOWRU2 I,X1 RAM SCR1 WRURES2B RESPEXIT 1E9 70731C296359000031B9 2153 DOWRU3 I,X1 RAM SCR1 WRURES3B RESPEXIT 1EA F0731C2B6359000031B9 2154 DOWRU4 I,X1 RAM SCR1 WRURES4B RESPEXIT 1EB 781B0DAC62D9000011EC 2156 SHIFTL4 X1 SCR0 ADD RAM SCR0,R TEMP 1EC F81B0DAC62D9000011ED 2157 SHIFTL3 X1 SCR0 ADD RAM SCR0,R TEMP 1ED F81B0DAC62D9000011EE 2158 SHIFTL2 X1 SCR0 ADD RAM SCR0,R TEMP 1EE F8130DAC62D900009EF0 2159 X1 SCR0 ADD RAM SCR0 TEMP POP DIDNTPOP 2160 TITLE.MAC CPU Read processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 55 PPU5/REV 26 microcode File# 0 CPU Read processor 1EF F8130EAC62F8001131F0 2161 BIREAD I,X1 SCR0 IOR LIT RAM TEMP RTODATA 1F0 70B31C2C6359000031F1 2162 I,X1 RAM SCR2 TEMP (save RESPTO data) 1F1 F0F31C1F6359000031F2 2163 I,X1 RAM SCR3 BILC get the request for l 1F2 78531F1E6359000331F3 2164 I,X1 LIT AND RAM SCR1 BIHC PRTNUMMASK (save the port #) 1F3 78131F1E63590FFF31F4 2165 I,X1 LIT AND RAM SCR0 BIHC #0FFF put address in scratch 1F4 58130E8072FF000331F7 2166 I SCR0 IOR LIT PRTNUMMASK SKIP RPTNOTKN is it a good port ad 2167 SKIPORG 1F5 4FF31C00637901F511F5 2167$ WSTE0020 LIT SCR1F * * ****** wasted ****** 2168 >>>>>>>>>>>>>>>>>>>>> 1F6 C8310C0062F3000031F9 2169 > I SCR0 INDX1 RDCKWHO1 yes,set index,go proc 1F7 4AF31C006379400011B7 2170 >RPTNOTKN LIT SCRB #4000 BADCOMM no, assert BE & die! 2171 >>>>>>>>>>>>>>>>>>>>> 2173 STARTSKP 1F8 4FF31C00637901F811F8 2173$ WSTE0021 LIT SCR1F * * ****** wasted ****** 1F9 58D30F0072FF020031FA 2174 RDCKWHO1 I SCR3 AND LIT CBIT SKIP RDISUS to us or to controlle 2175 >>>>>>>>>>>>>>>>>>>>> 1FA 58D30E8072FF000F3208 2176 >RDISUS I SCR3 IOR LIT #000F SKIP RDNOTLEG to us. known address? 1FB F8131F04735F400031FD 2177 > I,X1 LIT AND RAM FLAGS PORTDEAD SKIP RNOTDEAD to controller. port D 2178 >>>>>>>>>>>>>>>>>>>>> 2179 >>>>>>>>>>>>>>>>>>>>> 1FC D8131C00637900003206 2180 > I ZERO SCR0 SENDLZ yes, respond with zero 1FD F8131E84735FF4FF31FE 2181 >RNOTDEAD I,X1 LIT IOR RAM FLAGS CSFREE SKIP RNOTFREE no, is the C/S port f 2182 >>>>>>>>>>>>>>>>>>>>> 2183 >>>>>>>>>>>>>>>>>>>>> 1FE 49720C0062F30000BEF0 2184 >RNOTFREE IP SCR5 INDX1 POP DIDNTPOP no, wait 'til complete 1FF E8311C00636200621200 2185 > X1 LIT CSOUT CTLRRD yes, start read 2186 >>>>>>>>>>>>>>>>>>>>> 200 68331C0463780E813201 2187 I,X1 LIT RAM FLAGS STARTRD set flag & retry count 201 E8331C086378809D3202 2188 I,X1 LIT RAM TYPECKSM CRDSTART set type, count & che 202 F9130D8962F8053C3203 2189 I,X1 SCR4 ADD LIT RAM CNTDOWN TIMECNST start timer 203 E8B30C0D62F800003204 2190 I,X1 SCR2 RAM RESPTO set where to respond 204 D9130D8062F900033205 2191 I SCR4 ADD LIT SCR4 TIMERW bump clock for overhe 205 68F30C0A62F8000031BD 2192 I,X1 SCR3 RAM ADDRESS DECIBF set address to send 206 D8531C00637900003207 2194 SENDLZ I ZERO SCR1 set lower half to zero 207 58930E0062F9001031B9 2195 I SCR2 XOR LIT SCR2 ADATAXOR RESPEXIT & send Abnormal Data 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 56 PPU5/REV 26 microcode File# 0 CPU Read processor 2197 SKIPORG 2198 >>>>>>>>>>>>>>>>>>>>> 208 4AF31C006379400011B7 2199 >RDNOTLEG LIT SCRB #4000 BADCOMM unknown add, assert B 209 C8F3080072FF00003E80 2200 > I SCR3 DB0 RDTAB yes, process request 2201 >>>>>>>>>>>>>>>>>>>>> 2202 2203 BLOCK 16 2204 >>>>>>>>>>>>>>>>>>>>> E80 58D31C006379000031FD 2205 >RDTAB I ZERO SCR3 RNOTDEAD device ID, give to co E81 D9D30E8072FF00001217 2206 > SCR7 IOR LIT 0 SKIP RDSTS internal status, INT E82 70331C0E63590000320A 2207 > I,X1 RAM SCR0 HSW1 RDSW1 controller status one E83 F0331C1063590000320B 2208 > I,X1 RAM SCR0 HSW2 RDSW2 controller status two E84 F0331C1463590000320C 2209 > I,X1 RAM SCR0 SLOT RDBCNT current byte count E85 F0331C1763590000320F 2210 > I,X1 RAM SCR0 HADDR RDMA1 current memory address E86 70331C19635900003211 2211 > I,X1 RAM SCR0 SLOT2 RDBCNT2 next byte count E87 F0331C1C635900003210 2212 > I,X1 RAM SCR0 HADDR2 RDMA2 next memory address E88 F9930F0072FF10003222 2213 > I,X1 SCR6 AND LIT SOPDDW SKIP RDMODENOTDW read mode register E89 4AF31C006379400011B7 2214 > LIT SCRB #4000 BADCOMM unknown address, asse E8A 4AF31C006379400011B7 2215 > LIT SCRB #4000 BADCOMM unknown address, asse E8B 4AF31C006379400011B7 2216 > LIT SCRB #4000 BADCOMM unknown address, asse E8C 4AF31C006379400011B7 2217 > LIT SCRB #4000 BADCOMM unknown address, asse E8D 4AF31C006379400011B7 2218 > LIT SCRB #4000 BADCOMM unknown address, asse E8E 4AF31C006379400011B7 2219 > LIT SCRB #4000 BADCOMM unknown address, asse E8F 4AF31C006379400011B7 2220 > LIT SCRB #4000 BADCOMM unknown address, asse 2221 >>>>>>>>>>>>>>>>>>>>> 2222 ENDBLOCK 20A F0731C0F6359000031B9 2224 RDSW1 I,X1 RAM SCR1 LSW1 RESPEXIT 2225 20B F0731C116359000031B9 2226 RDSW2 I,X1 RAM SCR1 LSW2 RESPEXIT 2227 20C F0731C1563590000120D 2228 RDBCNT X1 RAM SCR1 BCNT 20D 78530D9662D90000120E 2229 X1 SCR1 ADD RAM SCR1 LAST recombine BC with LAST 20E 78530D9362D9000011B9 2230 X1 SCR1 ADD RAM SCR1 CORBC RESPEXIT and the correction co 2231 20F 70731C186359000011B9 2232 RDMA1 X1 RAM SCR1 LADDR RESPEXIT 2233 210 F0731C1D6359000031B9 2234 RDMA2 I,X1 RAM SCR1 LADDR2 RESPEXIT 2235 211 70731C1A635900001212 2236 RDBCNT2 X1 RAM SCR1 BCNT2 212 F8530D9B62D900001213 2237 X1 SCR1 ADD RAM SCR1 LAST2 recombine BC with LAST 213 78131E93735F00001214 2238 X1 LIT IOR RAM CORBC 0 SKIP CORRBCNOT0 input or output (CO 2239 2240 SKIPORG 2241 >>>>>>>>>>>>>>>>>>>>> 214 58530D8062F9000411B9 2242 >CORRBCNOT0 SCR1 ADD LIT SCR1 4 RESPEXIT BC2 now in SCR1, resp 215 58311C00633F000011B9 2243 > RESPEXIT BC2 now in SCR1,respo 2244 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 57 PPU5/REV 26 microcode File# 0 CPU Read processor 2246 SKIPORG 2247 >>>>>>>>>>>>>>>>>>>>> 216 F0731C0563590000321F 2248 > I,X1 RAM SCR1 PRTST RDSTEXIT no, process read stat 217 79D34F2C62F800031218 2249 >RDSTS STC,X1 SCR7 AND LIT RAM TEMP PRTNUMMASK yes, get port # of INT 2250 >>>>>>>>>>>>>>>>>>>>> 218 38538D2C72DF0000121A 2251 TWC,CST,X1 SCR1 SUB RAM TEMP 0 SKIP INTNOTUS is it us? 2252 SKIPORG 219 4FF31C00637902191219 2252$ WSTE0022 LIT SCR1F * * ****** wasted ****** 2253 >>>>>>>>>>>>>>>>>>>>> 21A F0731C0563590000321F 2254 >INTNOTUS I,X1 RAM SCR1 PRTST RDSTEXIT 21B 70731C0563590000121C 2255 > X1 RAM SCR1 PRTST INTISUS 2256 >>>>>>>>>>>>>>>>>>>>> 2257 21C D8101C0063660000121D 2258 INTISUS ZERO SBINT yes, clear INT 21D D9D31C0063790000121E 2259 ZERO SCR7 & INT POLL response 21E 78131F056358E7FF121F 2260 X1 LIT AND RAM RAM PRTST INTCLR clear interrupt, 21F 70331C04635900001220 2261 RDSTEXIT X1 RAM SCR0 FLAGS setup for output 220 F8131F056358FFE511B9 2262 X1 LIT AND RAM RAM PRTST STSCLBTS RESPEXIT clear status & exit 2263 2264 SKIPORG 221 4FF31C00637902211221 2264$ WSTE0023 LIT SCR1F * * ****** wasted ****** 2265 >>>>>>>>>>>>>>>>>>>>> 222 48731C00637900003224 2266 >RDMODENOTDW I LIT SCR1 0000 RDMODEND no,indicate it is cle 223 C8731C00637900013224 2267 > I LIT SCR1 DOUBWRTBIT RDMODEND yes,indicate it is set 2268 >>>>>>>>>>>>>>>>>>>>> 224 58131C006379000031B9 2269 RDMODEND I ZERO SCR0 RESPEXIT clear hi half,go resp 2270 TITLE.MAC CPU Write processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 58 PPU5/REV 26 microcode File# 0 CPU Write processor 2271 STARTSKP 225 58130E8072FF00033226 2272 BIWRITE I SCR0 IOR LIT PRTNUMMASK SKIP WPTNOTKN is legal port #? 2273 >>>>>>>>>>>>>>>>>>>>> 226 4AF31C006379400011B7 2274 >WPTNOTKN LIT SCRB #4000 BADCOMM bad address, assert B 227 70F31C1F635900003228 2275 > I,X1 RAM SCR3 BILC known port, save comm 2276 >>>>>>>>>>>>>>>>>>>>> 228 70731C20635900003229 2277 I,X1 RAM SCR1 BIHD 229 F0B31C2163590000322A 2278 I,X1 RAM SCR2 BILD 22A F8131F1E63590003322B 2279 I,X1 LIT AND RAM SCR0 BIHC PRTNUMMASK set index 22B 48310C0062F30000322C 2280 I SCR0 INDX1 22C 58D30F0072FF0200322E 2281 I SCR3 AND LIT CBIT SKIP WRISUS to us or controller? 2282 SKIPORG 22D 4FF31C006379022D122D 2282$ WSTE0024 LIT SCR1F * * ****** wasted ****** 2283 >>>>>>>>>>>>>>>>>>>>> 22E D8D30E8072FF000F323C 2284 >WRISUS I SCR3 IOR LIT #000F SKIP WRNOTLEG to us. known address? 22F F8131F04735F40003231 2285 > I,X1 LIT AND RAM FLAGS PORTDEAD SKIP WNOTDEAD to controller. port D 2286 >>>>>>>>>>>>>>>>>>>>> 2287 >>>>>>>>>>>>>>>>>>>>> 230 58311C00633F000031BD 2288 > I DECIBF yes, just ignore it 231 F8131E84735FF4FF3232 2289 >WNOTDEAD I,X1 LIT IOR RAM FLAGS CSFREE SKIP WNOTFREE no, is the C/S port f 2290 >>>>>>>>>>>>>>>>>>>>> 2291 >>>>>>>>>>>>>>>>>>>>> 232 49720C0062F30000BEF0 2292 >WNOTFREE IP SCR5 INDX1 POP DIDNTPOP no, wait 'til complete 233 E8311C00636200961234 2293 > X1 LIT CSOUT CTLRWR yes, start write 2294 >>>>>>>>>>>>>>>>>>>>> 234 68331C04637806813235 2295 I,X1 LIT RAM FLAGS STARTWR set flag & retry count 235 68331C08637800693236 2296 I,X1 LIT RAM TYPECKSM CWRSTART set type, count & che 236 79130D8962F8053C3237 2297 I,X1 SCR4 ADD LIT RAM CNTDOWN TIMECNST start timer 237 E8F30C0A62F800003238 2298 I,X1 SCR3 RAM ADDRESS setup bytes for output 238 68730C0B62F800003239 2299 I,X1 SCR1 RAM HWORD 239 D9130D8062F90006323A 2300 I SCR4 ADD LIT SCR4 TIMEWW bump clock for overhe 23A E8B30C0C62F8000031BD 2301 I,X1 SCR2 RAM LWORD DECIBF exit 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 59 PPU5/REV 26 microcode File# 0 CPU Write processor 2303 SKIPORG 23B 4FF31C006379023B123B 2303$ WSTE0025 LIT SCR1F * * ****** wasted ****** 2304 >>>>>>>>>>>>>>>>>>>>> 23C 4AF31C006379400011B7 2305 >WRNOTLEG LIT SCRB #4000 BADCOMM unknown address, asse 23D C8F3080072FF00003E70 2306 > I SCR3 DB0 WRTAB process request 2307 >>>>>>>>>>>>>>>>>>>>> 2308 2309 BLOCK 16 2310 >>>>>>>>>>>>>>>>>>>>> E70 FA530E8262D90000123E 2311 >WRTAB X1 SCR9 IOR RAM SCR9 PBITHIGH RESCONT reset a controller E71 F8131F0563589A891245 2312 >WRTABABT X1 LIT AND RAM RAM PRTST ABTCLR ABORT abort FIFO operation E72 58930F0062F91A013252 2313 > I SCR2 AND LIT SCR2 GOODBITS SSSTS selective set status E73 D8930F0062F91A013253 2314 > I SCR2 AND LIT SCR2 GOODBITS SCSTS selective clear status E74 78131F05735F80003258 2315 > I,X1 LIT AND RAM PRTST BTWREC SKIP LDBC1 set 1st byte count E75 E8730C2C62F802FC72F7 2316 > I,X1 SCR1 RAM TEMP LDMA1,PUSH ADDIR set 1st memory address E76 D8930E8072FF800032A9 2317 > I SCR2 IOR LIT LASTBIT SKIP LDBC2 set next byte count E77 68730C2C62F8030072F7 2318 > I,X1 SCR1 RAM TEMP LDMA2,PUSH ADDIR set next memory addre E78 D8930F0072FF00013256 2319 > I SCR2 AND LIT DOUBWRTBIT SKIP WRMODENOTTW set or unset trip E79 4AF31C006379400011B7 2320 > LIT SCRB #4000 BADCOMM bad address,assert BE E7A 4AF31C006379400011B7 2321 > LIT SCRB #4000 BADCOMM bad address,assert BE E7B 4AF31C006379400011B7 2322 > LIT SCRB #4000 BADCOMM bad address,assert BE E7C 4AF31C006379400011B7 2323 > LIT SCRB #4000 BADCOMM bad address,assert BE E7D 4AF31C006379400011B7 2324 > LIT SCRB #4000 BADCOMM bad address,assert BE E7E 4AF31C006379400011B7 2325 > LIT SCRB #4000 BADCOMM bad address,assert BE E7F 4AF31C006379400011B7 2326 > LIT SCRB #4000 BADCOMM bad address,assert BE 2327 >>>>>>>>>>>>>>>>>>>>> 2328 ENDBLOCK 23E FA530E0262D90000123F 2330 RESCONT X1 SCR9 XOR RAM SCR9 PBITHIGH 23F 4A710C0062F200001240 2331 SCR9 DPOE assert MCLR (master c 240 48331C00637900C83242 2332 I LIT SCR0 200 RESCONT2 set a timer 2333 SKIPORG 241 4FF31C00637902411241 2333$ WSTE0026 LIT SCR1F * * ****** wasted ****** 2334 >>>>>>>>>>>>>>>>>>>>> 242 D8130D8072F9FFFF3242 2335 >RESCONT2 I SCR0 ADD LIT SCR0 -1 SKIP RESCONT2 wait 50 u-seconds 243 D8301C00633F02447247 2336 > I *+1,PUSH ABORTPRT then do an abort 2337 >>>>>>>>>>>>>>>>>>>>> 244 7A530E0262D900003E71 2338 I,X1 SCR9 XOR RAM SCR9 PBITHIGH WRTABABT release MCLR and clea 245 78131E85635880801246 2340 ABORT X1 LIT IOR RAM RAM PRTST ABTSET clear & set selected 246 F8131C04637801BD5247 2341 X1 ZERO RAM FLAGS DECIBF,P ABORTPRT clear I/O & cleanup t 2342 247 7A530E8162D900001248 2343 ABORTPRT X1 SCR9 IOR RAM SCR9 PBITLOW clear output enable 248 7A530E0162D900001249 2344 X1 SCR9 XOR RAM SCR9 PBITLOW 249 4A710C0062F20000124A 2345 SCR9 DPOE 24A 68311C0063760000124B 2346 X1 LIT DPDIR DIRINP set direction to read 24B 78311C0063230000124C 2347 X1 DPRST reset Data port 24C 7A130E8362D90000124D 2348 X1,T4 SCR8 IOR RAM SCR8 PBITIM disallow interrupts t 24D 4A310C0062F70000124E 2349 SCR8 IMR 24E D8301C00633F0000124F 2350 T3 24F 68311C00636300011250 2351 X1 LIT DPRST DPRST1IN (reset the Data port 250 E8301C00637F00011251 2352 X1,T3 LIT DPRST1IN (NEED CONSTANT FOR DP 251 F8121C1263780000BEF0 2353 IP,X1 ZERO RAM BCOVERUN POP DIDNTPOP set overrun detector 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 60 PPU5/REV 26 microcode File# 0 CPU Write processor 252 78930E8562D8000031BD 2356 SSSTS I,X1 SCR2 IOR RAM RAM PRTST DECIBF set selected bits & e 253 78930E8562D800001254 2358 SCSTS X1 SCR2 IOR RAM RAM PRTST set the selected bits 254 F8930E0562D8000031BD 2359 I,X1 SCR2 XOR RAM RAM PRTST DECIBF then clear them & exit 2361 SKIPORG 255 4FF31C00637902551255 2361$ WSTE0027 LIT SCR1F * * ****** wasted ****** 2362 >>>>>>>>>>>>>>>>>>>>> 256 D9930F0062F9EFFF31BD 2363 >WRMODENOTTW I SCR6 AND LIT SCR6 #FFFF-SOPDDW DECIBF clear it and exit 257 D9930E8062F9100031BD 2364 > I SCR6 IOR LIT SCR6 SOPDDW DECIBF set it and exit 2365 >>>>>>>>>>>>>>>>>>>>> 2366 TITLE.MAC First byte count loader 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 61 PPU5/REV 26 microcode File# 0 First byte count loader 2367 ***************************************************************************************************** 2368 * The first part of this routine -- down to TESTDIR -- * 2369 * checks to ensure that we have valid data. This includes: * 2370 * -we must be between records or the port gets confused. * 2371 * -if not last BC, BC must be a multiple of 4 and not zero else BUS ERROR * 2372 * This part also handles the special case of BC=0 so the * 2373 * following routines know that the byte count will always be * 2374 * greater than zero. * 2375 ***************************************************************************************************** 2376 2377 SKIPORG 2378 >>>>>>>>>>>>>>>>>>>>> 258 78131E856358040231BD 2379 >LDBC1 I,X1 LIT IOR RAM RAM PRTST CONFUSED DECIBF no, confusing. 259 58930E8072FF8000325B 2380 > I SCR2 IOR LIT LASTBIT SKIP *+2 yes, byte count =0? 2381 >>>>>>>>>>>>>>>>>>>>> 2382 >>>>>>>>>>>>>>>>>>>>> 25A 78930F0072FF80003260 2383 > I,X1 SCR2 AND LIT LASTBIT SKIP BCNLAST yes, last BC? 25B 58930F0072FF8000325D 2384 > I SCR2 AND LIT LASTBIT SKIP *+2 not zero, last BC? 2385 >>>>>>>>>>>>>>>>>>>>> 2386 >>>>>>>>>>>>>>>>>>>>> 25C 68B30C1662F800003263 2387 > I,X1 SCR2 RAM LAST TESTDIR yes, anything else is 25D D8930E8072FFFFFC325E 2388 > I SCR2 IOR LIT #FFFC SKIP no, a multiple of 4? 2389 >>>>>>>>>>>>>>>>>>>>> 2390 >>>>>>>>>>>>>>>>>>>>> 25E 78131E85635804023304 2391 > I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA no, unacceptable data 25F 68B30C1662F800003263 2392 > I,X1 SCR2 RAM LAST TESTDIR yes, OK 2393 >>>>>>>>>>>>>>>>>>>>> 2395 SKIPORG 2396 >>>>>>>>>>>>>>>>>>>>> 260 78131E85635804023304 2397 >BCNLAST I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA no, cockpit error 261 F8131F0563587FFF31BD 2398 > I,X1 LIT AND RAM RAM PRTST #FFFF BAND (CM-BTWREC) DECIBF yes, just wait 2399 >>>>>>>>>>>>>>>>>>>>> 2401 ***************************************************************************************************** 2402 * * 2403 * The next few lines determine what the direction is and whether * 2404 * we are in double or single data word store mode. They jump to the * 2405 * appropriate initialization routine to initialize the BCNT, LAST, and * 2406 * CORBC variables. These few lines also do the first part of the data * 2407 * port reset (I.E. they set the direction and do the first DPRST). * 2408 * * 2409 ***************************************************************************************************** 2410 2411 STARTSKP 262 4FF31C00637902621262 2411$ WSTE0028 LIT SCR1F * * ****** wasted ****** 263 F8131F05735600011264 2412 TESTDIR X1 LIT AND RAM DPDIR PRTST DMADIR SKIP DIRISIN test/set DMA direction 2413 >>>>>>>>>>>>>>>>>>>>> 264 F9930F0072E310001266 2414 >DIRISIN X1 SCR6 AND LIT DPRST SOPDDW SKIP MODEIS1W input,single or doubl 265 78131F18734300011268 2415 > X1 LIT AND RAM DPRST LADDR 1 SKIP OUTEVENSTART output,is start a 2416 >>>>>>>>>>>>>>>>>>>>> 2417 >>>>>>>>>>>>>>>>>>>>> 266 E8331013737800041E6C 2418 >MODEIS1W X1 LIT RAM CORBC 4 INDX FISETINT1W single mode,set BC 267 F8131F18735F00011279 2419 > X1 LIT AND RAM LADDR 1 SKIP LDBC1INEVEN double mode,is sta 2420 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 62 PPU5/REV 26 microcode File# 0 First byte count loader 2422 ***************************************************************************************************** 2423 * DIRECTION IS OUTPUT * 2424 ***************************************************************************************************** 2425 2426 >>>>>>>>>>>>>>>>>>>>> 268 F81311967359FFFF1EEC 2427 >OUTEVENSTART X1,T4 LIT ADD RAM SCR0 LAST -1 INDX FOSETI2W even addr,set for dou 269 781311967359FFFF1E60 2428 > X1,T4 LIT ADD RAM SCR0 LAST -1 INDX FOSETI1W odd addr,set for sing 2429 >>>>>>>>>>>>>>>>>>>>> 2430 2431 2432 BLOCK 4,OUTIOR1 2433 >>>>>>>>>>>>>>>>>>>>> 2434 >* table to set interrupt address for output double word EEC 48331C1C637A0F601270 2435 >FOSETI2W LIT IADR PRT0IADR FOUTINT WRITEBC set output- port 0 EED C8331C18637A0F601270 2436 > LIT IADR PRT1IADR FOUTINT WRITEBC EEE C8331C14637A0F601270 2437 > LIT IADR PRT2IADR FOUTINT WRITEBC EEF 48331C10637A0F601270 2438 > LIT IADR PRT3IADR FOUTINT WRITEBC set output- port 3 2439 >>>>>>>>>>>>>>>>>>>>> 2440 ENDBLOCK 2442 BLOCK 4,IORFOSETI1W 2443 >>>>>>>>>>>>>>>>>>>>> 2444 >* table to set interrupt address for output single word E60 48331C1C637A0F50126B 2445 >FOSETI1W LIT IADR PRT0IADR FOUTI1W OUTODDADDR set output- port 0 E61 C8331C18637A0F50126B 2446 > LIT IADR PRT1IADR FOUTI1W OUTODDADDR E62 C8331C14637A0F50126B 2447 > LIT IADR PRT2IADR FOUTI1W OUTODDADDR E63 48331C10637A0F50126B 2448 > LIT IADR PRT3IADR FOUTI1W OUTODDADDR set output- port 3 2449 >>>>>>>>>>>>>>>>>>>>> 2450 ENDBLOCK 2451 2452 STARTSKP 26A 4FF31C006379026A126A 2452$ WSTE0029 LIT SCR1F * * ****** wasted ****** 26B D8130E8072FF8003326D 2453 OUTODDADDR I SCR0 IOR LIT #8003 SKIP *+2 BC>4? 2454 >>>>>>>>>>>>>>>>>>>>> 26C D8131C00637900003271 2455 > I ZERO SCR0 WRITEBC1 no, setup for one wor 26D 78131D966359FFFB326E 2456 > I,X1 LIT ADD RAM SCR0 LAST -5 yes, process 2457 >>>>>>>>>>>>>>>>>>>>> 2458 26E 58130F0062F97FF8326F 2459 I SCR0 AND LIT SCR0 #7FF8 26F D8130D8062F900043271 2460 I SCR0 ADD LIT SCR0 4 WRITEBC1 2461 270 58130F0062F97FF83271 2462 WRITEBC I SCR0 AND LIT SCR0 #7FF8 271 78135C13637800001272 2463 WRITEBC1 STC,X1 ZERO RAM CORBC set the BC correction 272 B8138C9662D800001273 2464 TWC,CST,X1 SCR0 RSUB RAM RAM LAST 273 E8330C1562F800003274 2465 I,X1 SCR0 RAM BCNT 274 68330C0762F800003275 2466 I,X1 SCR0 RAM CLKFIX save for clock correc 275 78131F0563581E0B3276 2467 I,X1 LIT AND RAM RAM PRTST BC1CLR BAND #FFFF 276 68311C00636300011277 2468 X1 LIT DPRST DPRSTOUT (reset the Data port 277 68301C00637F00011295 2469 X1,T3 LIT DPRSTOUT ALLOWINT (CONSTANT FOR DPRST) 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 63 PPU5/REV 26 microcode File# 0 First byte count loader 2471 ***************************************************************************************************** 2472 * * 2473 * DIRECTION IS INPUT -- DOUBLE DATA WORD STORE MODE * 2474 * CORBC IS SET TO 8. * 2475 * * 2476 * If the start address is even and BCNT >=8, BCNT will be the greatest * 2477 * integer multiple of eight that is less than or equat to the input number * 2478 * minus 8. If the start address is ODD or BCNT < 8, BCNT will be the * 2479 * greatest number of the form 4+8K (K is an integer) that is less than or * 2480 * equal to the input number minus 8. This means that BCNT should come out * 2481 * to be 8 less than the remaining whole word part of the input byte count * 2482 * that is to be handled by the interrupt handlers. I.E. If there is no * 2483 * whole word part of the byte count remaining, BCNT=-8(#FFF8), and if * 2484 * there is one double word transfer left, BCNT=0000, and if there is one * 2485 * single word transfer left, BCNT=-4(#FFFC). * 2486 * * 2487 * LAST will contain the LAST BIT (if it is set) and be the input * 2488 * number minus (BCNT+8). This should come out to be one of the following * 2489 * numbers: 0,1,2,3,4,5,6,OR 7. If the start address is odd, we will start * 2490 * out with a single data word store, otherwise, we will start out with * 2491 * double data word stores. * 2492 * * 2493 ***************************************************************************************************** 2495 SKIPORG 2496 >>>>>>>>>>>>>>>>>>>>> 278 68331013737800081E68 2497 > X1 LIT RAM CORBC 8 INDX INSETINT2WODD odd,first store 279 F8131E96735F8007127A 2498 >LDBC1INEVEN X1 LIT IOR RAM LAST (LASTBIT+0007) SKIP LDBC1GE8 even,BC>=8? 2499 >>>>>>>>>>>>>>>>>>>>> 2500 >>>>>>>>>>>>>>>>>>>>> 27A 68331013737800081E64 2501 >LDBC1GE8 X1 LIT RAM CORBC 8 INDX INSETINT2WEVEN BC>=8,first sto 27B 68331013737800081E68 2502 > X1 LIT RAM CORBC 8 INDX INSETINT2WODD BC<8,first store 2503 >>>>>>>>>>>>>>>>>>>>> 2505 BLOCK 4,ISI2WEIOR 2506 >>>>>>>>>>>>>>>>>>>>> E64 68331C1C637A0F301282 2507 >INSETINT2WEVEN X1 LIT IADR PRT0IADR FINPINT2W INEVEN2W set input- port 0 E65 E8331C18637A0F301282 2508 > X1 LIT IADR PRT1IADR FINPINT2W INEVEN2W E66 E8331C14637A0F301282 2509 > X1 LIT IADR PRT2IADR FINPINT2W INEVEN2W E67 68331C10637A0F301282 2510 > X1 LIT IADR PRT3IADR FINPINT2W INEVEN2W set input- port 3 2511 >>>>>>>>>>>>>>>>>>>>> 2512 ENDBLOCK 2514 BLOCK 4,ISI2WOIOR 2515 >>>>>>>>>>>>>>>>>>>>> E68 68331C1C637A0F40127C 2516 >INSETINT2WODD X1 LIT IADR PRT0IADR FINPINT2WODD INODD2W set input- port 0 E69 E8331C18637A0F40127C 2517 > X1 LIT IADR PRT1IADR FINPINT2WODD INODD2W E6A E8331C14637A0F40127C 2518 > X1 LIT IADR PRT2IADR FINPINT2WODD INODD2W E6B 68331C10637A0F40127C 2519 > X1 LIT IADR PRT3IADR FINPINT2WODD INODD2W set input- port 3 2520 >>>>>>>>>>>>>>>>>>>>> 2521 ENDBLOCK 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 64 PPU5/REV 26 microcode File# 0 First byte count loader 2523 EVEN 27C F8131F1663597FFC327D 2524 INODD2W I,X1 LIT AND RAM SCR0 LAST #7FFC 27D 78130E8072FF0000327E 2525 I,X1 SCR0 IOR LIT 0 SKIP BC >= 4? 2526 >>>>>>>>>>>>>>>>>>>>> 27E F8131D966359FFFC3280 2527 > I,X1 LIT ADD RAM SCR0 LAST -4 *+2 yes,process 27F 78315C00633F00001283 2528 > X1,STC CALCLAST no,set for 1 xfer of 2529 >>>>>>>>>>>>>>>>>>>>> 280 58130F0062F97FF83281 2530 I SCR0 AND LIT SCR0 #7FF8 calculate BC 281 58134D8062F900041283 2531 STC SCR0 ADD LIT SCR0 4 CALCLAST SCR0 now contains BCNT 282 F8135F1663597FF81283 2533 INEVEN2W X1,STC LIT AND RAM SCR0 LAST #7FF8 calculate mult of 8 p 283 38138C9662D800001284 2534 CALCLAST TWC,CST,X1 SCR0 RSUB RAM RAM LAST calculate LAST 284 F8130D9562F8FFF83285 2535 I,X1 SCR0 ADD LIT RAM BCNT -8 store byte count 285 78131F0563581E0B3286 2536 I,X1 LIT AND RAM RAM PRTST BC1CLR BAND #FFFF 286 E8311C00636300001287 2537 X1 LIT DPRST DPRST2IN finish data port reset 287 E8301C00637F00001288 2538 X1,T3 LIT DPRST2IN (constant for DPRST) 288 78131F16735F8000128A 2540 X1 LIT AND RAM LAST LASTBIT SKIP LDBC1INOTLAST is this last BC? 2541 SKIPORG 289 4FF31C00637902891289 2541$ WSTE0030 LIT SCR1F * * ****** wasted ****** 2542 >>>>>>>>>>>>>>>>>>>>> 28A F8311C00633F00003295 2543 >LDBC1INOTLAST I,X1 ALLOWINT not last,allow interr 28B 68331C006379FFF8328C 2544 > I,X1 LIT SCR0 -8 is last,get const in 2545 >>>>>>>>>>>>>>>>>>>>> 28C F8130E1572DF00003295 2546 I,X1 SCR0 XOR RAM BCNT 0 SKIP ALLOWINT if whole word part of 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 65 PPU5/REV 26 microcode File# 0 First byte count loader 2548 ***************************************************************************************************** 2549 * DIRECTION IS INPUT -- SINGLE DATA WORD STORE MODE * 2550 *CORBC IS SET TO 4 * 2551 * BCNT is the greatest integer multiple of 4 that is less than or * 2552 * equal to the input byte count. * 2553 * LAST contains the LAST bit and the input byte count modulo 4 which * 2554 * should be 0, 1, 2, OR 3. * 2555 ***************************************************************************************************** 2557 BLOCK 4,INPIOR 2558 >>>>>>>>>>>>>>>>>>>>> E6C E8331C1C637A0F20128D 2559 >FISETINT1W X1 LIT IADR PRT0IADR FINPINT1W READBC set input- port 0 E6D 68331C18637A0F20128D 2560 > X1 LIT IADR PRT1IADR FINPINT1W READBC E6E 68331C14637A0F20128D 2561 > X1 LIT IADR PRT2IADR FINPINT1W READBC E6F E8331C10637A0F20128D 2562 > X1 LIT IADR PRT3IADR FINPINT1W READBC set input- port 3 2563 >>>>>>>>>>>>>>>>>>>>> 2564 ENDBLOCK 28D F8135F1663597FFC128E 2566 READBC STC,X1 LIT AND RAM SCR0 LAST #7FFC 28E B8138C9662D80000128F 2567 TWC,CST,X1 SCR0 RSUB RAM RAM LAST 28F F8130D9562F8FFFC3290 2568 I,X1 SCR0 ADD LIT RAM BCNT -4 290 78131F0563581E0B3291 2569 I,X1 LIT AND RAM RAM PRTST BC1CLR BAND #FFFF 291 E8311C00636300011292 2570 X1 LIT DPRST DPRST1IN (reset the Data port 292 68301C00637F00011293 2571 X1,T3 LIT DPRST1IN (CONSTANT FOR DPRST) 293 F8131F15735F80001295 2572 X1,T4 LIT AND RAM BCNT #8000 SKIP ALLOWINT no int's BC<4 & input 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 66 PPU5/REV 26 microcode File# 0 First byte count loader 2574 ***************************************************************************************************** 2575 * This part enables interrupts if they should be enabled and pre-fills * 2576 * the FIFO if the direction is output. * 2577 * The FIFO pre-fill is accomplished by alternately allowing interrupts * 2578 * on this port and dis-allowing interrupts on this port. This prevents this * 2579 * port from starving other ports during the initial loading of the FIFO. * 2580 * We use a PUSH and the interruptable POP in turn because this allows * 2581 * this loop the ensure progress even with interrupts happening. * 2582 ***************************************************************************************************** 2584 SKIPORG 2585 >>>>>>>>>>>>>>>>>>>>> 294 F8131E856358008031BD 2586 > I,X1 LIT IOR RAM RAM PRTST DMANBZ DECIBF signal FIFO not runni 295 7A130E8362D901BD5296 2587 >ALLOWINT X1,T4 SCR8 IOR RAM SCR8 PBITIM DECIBF,P DO1FETCH allow at least 1 inte 2588 >>>>>>>>>>>>>>>>>>>>> 296 7A130E0362D900001297 2590 DO1FETCH X1 SCR8 XOR RAM SCR8 PBITIM allow interrupts this 297 CA310C0062F700001298 2591 SCR8 IMR 298 78131F05735F0001129A 2592 X1 LIT AND RAM PRTST DMADIR SKIP DO1FEXIT write? 2593 SKIPORG 299 4FF31C00637902991299 2593$ WSTE0031 LIT SCR1F * * ****** wasted ****** 2594 >>>>>>>>>>>>>>>>>>>>> 29A D8321C00633F0000BEF0 2595 >DO1FEXIT IP POP DIDNTPOP no, just exit 29B C8331C006379000A12A7 2596 > LIT SCR0 10 DO1FLOOP yes, do pre-fill of F 2597 >>>>>>>>>>>>>>>>>>>>> 2598 SKIPORG 2599 >>>>>>>>>>>>>>>>>>>>> 29C D8321C00633F0000BEF0 2600 > IP POP DIDNTPOP yes, that's it 29D 58130D8072F9FFFF129F 2601 >DO1FNEND SCR0 ADD LIT SCR0 -1 SKIP *+2 no, done enough? 2602 >>>>>>>>>>>>>>>>>>>>> 2603 >>>>>>>>>>>>>>>>>>>>> 29E D8321C00633F0000BEF0 2604 > IP POP DIDNTPOP yes, exit 29F 7A130E0362D902A152A0 2605 > X1 SCR8 XOR RAM SCR8 PBITIM *+2,PUSH *+1 no, allow only 1 inte 2606 >>>>>>>>>>>>>>>>>>>>> 2A0 4A320C0062F70000BEF0 2607 IP SCR8 IMR POP DIDNTPOP 2A1 D8301C00633F02A352A2 2608 *+2,PUSH *+1 wait for it and 2A2 D8321C00633F0000BEF0 2609 IP POP DIDNTPOP 2A3 D8301C00633F02A552A4 2610 *+2,PUSH *+1 2A4 D8321C00633F0000BEF0 2611 IP POP DIDNTPOP 2A5 D8301C00633F02A752A6 2612 DO1FLOOP,P *+1 then allow the IBF in 2A6 D8321C00633F0000BEF0 2613 IP POP DIDNTPOP 2A7 F8131F05735F0020129D 2614 DO1FLOOP X1 LIT AND RAM PRTST BCLAST SKIP DO1FNEND BC exhausted? 2615 TITLE.MAC second byte count loader 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 67 PPU5/REV 26 microcode File# 0 second byte count loader 2616 ***************************************************************************************************** 2617 * The first part of this routine (down to TESTDIR2) ensures that the * 2618 * input data is okay. The byte count that was written must not be zero, * 2619 * and if the LAST bit is not set, it must be a multiple of 4. If these * 2620 * conditions are not met, we will do a bad data to a pseudo address bus * 2621 * error. * 2622 ***************************************************************************************************** 2623 2624 SKIPORG 2625 >>>>>>>>>>>>>>>>>>>>> 2A8 78131E85635804023304 2626 > I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA BC zero, cockpit error 2A9 58930F0072FF800032AB 2627 >LDBC2 I SCR2 AND LIT LASTBIT SKIP *+2 not zero, last BC? 2628 >>>>>>>>>>>>>>>>>>>>> 2629 >>>>>>>>>>>>>>>>>>>>> 2AA E8B30C1B62F8000032AF 2630 > I,X1 SCR2 RAM LAST2 TESTDIR2 yes, anything else is 2AB 58930E8072FFFFFC32AC 2631 > I SCR2 IOR LIT #FFFC SKIP no, a multiple of 4? 2632 >>>>>>>>>>>>>>>>>>>>> 2633 >>>>>>>>>>>>>>>>>>>>> 2AC 78131E85635804023304 2634 > I,X1 LIT IOR RAM RAM PRTST CONFUSED BADDATA no, unacceptable data 2AD E8B30C1B62F8000032AF 2635 > I,X1 SCR2 RAM LAST2 TESTDIR2 yes, go test DMA dire 2636 >>>>>>>>>>>>>>>>>>>>> 2637 STARTSKP 2AE 4FF31C00637902AE12AE 2637$ WSTE0032 LIT SCR1F * * ****** wasted ****** 2AF 78131F05735F000132B0 2638 TESTDIR2 I,X1 LIT AND RAM PRTST DMADIR SKIP DIRISIN2 test DMA direction 2639 >>>>>>>>>>>>>>>>>>>>> 2B0 78135F1B63597FFC12CF 2640 >DIRISIN2 STC,X1 LIT AND RAM SCR0 LAST2 #7FFC READBC2 input, go process 2B1 F8131D9B6359FFFF32B2 2641 > I,X1 LIT ADD RAM SCR0 LAST2 -1 TESTODD2 write 2642 >>>>>>>>>>>>>>>>>>>>> 2644 ***************************************************************************************************** 2645 * Direction is OUTPUT * 2646 ***************************************************************************************************** 2B2 F8131F1D735F000132B4 2647 TESTODD2 I,X1 LIT AND RAM LADDR2 1 SKIP NOTODD2 need to fetch odd add 2648 SKIPORG 2B3 4FF31C00637902B312B3 2648$ WSTE0033 LIT SCR1F * * ****** wasted ****** 2649 >>>>>>>>>>>>>>>>>>>>> 2B4 D8134F0062F97FF812BA 2650 >NOTODD2 STC SCR0 AND LIT SCR0 #7FF8 WRITEBC2 no, go process 2B5 58130E8072FF800332B7 2651 > I SCR0 IOR LIT #8003 SKIP *+2 yes, BC>4? 2652 >>>>>>>>>>>>>>>>>>>>> 2653 >>>>>>>>>>>>>>>>>>>>> 2B6 78131C1A6378000032BD 2654 > I,X1 ZERO RAM BCNT2 WRITEB2A no, setup for single 2B7 78131D9B6359FFFB32B8 2655 > I,X1 LIT ADD RAM SCR0 LAST2 -5 yes, process 2656 >>>>>>>>>>>>>>>>>>>>> 2657 2B8 D8130F0062F97FF832B9 2658 I SCR0 AND LIT SCR0 #7FF8 2B9 58134D8062F9000412BA 2659 STC SCR0 ADD LIT SCR0 4 2BA B8138C9B62D8000012BB 2660 WRITEBC2 TWC,CST,X1 SCR0 RSUB RAM RAM LAST2 2BB 68330C1A62F8000032BC 2661 I,X1 SCR0 RAM BCNT2 2BC 78131C136378000032BD 2662 I,X1 ZERO RAM CORBC set the BC correction 2BD F8131F05735F004032BE 2663 WRITEB2A I,X1 LIT AND RAM PRTST BCNRDY SKIP WRITEB2B waiting for BCNT? 2664 SKIPORG 2665 >>>>>>>>>>>>>>>>>>>>> 2BE F8131F926378000011BD 2666 >WRITEB2B X1 ONES RAM BCOVERUN DECIBF no, we now have the n 2BF 78131E056358004032C0 2667 > I,X1 LIT XOR RAM RAM PRTST BCNRDY yes, indicate it's he 2668 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 68 PPU5/REV 26 microcode File# 0 second byte count loader 2669 2C0 F0331C1A6359000032C1 2670 I,X1 RAM SCR0 BCNT2 and move the rest of 2C1 68330C1562F8000032C2 2671 I,X1 SCR0 RAM BCNT the parameters over 2C2 E8330C0762F8000032C3 2672 I,X1 SCR0 RAM CLKFIX save for timer fixing 2C3 F0331C1C6359000032C4 2673 I,X1 RAM SCR0 HADDR2 2C4 E8230C1762F8000032C5 2674 I,X1,P SCR0 RAM HADDR 2C5 70331C196359000032C6 2675 I,X1 RAM SCR0 SLOT2 2C6 E8330C1462F8000032C7 2676 I,X1 SCR0 RAM SLOT 2C7 70331C1B6359000032C8 2677 I,X1 RAM SCR0 LAST2 2C8 E8330C1662F8000032C9 2678 I,X1 SCR0 RAM LAST 2C9 F0331C1D6359000032CA 2679 I,X1 RAM SCR0 LADDR2 2CA F8131F1D735F000132CC 2680 I,X1 LIT AND RAM LADDR2 1 SKIP WB2NOT1W need to do a single f 2681 SKIPORG 2CB 4FF31C00637902CB12CB 2681$ WSTE0034 LIT SCR1F * * ****** wasted ****** 2682 >>>>>>>>>>>>>>>>>>>>> 2CC 68230C1862F8000032CE 2683 >WB2NOT1W I,X1,P SCR0 RAM LADDR WB2INTSON no, exit 2CD E823001872F800001E50 2684 > X1,P SCR0 RAM LADDR INDX WB2O1WIP yes, set vector & exit 2685 >>>>>>>>>>>>>>>>>>>>> 2687 BLOCK 4,WB2O1WIOR 2688 >>>>>>>>>>>>>>>>>>>>> E50 E8331C1C637A0F5012CE 2689 >WB2O1WIP X1 LIT IADR PRT0IADR FOUTI1W WB2INTSON set output- port 0 E51 68331C18637A0F5012CE 2690 > X1 LIT IADR PRT1IADR FOUTI1W WB2INTSON E52 68331C14637A0F5012CE 2691 > X1 LIT IADR PRT2IADR FOUTI1W WB2INTSON E53 E8331C10637A0F5012CE 2692 > X1 LIT IADR PRT3IADR FOUTI1W WB2INTSON set output- port 3 2693 >>>>>>>>>>>>>>>>>>>>> 2694 ENDBLOCK 2695 2CE 7A130E0362D9000031BD 2696 WB2INTSON I,X1 SCR8 XOR RAM SCR8 PBITIM DECIBF allow interrupts (loa 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 69 PPU5/REV 26 microcode File# 0 second byte count loader 2698 ***************************************************************************************************** 2699 * Direction is INPUT * 2700 * The BCNT2 variable is always set up for input like we are * 2701 * in single data word store mode. The rollover routines are * 2702 * responsible for readjusting this variable for use with a CORBC * 2703 * of 8, otherwise the correction factor for BCNT2 should be * 2704 * assumed to be 4 if the direction is input. * 2705 ***************************************************************************************************** 2706 2CF 38138C9B62D8000012D0 2707 READBC2 TWC,CST,X1 SCR0 RSUB RAM RAM LAST2 2D0 F8130D9A62F8FFFC32D1 2708 I,X1 SCR0 ADD LIT RAM BCNT2 -4 2D1 F8131F05735F004032D2 2709 I,X1 LIT AND RAM PRTST BCNRDY SKIP READB2B waiting for BCNT? 2710 SKIPORG 2711 >>>>>>>>>>>>>>>>>>>>> 2D2 F8131F926378000011BD 2712 >READB2B X1 ONES RAM BCOVERUN DECIBF no, we now have the n 2D3 78131E056358004032D4 2713 > I,X1 LIT XOR RAM RAM PRTST BCNRDY yes, indicate it's he 2714 >>>>>>>>>>>>>>>>>>>>> 2D4 F0331C1C6359000032D5 2715 I,X1 RAM SCR0 HADDR2 and move the rest of 2D5 68230C1762F8000032D6 2716 I,X1,P SCR0 RAM HADDR the parameters over 2D6 F0331C1D6359000032D7 2717 I,X1 RAM SCR0 LADDR2 2D7 E8230C1862F8000032D8 2718 I,X1,P SCR0 RAM LADDR 2D8 F0331C196359000032D9 2719 I,X1 RAM SCR0 SLOT2 2D9 E8330C1462F8000032DA 2720 I,X1 SCR0 RAM SLOT 2DA F0331C1B6359000032DB 2721 I,X1 RAM SCR0 LAST2 2DB 68330C1662F8000032DC 2722 I,X1 SCR0 RAM LAST 2DC 70331C1A6359000032DD 2723 I,X1 RAM SCR0 BCNT2 2DD E8330C1562F8000032DE 2724 I,X1 SCR0 RAM BCNT 2DE 68330C0762F8000032DF 2725 I,X1 SCR0 RAM CLKFIX save for timer fixing 2DF D9930F0072FF100032E0 2726 I SCR6 AND LIT SOPDDW SKIP B2SINGLE double word? 2727 SKIPORG 2728 >>>>>>>>>>>>>>>>>>>>> 2E0 F8131F1A735F800032E3 2729 >B2SINGLE I,X1 LIT AND RAM BCNT2 #8000 SKIP B2LISBIG if BC < 4, then 2E1 F8130D9562F8FFFC32E4 2730 > I,X1 SCR0 ADD LIT RAM BCNT -4 B2DODUB correct it for CORBC=8 2731 >>>>>>>>>>>>>>>>>>>>> 2732 SKIPORG 2733 >>>>>>>>>>>>>>>>>>>>> 2E2 F8131E856358008031BD 2734 > I,X1 LIT IOR RAM RAM PRTST DMANBZ DECIBF indicate FIFO done 2E3 7A130E0362D9000031BD 2735 >B2LISBIG I,X1 SCR8 XOR RAM SCR8 PBITIM DECIBF allow interrupts 2736 >>>>>>>>>>>>>>>>>>>>> 2737 2738 2E4 78131F1663597FFF32E5 2739 B2DODUB I,X1 LIT AND RAM SCR0 LAST (#FFFF-LASTBIT) calculate the real... 2E5 78130D9562D9000032E6 2740 I,X1 SCR0 ADD RAM SCR0 BCNT ...BCNT minus 8 2E6 58130F0072FF800032E8 2741 I SCR0 AND LIT #8000 SKIP BC2WOKBC is (BCNT-8) < 0? 2742 SKIPORG 2E7 4FF31C00637902E712E7 2742$ WSTE0035 LIT SCR1F * * ****** wasted ****** 2743 >>>>>>>>>>>>>>>>>>>>> 2E8 F8131F18735F000132EE 2744 >BC2WOKBC I,X1 LIT AND RAM LADDR 1 SKIP BC2WROLEVEN BC>=8, even or odd 2E9 F8131F16735F800032EA 2745 > I,X1 LIT AND RAM LAST LASTBIT SKIP BC2WBC2NLAST BC<8,is it last? 2746 >>>>>>>>>>>>>>>>>>>>> 2747 >>>>>>>>>>>>>>>>>>>>> 2EA 7A13020372D900003E54 2748 >BC2WBC2NLAST I,X1 SCR8 XOR RAM SCR8 PBITIM INDX BC2WODDINT not last, allow int 2EB 78131E856358008032EC 2749 > I,X1 LIT IOR RAM RAM PRTST DMANBZ set port not busy 2750 >>>>>>>>>>>>>>>>>>>>> 2EC F8130D9662F8800832ED 2751 I,X1 SCR0 ADD LIT RAM LAST (LASTBIT + 8) store value for last 2ED E8331C156378FFF831BD 2752 I,X1 LIT RAM BCNT -8 DECIBF set BCNT & return 2753 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 70 PPU5/REV 26 microcode File# 0 second byte count loader 2754 SKIPORG 2755 >>>>>>>>>>>>>>>>>>>>> 2EE 78131F15735F000432F0 2756 >BC2WROLEVEN I,X1 LIT AND RAM BCNT 4 SKIP BC2WEVNOADJ even adr, do we ne 2EF 78131F15735F000432F5 2757 > I,X1 LIT AND RAM BCNT 4 SKIP BC2WODDADJBC odd adr,do we nee 2758 >>>>>>>>>>>>>>>>>>>>> 2759 >>>>>>>>>>>>>>>>>>>>> 2F0 7A130E0362D9000031BD 2760 >BC2WEVNOADJ I,X1 SCR8 XOR RAM SCR8 PBITIM DECIBF everything ok, exit 2F1 78131D956358FFFC32F2 2761 > I,X1 LIT ADD RAM RAM BCNT -4 BCNT needs adjustment 2762 >>>>>>>>>>>>>>>>>>>>> 2F2 78131D966358000432F0 2763 I,X1 LIT ADD RAM RAM LAST 4 BC2WEVNOADJ LAST needs adjustm 2764 2765 SKIPORG 2F3 4FF31C00637902F312F3 2765$ WSTE0036 LIT SCR1F * * ****** wasted ****** 2766 >>>>>>>>>>>>>>>>>>>>> 2F4 7A13020372D900003E54 2767 >BC2WODJM I,X1 SCR8 XOR RAM SCR8 PBITIM INDX BC2WODDINT BCNT okay, set odd 2F5 F8131D956358FFFC32F6 2768 >BC2WODDADJBC I,X1 LIT ADD RAM RAM BCNT -4 BCNT needs adjustment 2769 >>>>>>>>>>>>>>>>>>>>> 2F6 78131D966358000412F4 2770 X1 LIT ADD RAM RAM LAST 4 BC2WODJM LAST needs adjustment 2771 BLOCK 4,BC2WOIXOR 2772 >>>>>>>>>>>>>>>>>>>>> E54 E8331C1C637A0F4011BD 2773 >BC2WODDINT X1 LIT IADR PRT0IADR FINPINT2WODD DECIBF set int addr,return E55 68331C18637A0F4011BD 2774 > X1 LIT IADR PRT1IADR FINPINT2WODD DECIBF set int addr,return E56 68331C14637A0F4011BD 2775 > X1 LIT IADR PRT2IADR FINPINT2WODD DECIBF set int addr,return E57 E8331C10637A0F4011BD 2776 > X1 LIT IADR PRT3IADR FINPINT2WODD DECIBF set int addr,return 2777 >>>>>>>>>>>>>>>>>>>>> 2778 ENDBLOCK 2779 TITLE.MAC memory address loader 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 71 PPU5/REV 26 microcode File# 0 memory address loader 2780 ***************************************************************************************************** 2781 * * 2782 * This part sets up the SLOT, HADDR, and LADDR variables. These * 2783 * variables are stored into SBCB, SBHC, and SBLC (respectively) when the * 2784 * PPU does transfers. They are set up for double word reads for the output * 2785 * direction and for single data word writes for the input direction. XOR * 2786 * constants are used to change these values to single word reads or double * 2787 * data word stores when needed. * 2788 * * 2789 ***************************************************************************************************** 2F7 F8131F2C63590F0032F8 2791 ADDIR I,X1 LIT AND RAM SCR0 TEMP #0F00 get slot number 2F8 F8131F05735F000132FA 2792 I,X1 LIT AND RAM PRTST DMADIR SKIP DIRISRD figure direction 2793 SKIPORG 2F9 4FF31C00637902F912F9 2793$ WSTE0037 LIT SCR1F * * ****** wasted ****** 2794 >>>>>>>>>>>>>>>>>>>>> 2FA D8120E8062F98063BEF0 2795 >DIRISRD I SCR0 IOR LIT SCR0 WRITBITS POP DIDNTPOP write into memory 2FB D8120E8062F9B02DBEF0 2796 > I SCR0 IOR LIT SCR0 READBITS POP DIDNTPOP read from memory 2797 >>>>>>>>>>>>>>>>>>>>> 2FC 78130F1462F88FFF32FD 2799 LDMA1 I,X1 SCR0 AND LIT RAM SLOT #8FFF set bus control 2FD 70331C2C2359000032FE 2800 I,X1 RAM SCR0,L TEMP 2FE F8030F1762F830FF32FF 2801 I,X1,P SCR0 AND LIT RAM HADDR #30FF set command word 2FF 68A30C1862F8000031BD 2802 I,X1,P SCR2 RAM LADDR DECIBF 2803 2804 300 78130F1962F88FFF3301 2805 LDMA2 I,X1 SCR0 AND LIT RAM SLOT2 #8FFF set destination 301 F0331C2C235900003302 2806 I,X1 RAM SCR0,L TEMP fix up command word 302 78130F1C62F830FF3303 2807 I,X1 SCR0 AND LIT RAM HADDR2 #30FF 303 E8B30C1D62F8000031BD 2808 I,X1 SCR2 RAM LADDR2 DECIBF 2809 304 4AF31C006379D00011B7 2810 BADDATA LIT SCRB #D000 BADCOMM illegal data, assert 2811 TITLE.MAC Call Back Needed Interrupt processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 72 PPU5/REV 26 microcode File# 0 Call Back Needed Interrupt processor 2812 ***************************************************************************************************** 2813 * * 2814 * Call Back Needed interrupt routine. * 2815 * * 2816 ***************************************************************************************************** 2818 VECTOR 2819 >>>>>>>>>>>>>>>>>>>>> F10 C8311C00636A0004130D 2820 >CBNINT LIT SBRFI RFIOUT CBNINT1 RTO cleared, start ca F11 C8311C00636A0004130D 2821 > LIT SBRFI RFIOUT CBNINT1 RTO cleared, start ca F12 C8311C00636A0004130D 2822 > LIT SBRFI RFIOUT CBNINT1 RTO cleared, start ca F13 C8311C00636A0004130D 2823 > LIT SBRFI RFIOUT CBNINT1 RTO cleared, start ca F14 C8311C00636A0004130D 2824 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back F15 C8311C00636A0004130D 2825 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back F16 C8311C00636A0004130D 2826 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back F17 C8311C00636A0004130D 2827 > LIT SBRFI RFIOUT CBNINT1 RTO set, do call back F18 D8331C006539030B5309 2828 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F19 D8331C006539030B5309 2829 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F1A D8331C006539030B5309 2830 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F1B D8331C006539030B5309 2831 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F1C D8331C006539030B5309 2832 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F1D D8331C006539030B5309 2833 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F1E D8331C006539030B5309 2834 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go F1F D8331C006539030B5309 2835 > SBST SCR0 CBNERR,P CONGODIE BUS Parity Error, go 2836 >>>>>>>>>>>>>>>>>>>>> 2837 ENDVECTOR 305 4AF31C0063791000133E 2839 PEGODIE LIT SCRB #1000 SAVEIBF 306 4AF31C0063792000133E 2840 BFGODIE LIT SCRB #2000 SAVEIBF 307 CAF31C0063795000133E 2841 RTOGODIE LIT SCRB #5000 SAVEIBF 308 CAF31C0063796000133E 2842 RESGODIE LIT SCRB #6000 SAVEIBF 309 4AF31C006379B000133E 2843 CONGODIE LIT SCRB #B000 SAVEIBF 2845 CIRESERR HALT Call Back Response Time-out Error 30A 4FF31C006379030A130A 2845$ CIRESERR LIT SCR1F * * Call Back Response Ti 2846 2847 CBNERR HALT Bus Parity Error on Call Back Needed Interrupt 30B 4FF31C006379030B130B 2847$ CBNERR LIT SCR1F * * Bus Parity Error on C 2848 2849 CIINPERR HALT Call Back Input Bus Parity Error or Bad Flags 30C 4FF31C006379030C130C 2849$ CIINPERR LIT SCR1F * * Call Back Input Bus P 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 73 PPU5/REV 26 microcode File# 0 Call Back Needed Interrupt processor 2851 ***************************************************************************************************** 2852 * We come here when someone has attempted to send us * 2853 * something on the bus and we are accepting CBN interrupts. * 2854 * We will set RFI then wait for the data to show up. * 2855 * We will place it into a circular buffer of such requests * 2856 * unless it is an interrupt poll, which we will service * 2857 * directly. * 2858 ***************************************************************************************************** 2859 30D CBB10C0062ED0000130E 2860 CBNINT1 SCRE INDX2 address RAM 30E 5A130E8062F90010130F 2861 SCR8 IOR LIT SCR8 CBNIM temp. mask off CBN in 30F 4A310C0062F700001310 2862 SCR8 IMR (since it must come f 310 DA130E0062F900101311 2863 SCR8 XOR LIT SCR8 CBNIM and restore scr8 311 5AD30D8062F900011312 2864 SCRB ADD LIT SCRB 1 set 'New BUS Transfer' 312 48331C236378007D1316 2865 X2 LIT RAM BIST CBNTO CINOTIBF and setup a CBN time- 2867 STARTSKP 313 58131DA37358FFFF1315 2868 CICKTO X2 LIT ADD RAM RAM BIST -1 SKIP CINOTTO time-out? 2869 >>>>>>>>>>>>>>>>>>>>> 314 D8331C006539030A5308 2870 > SBST SCR0 CIRESERR,P RESGODIE yes, go DIE! 315 5C130F0072FF00401316 2871 >CINOTTO SCR10 AND LIT IBF SKIP CINOTIBF no, IBF? 2872 >>>>>>>>>>>>>>>>>>>>> 2873 >>>>>>>>>>>>>>>>>>>>> 316 DC331C00653900001313 2874 >CINOTIBF SBST SCR10 CICKTO get S-BUS status again 317 D8331C23653800001318 2875 > X2 SBST RAM BIST yes, save input data 2876 >>>>>>>>>>>>>>>>>>>>> 318 D8331C1E65F800001319 2877 X2 SBHC RAM BIHC fetch the first word 319 D8331C1F66780000131A 2878 X2 SBLC RAM BILC ...into the current b 31A 58331C2267B80000131B 2879 X2 SBFT RAM BIFT ...and slot info too 2880 31B 5C131F2363597030131C 2881 X2 LIT AND RAM SCR10 BIST FLAGMASK isolate flags for test 31C D8131F23735F0080131E 2882 X2 LIT AND RAM BIST DWTIN SKIP CINOTDWT Double Word Transfer? 2883 SKIPORG 31D 4FF31C006379031D131D 2883$ WSTE0038 LIT SCR1F * * ****** wasted ****** 2884 >>>>>>>>>>>>>>>>>>>>> 31E 5C130D8062F9DFE01323 2885 >CINOTDWT SCR10 ADD LIT SCR10 -COMMCOMM CIPROCSW (single word) 31F DC130D8062F9DFF01320 2886 > SCR10 ADD LIT SCR10 -COMMDATA (double word) 2887 >>>>>>>>>>>>>>>>>>>>> 320 D8331C2066F800001321 2888 X2 SBHD RAM BIHD this is double word, 321 58331C21677800001322 2889 X2 SBLD RAM BILD ...get the second word 322 5C130E8072FF00001324 2890 SCR10 IOR LIT 0 SKIP CINOTDAT DWT, good Command & D 2891 323 DC130E8072FF00001326 2892 CIPROCSW SCR10 IOR LIT 0 SKIP CINOTCOM single, good Command? 2893 SKIPORG 2894 >>>>>>>>>>>>>>>>>>>>> 324 58131F23735F40001338 2895 >CINOTDAT X2 LIT AND RAM BIST BPE SKIP CINOTBPE no, die! 325 5B530F0072FF0003133A 2896 > SCRD AND LIT 3 SKIP CIEXIT clear RFI? 2897 >>>>>>>>>>>>>>>>>>>>> 2898 >>>>>>>>>>>>>>>>>>>>> 326 58131F23735F40001338 2899 >CINOTCOM X2 LIT AND RAM BIST BPE SKIP CINOTBPE no, die! 327 5C131E1E635960001328 2900 > X2 LIT XOR RAM SCR10 BIHC #6000 check for Interrupt P 2901 >>>>>>>>>>>>>>>>>>>>> 328 DC130E8072FF0000132A 2902 SCR10 IOR LIT 0 SKIP CINOTPOL 2903 SKIPORG 329 4FF31C00637903291329 2903$ WSTE0039 LIT SCR1F * * ****** wasted ****** 2904 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 74 PPU5/REV 26 microcode File# 0 Call Back Needed Interrupt processor 32A 5B530F0072FF0003133A 2905 >CINOTPOL SCRD AND LIT 3 SKIP CIEXIT not a Poll- clear RFI? 32B DC131F22E359000F132C 2906 > X2 LIT AND,X RAM SCR10 BIFT #000F get FROM slot # 2907 >>>>>>>>>>>>>>>>>>>>> 32C DC130E8062F90011132D 2908 SCR10 IOR LIT SCR10 RTODATA output Poll response 32D 59D30E8072FF0000132E 2909 SCR7 IOR LIT 0 SKIP CIISUS are we interrupting? 2910 SKIPORG 2911 >>>>>>>>>>>>>>>>>>>>> 32E 49F00C0062F000001332 2912 >CIISUS SCR7 SBHC CIOURPOL say it's us, send the 32F C8301C00637000001330 2913 > LIT SBHC 0 no, give negative res 2914 >>>>>>>>>>>>>>>>>>>>> 330 C8301C00637100001331 2915 LIT SBLC 0 331 4C310C0062F5000010EE 2916 SCR10 SBCB RTODELAY wait for RTO and exit 2917 332 49F10C0062ED00001333 2918 CIOURPOL SCR7 INDX2 and send the current 333 50301C05635100001334 2919 X2 RAM SBLC PRTST port status 334 4C310C0062F500001335 2920 SCR10 SBCB 335 D8131F056358E7FF1336 2921 X2 LIT AND RAM RAM PRTST INTCLR clear everything up 336 48311C00636600001337 2922 LIT SBINT 0 337 49F21C0063790000BEF0 2923 I LIT SCR7 0 POP DIDNTPOP & exit 2924 2925 SKIPORG 2926 >>>>>>>>>>>>>>>>>>>>> 338 4AF31C0063792000133D 2927 >CINOTBPE LIT SCRB #2000 CIBSE wrong flags bus error 339 4AF31C0063791000133D 2928 > LIT SCRB #1000 CIBSE bus parity error 2929 >>>>>>>>>>>>>>>>>>>>> 2931 SKIPORG 2932 >>>>>>>>>>>>>>>>>>>>> 33A 5B530D8062F90001133C 2933 >CIEXIT SCRD ADD LIT SCRD 1 CIEXIT1 allow more inputs 33B 5A130E8062F90010133A 2934 > SCR8 IOR LIT SCR8 CBNIM CIEXIT all filled up, clear 2935 >>>>>>>>>>>>>>>>>>>>> 33C 5B920D8062F90001BEF0 2936 CIEXIT1 I SCRE ADD LIT SCRE 1 POP DIDNTPOP 2937 33D CBB00C0062F3030C5345 2938 CIBSE SCRE INDX1 CIINPERR,P WTFORPON 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 75 PPU5/REV 26 microcode File# 0 Call Back Needed Interrupt processor 2940 ***************************************************************************************************** 2941 * Bus error garbage * 2942 ***************************************************************************************************** 2943 33E 4BB10C0062F30000133F 2944 SAVEIBF SCRE INDX1 address the RAM 33F 68330C2362F800001340 2945 X1 SCR0 RAM BIST save input data 340 F8331C1E65F800001341 2946 X1 SBHC RAM BIHC 341 F8331C1F667800001342 2947 X1 SBLC RAM BILC 342 F8331C2066F800001343 2948 X1 SBHD RAM BIHD 343 F8331C21677800001344 2949 X1 SBLD RAM BILD 344 78331C2267B800001345 2950 X1 SBFT RAM BIFT WTFORPON 2951 345 C8311C00636D00001346 2952 WTFORPON LIT INDX2 0 move the BUS Inputs t 346 DAD30F2662F8F0001347 2953 X2 SCRB AND LIT RAM WRURES2A #F000 WRU responses. 347 78131F2363590F001348 2954 X1 LIT AND RAM SCR0 BIST #0F00 348 58130EA662D800001349 2955 X2 SCR0 IOR RAM RAM WRURES2A 349 78131F22635900FF134A 2956 X1 LIT AND RAM SCR0 BIFT #00FF 34A D8130EA662D80000134B 2957 X2 SCR0 IOR RAM RAM WRURES2A 34B 78131F23635930BF134C 2958 X1 LIT AND RAM SCR0 BIST #30BF 34C C8330C2762F80000134D 2959 X2 SCR0 RAM WRURES2B 34D F8131F2263590F00134E 2960 X1 LIT AND RAM SCR0 BIFT #0F00 34E D8130EA762D80000134F 2961 X2 SCR0 IOR RAM RAM WRURES2B 34F F0331C1E635900001350 2962 X1 RAM SCR0 BIHC 350 48330C2862F800001351 2963 X2 SCR0 RAM WRURES3A 351 F0331C1F635900001352 2964 X1 RAM SCR0 BILC 352 48330C2962F800001353 2965 X2 SCR0 RAM WRURES3B 353 F0331C20635900001354 2966 X1 RAM SCR0 BIHD 354 48330C2A62F800001355 2967 X2 SCR0 RAM WRURES4A 355 F0331C21635900001356 2968 X1 RAM SCR0 BILD 356 48330C2B62F800001357 2969 X2 SCR0 RAM WRURES4B 357 D8331C00633B00001358 2970 T4 SBRST then save the output 358 C8311C00636D00011359 2971 LIT INDX2 1 359 D8331C0067B90000135A 2972 SBFT SCR0 get our slot number 35A 58130F00E2F9F000135B 2973 SCR0 AND,X LIT SCR0 #F000 35B E8330C2C62F8035C51EB 2974 X1 SCR0 RAM TEMP *+1,PUSH SHIFTL4 35C 58130E8062F9009B135D 2975 SCR0 IOR LIT SCR0 COPYTOME 35D 48310C0062F50000135E 2976 SCR0 SBCB start the transfer 35E 48331C006379007D1362 2977 X2 LIT SCR0 CTMTO CTMNIBF and setup a time-out 2978 STARTSKP 35F 58130D8072F9FFFF1361 2979 CTMCKTO SCR0 ADD LIT SCR0 -1 SKIP CTMNOTTO time-out? 2980 >>>>>>>>>>>>>>>>>>>>> 360 D8311C00633F00001367 2981 > CKBSE yes, skip it! 361 5C130F0072FF00401362 2982 >CTMNOTTO SCR10 AND LIT IBF SKIP CTMNIBF no, IBF? 2983 >>>>>>>>>>>>>>>>>>>>> 2984 2985 >>>>>>>>>>>>>>>>>>>>> 362 5C331C0065390000135F 2986 >CTMNIBF SBST SCR10 CTMCKTO get S-BUS status again 363 D8331C2465F800001364 2987 > X2 SBHC RAM WRURES1A yes, save input data 2988 >>>>>>>>>>>>>>>>>>>>> 364 58331C25667800001365 2989 X2 SBLC RAM WRURES1B 365 D8331C2666F800001366 2990 X2 SBHD RAM WRURES2A 366 D8331C27677800001367 2991 X2 SBLD RAM WRURES2B 367 DAD30E8072FF00001368 2992 CKBSE SCRB IOR LIT 0 SKIP ISBSE should we pull on BSE? 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 76 PPU5/REV 26 microcode File# 0 Call Back Needed Interrupt processor 2994 SKIPORG 2995 >>>>>>>>>>>>>>>>>>>>> 368 C8311C00637520001369 2996 >ISBSE LIT SBCB BSE yes, assert BUS ERROR 369 58311C00633F0000136A 2997 > NOP 2998 >>>>>>>>>>>>>>>>>>>>> 2999 36A C8311C0063730000136B 3000 LIT INDX1 0 now save all the Byte 36B C8311C00636D0001136C 3001 LIT INDX2 1 Counts and Addresses 36C 58301C00633F036D5385 3002 *+1,PUSH GETFLAGS 36D 48330C2862F80000136E 3003 X2 SCR0 RAM WRURES3A 36E C8730C2962F80000136F 3004 X2 SCR1 RAM WRURES3B 36F 48B30C2A62F800001370 3005 X2 SCR2 RAM WRURES4A 370 C8F30C2B62F800001371 3006 X2 SCR3 RAM WRURES4B 3007 371 C8311C00637300011372 3008 LIT INDX1 1 372 48311C00636D00021373 3009 LIT INDX2 2 373 D8301C00633F03745385 3010 *+1,PUSH GETFLAGS 374 48330C2462F800001375 3011 X2 SCR0 RAM WRURES1A 375 48730C2562F800001376 3012 X2 SCR1 RAM WRURES1B 376 C8B30C2662F800001377 3013 X2 SCR2 RAM WRURES2A 377 C8F30C2762F800001378 3014 X2 SCR3 RAM WRURES2B 3015 378 48311C00637300021379 3016 LIT INDX1 2 379 58301C00633F037A5385 3017 *+1,PUSH GETFLAGS 37A C8330C2862F80000137B 3018 X2 SCR0 RAM WRURES3A 37B 48730C2962F80000137C 3019 X2 SCR1 RAM WRURES3B 37C C8B30C2A62F80000137D 3020 X2 SCR2 RAM WRURES4A 37D C8F30C2B62F80000137E 3021 X2 SCR3 RAM WRURES4B 3022 37E C8311C0063730003137F 3023 LIT INDX1 3 37F C8311C00636D00031380 3024 LIT INDX2 3 380 D8301C00633F03815385 3025 *+1,PUSH GETFLAGS 381 C8330C2462F800001382 3026 X2 SCR0 RAM WRURES1A 382 48730C2562F800001383 3027 X2 SCR1 RAM WRURES1B 383 C8B30C2662F800001384 3028 X2 SCR2 RAM WRURES2A 384 48F30C2762F800009384 3029 X2 SCR3 RAM WRURES2B POP * That's it! Go die!!! 385 F8131F14E3590F001386 3031 GETFLAGS X1 LIT AND,X RAM SCR0 SLOT #0F00 get the slot number, 386 E8330C2C62F8038751EB 3032 X1 SCR0 RAM TEMP *+1,PUSH SHIFTL4 387 78531F176359000F1388 3033 X1 LIT AND RAM SCR1 HADDR #000F some of the high addr 388 E8730C2C62F800001389 3034 X1 SCR1 RAM TEMP 389 78130EAC62D90000138A 3035 X1 SCR0 IOR RAM SCR0 TEMP 38A F0331C0443590000138B 3036 X1 RAM SCR0,H FLAGS and the flags 3037 38B F0731C1863590000138C 3038 X1 RAM SCR1 LADDR 38C 70B31C0563590000138D 3039 X1 RAM SCR2 PRTST 38D 70F31C15635900009EF0 3040 X1 RAM SCR3 BCNT POP DIDNTPOP 3041 TITLE.MAC FIFO Input processor for Single Data Word Store Mode 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 77 PPU5/REV 26 microcode File# 0 FIFO Input processor for Single Data Word Store Mode 3042 ***************************************************************************************************** 3043 * * 3044 * FIFO Input processor for Single Data Word Store Mode * 3045 * * 3046 ***************************************************************************************************** 3048 VECTOR 3049 >>>>>>>>>>>>>>>>>>>>> F20 50213C1763500000138F 3050 >FINPINT1W X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WR F21 50213C1763500000138F 3051 > X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WR F22 50213C1763500000138F 3052 > X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WR F23 50213C1763500000138F 3053 > X2,C,P RAM SBHC HADDR FIWRITE RTO cleared, start WR F24 D8321C00633F0000BEF0 3054 > IP POP DIDNTPOP RTO set, wait for it F25 D8321C00633F0000BEF0 3055 > IP POP DIDNTPOP RTO set, wait for it F26 D8321C00633F0000BEF0 3056 > IP POP DIDNTPOP RTO set, wait for it F27 D8321C00633F0000BEF0 3057 > IP POP DIDNTPOP RTO set, wait for it F28 58331C006539038E5309 3058 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F29 58331C006539038E5309 3059 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F2A 58331C006539038E5309 3060 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F2B 58331C006539038E5309 3061 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F2C 58331C006539038E5309 3062 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F2D 58331C006539038E5309 3063 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F2E 58331C006539038E5309 3064 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go F2F 58331C006539038E5309 3065 > SBST SCR0 FINPERR1,P CONGODIE BUS Parity Error, go 3066 >>>>>>>>>>>>>>>>>>>>> 3067 ENDVECTOR 3068 3069 3070 3071 FINPERR1 HALT Bus Parity Error Set on Interrupt for Single Data Word Store in Single Dat 38E 4FF31C006379038E138E 3071$ FINPERR1 LIT SCR1F * * Bus Parity Error Set 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 78 PPU5/REV 26 microcode File# 0 FIFO Input processor for Single Data Word Store Mode 3073 38F D0211C18635100001390 3074 FIWRITE X2,P RAM SBLC LADDR complete the WRITE 390 D8311C0060EE00001391 3075 X2,T2 DPIN SBHD 391 50311C14635500001392 3076 X2 RAM SBCB SLOT 392 D8311C0060EF00001393 3077 X2,T2 DPIN SBLD 393 58131D957358FFFC1394 3078 X2 LIT ADD RAM RAM BCNT -4 SKIP FIEXIT decrement BC & check 3079 SKIPORG 3080 >>>>>>>>>>>>>>>>>>>>> 394 D8021D9863580001BEF0 3081 >FIEXIT I,X2,P LIT ADD RAM RAM LADDR 1 POP DIDNTPOP not end, inc address 395 D8031D98635800011396 3082 > X2,P LIT ADD RAM RAM LADDR 1 make sure the address 3083 >>>>>>>>>>>>>>>>>>>>> 396 58131F16735F80001398 3084 X2 LIT AND RAM LAST LASTBIT SKIP FINOTEND end, last BC? 3085 SKIPORG 397 4FF31C00637903971397 3085$ WSTE0040 LIT SCR1F * * ****** wasted ****** 3086 >>>>>>>>>>>>>>>>>>>>> 398 D8131E92735F0000139F 3087 >FINOTEND X2 LIT IOR RAM BCOVERUN 0 SKIP FINEXTBC no, overrun? 399 5A130E8362D90000139A 3088 >FIEND X2 SCR8 IOR RAM SCR8 PBITIM yes, disallow interru 3089 >>>>>>>>>>>>>>>>>>>>> 39A 4A310C0062F70000139B 3090 FIEND2 SCR8 IMR 39B 58121E8563580080BEF0 3091 IP,X2 LIT IOR RAM RAM PRTST DMANBZ POP DIDNTPOP set FIFO not busy 39C 4A310C0062F70000139D 3093 FIORUN SCR8 IMR 39D D8121E8563580050BEF0 3094 IP,X2 LIT IOR RAM RAM PRTST OVRRUN POP DIDNTPOP say waiting & exit 3095 3096 SKIPORG 3097 >>>>>>>>>>>>>>>>>>>>> 39E 5A130E8362D90000139C 3098 > X2 SCR8 IOR RAM SCR8 PBITIM FIORUN yes, disable interrup 39F 58131E856358001013A0 3099 >FINEXTBC X2 LIT IOR RAM RAM PRTST BCROLL no, signal BC rollover 3100 >>>>>>>>>>>>>>>>>>>>> 3A0 D8131C126378000013A1 3101 X2 ZERO RAM BCOVERUN set overrun detector, 3A1 53331C1C6359000013A2 3102 X2 RAM SCRC HADDR2 and move the rest of 3A2 4B230C1762F8000013A3 3103 X2,P SCRC RAM HADDR the parameters over 3A3 D3331C1D6359000013A4 3104 X2 RAM SCRC LADDR2 3A4 4B230C1862F8000013A5 3105 X2,P SCRC RAM LADDR 3A5 D3331C196359000013A6 3106 X2 RAM SCRC SLOT2 3A6 4B330C1462F8000013A7 3107 X2 SCRC RAM SLOT 3A7 D3331C1B6359000013A8 3108 X2 RAM SCRC LAST2 3A8 4B330C1662F8000013A9 3109 X2 SCRC RAM LAST 3A9 D3331C1A6359000013AA 3110 X2 RAM SCRC BCNT2 check the new BC for 3AA CB330C0762F8000013AB 3111 X2 SCRC RAM CLKFIX set for clock adjuster 3AB 58131F1A735F800013AD 3112 X2 LIT AND RAM BCNT2 #8000 SKIP FIISBIG if BC < 4, then 3113 SKIPORG 3114 >>>>>>>>>>>>>>>>>>>>> 3AC 4B330C1562F800001399 3115 > X2 SCRC RAM BCNT FIEND don't allow inter 3AD 4B320C1562F80000BEF0 3116 >FIISBIG I,X2 SCRC RAM BCNT POP DIDNTPOP otherwise, continue 3117 >>>>>>>>>>>>>>>>>>>>> 3118 TITLE.MAC FIFO Input processor for Double Data Word Store Mode 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 79 PPU5/REV 26 microcode File# 0 FIFO Input processor for Double Data Word Store Mode 3119 ***************************************************************************************************** 3120 * * 3121 * FIFO Input processor for Double Data Word Store Mode -- Double Data Store Routine * 3122 * * 3123 ***************************************************************************************************** 3125 VECTOR 3126 >>>>>>>>>>>>>>>>>>>>> F30 D8133E176350700013AF 3127 >FINPINT2W X2,C LIT XOR RAM SBHC HADDR XORHADDR2W FIWRITE2W RTO cleared, start W F31 D8133E176350700013AF 3128 > X2,C LIT XOR RAM SBHC HADDR XORHADDR2W FIWRITE2W RTO cleared, start W F32 D8133E176350700013AF 3129 > X2,C LIT XOR RAM SBHC HADDR XORHADDR2W FIWRITE2W RTO cleared, start W F33 D8133E176350700013AF 3130 > X2,C LIT XOR RAM SBHC HADDR XORHADDR2W FIWRITE2W RTO cleared, start W F34 D8321C00633F0000BEF0 3131 > IP POP DIDNTPOP RTO set, wait for it F35 D8321C00633F0000BEF0 3132 > IP POP DIDNTPOP RTO set, wait for it F36 D8321C00633F0000BEF0 3133 > IP POP DIDNTPOP RTO set, wait for it F37 D8321C00633F0000BEF0 3134 > IP POP DIDNTPOP RTO set, wait for it F38 D8331C00653903AE5309 3135 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F39 D8331C00653903AE5309 3136 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F3A D8331C00653903AE5309 3137 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F3B D8331C00653903AE5309 3138 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F3C D8331C00653903AE5309 3139 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F3D D8331C00653903AE5309 3140 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F3E D8331C00653903AE5309 3141 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go F3F D8331C00653903AE5309 3142 > SBST SCR0 FINPERR2,P CONGODIE BUS Parity Error, go 3143 >>>>>>>>>>>>>>>>>>>>> 3144 ENDVECTOR 3146 FINPERR2 HALT Bus Parity Error Set on Interrupt for Double Data Word Store Routine 3AE 4FF31C00637903AE13AE 3146$ FINPERR2 LIT SCR1F * * Bus Parity Error Set 3AF 50211C186351000013B0 3148 FIWRITE2W X2,P RAM SBLC LADDR complete the WRITE 3B0 58311C0060EE000013B1 3149 X2,T2 DPIN SBHD 3B1 D8031D986358000213B2 3150 X2,P LIT ADD RAM RAM LADDR 2 increment address 3B2 58311C0060EF000013B3 3151 X2,T2 DPIN SBLD 3B3 58133D957358FFF813B5 3152 X2,C LIT ADD RAM RAM BCNT -8 SKIP FI2WEXIT decrement BC, check f 3153 SKIPORG 3154 >>>>>>>>>>>>>>>>>>>>> 3B4 D8311C0060E8000013B9 3155 > X2,T2 DPIN SBHW3 FI2WCKLAST BC exhausted,finish 3B5 D8311C0060E8000013B6 3156 >FI2WEXIT X2,T2 DPIN SBHW3 BC not exhausted,done 3157 >>>>>>>>>>>>>>>>>>>>> 3B6 58101E146355100013B7 3158 X2 LIT XOR RAM SBCB SLOT XORSLOT2W 3B7 D8311C0060E9000013B8 3159 X2,T2 DPIN SBLW3 finish xfer 3B8 D8301C00633F00009EF0 3160 X2 POP DIDNTPOP index must be same af 3B9 D8101E146355100013BA 3161 FI2WCKLAST X2 LIT XOR RAM SBCB SLOT XORSLOT2W 3BA D8311C0060E9000013BB 3162 X2,T2 DPIN SBLW3 FI2WCKWORD finish xfer 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 80 PPU5/REV 26 microcode File# 0 FIFO Input processor for Double Data Word Store Mode 3164 ***************************************************************************************************** 3165 * If there is a whole word left, the interrupt address is switched to * 3166 * the odd single word store routine to handle. * 3167 ***************************************************************************************************** 3168 STARTSKP 3BB 58131F16735F000413BC 3169 FI2WCKWORD X2 LIT AND RAM LAST 0004 SKIP FI2WPARTWRD is a whole word le 3170 >>>>>>>>>>>>>>>>>>>>> 3BC D8131F16735F800013C0 3171 >FI2WPARTWRD X2 LIT AND RAM LAST LASTBIT SKIP FI2WNOTLAST < 4 bytes,is last 3BD 58131D966358FFFC13BE 3172 > X2 LIT ADD RAM RAM LAST -4 >=4 bytes,fix up LAST 3173 >>>>>>>>>>>>>>>>>>>>> 3BE 58131195735800041E58 3174 X2 LIT ADD RAM RAM BCNT 4 INDX FI2WODDINT fix up BCNT for odd 3176 BLOCK 4,FI2WOIXOR 3177 >>>>>>>>>>>>>>>>>>>>> E58 C8331C1C637A0F409EF0 3178 >FI2WODDINT X2 LIT IADR PRT0IADR FINPINT2WODD POP DIDNTPOP set int addr,ret E59 48331C18637A0F409EF0 3179 > X2 LIT IADR PRT1IADR FINPINT2WODD POP DIDNTPOP set int addr,ret E5A 48331C14637A0F409EF0 3180 > X2 LIT IADR PRT2IADR FINPINT2WODD POP DIDNTPOP set int addr,ret E5B C8331C10637A0F409EF0 3181 > X2 LIT IADR PRT3IADR FINPINT2WODD POP DIDNTPOP set int addr,ret 3182 >>>>>>>>>>>>>>>>>>>>> 3183 ENDBLOCK 3185 SKIPORG 3BF 4FF31C00637903BF13BF 3185$ WSTE0041 LIT SCR1F * * ****** wasted ****** 3186 >>>>>>>>>>>>>>>>>>>>> 3C0 D8131E92735F000013C3 3187 >FI2WNOTLAST X2 LIT IOR RAM BCOVERUN 0 SKIP FI2WNEXTBC not last,overrun? 3C1 5A130E8362D90000139A 3188 > X2 SCR8 IOR RAM SCR8 PBITIM FIEND2 last,disallow interru 3189 >>>>>>>>>>>>>>>>>>>>> 3190 3191 SKIPORG 3192 >>>>>>>>>>>>>>>>>>>>> 3C2 5A130E8362D90000139C 3193 > X2 SCR8 IOR RAM SCR8 PBITIM FIORUN not ready, disallow i 3C3 D8131E856358001013C4 3194 >FI2WNEXTBC X2 LIT IOR RAM RAM PRTST BCROLL no, signal BC rollover 3195 >>>>>>>>>>>>>>>>>>>>> 3C4 58131C126378000013C5 3196 X2 ZERO RAM BCOVERUN set overrun detector, 3C5 D3331C1C6359000013C6 3197 X2 RAM SCRC HADDR2 and move the rest of 3C6 CB230C1762F8000013C7 3198 X2,P SCRC RAM HADDR the parameters over 3C7 D3331C1D6359000013C8 3199 X2 RAM SCRC LADDR2 3C8 4B230C1862F8000013C9 3200 X2,P SCRC RAM LADDR 3C9 D3331C196359000013CA 3201 X2 RAM SCRC SLOT2 3CA 4B330C1462F8000013CB 3202 X2 SCRC RAM SLOT 3CB 53331C1B6359000013CC 3203 X2 RAM SCRC LAST2 3CC CB330C1662F8000013CD 3204 X2 SCRC RAM LAST 3CD 53331C1A6359000013CE 3205 X2 RAM SCRC BCNT2 3CE 4B330C0762F8000013CF 3206 X2 SCRC RAM CLKFIX set for clock adjuster 3CF DB130D9562F8FFFC13D0 3207 X2 SCRC ADD LIT RAM BCNT -4 correct it for CORBC=8 3208 3D0 5B131F1663597FFF13D1 3209 X2 LIT AND RAM SCRC LAST (#FFFF-LASTBIT) calculate the real... 3D1 5B130D9562D9000013D2 3210 X2 SCRC ADD RAM SCRC BCNT ...BCNT minus 8 3D2 5B130F0072FF800013D4 3211 SCRC AND LIT #8000 SKIP FI2WOKBC is (BCNT-8) < 0? 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 81 PPU5/REV 26 microcode File# 0 FIFO Input processor for Double Data Word Store Mode 3213 ***************************************************************************************************** 3214 * Here we do something like this: * 3215 * If there are less than 8 bytes left AND this is the last * 3216 * BCNT, then we disable interrupts and set DMANBZ so EOR * 3217 * processor will clean up and make sure the entire remaining * 3218 * byte count is contained in LAST. * 3219 * If there are less than 8 bytes left AND this is NOT last BCNT, * 3220 * then the next byte count must only be a single word, so * 3221 * we set the interrupt address to be to the single word * 3222 * interrupt handler. * 3223 * * 3224 * If there are more than 8 bytes left, then we will leave * 3225 * the interrupts on. We need to check whether we will use the * 3226 * single of double word interrupt handler, however. * 3227 * * 3228 * We will use the single word interrupt handler for at * 3229 * least the first word if the first store on this byte count is * 3230 * to an odd address. * 3231 * * 3232 * We also must check to make sure that BCNT and LAST are * 3233 * the types of values that the other routines expect. In other * 3234 * words, BCNT should be of the form 8k where k is an integer if * 3235 * we are storing to an even address (using the double word * 3236 * interrupt handler from the start). If we are going to use the * 3237 * odd single word interrupt handler for the first store, then * 3238 * BCNT should be of the form 8k + 4 where k is an integer. The * 3239 * last few instructions handle this adjustment if it is needed. * 3240 * They check the 4 bit (bit #2) to see whether this adjustment * 3241 * must be made. (Remember also that the opposite adjustment must * 3242 * be made to LAST for everything to remain correct.) * 3243 ***************************************************************************************************** 3244 3245 SKIPORG 3D3 4FF31C00637903D313D3 3245$ WSTE0042 LIT SCR1F * * ****** wasted ****** 3246 >>>>>>>>>>>>>>>>>>>>> 3D4 D8131F18735F000113DC 3247 >FI2WOKBC X2 LIT AND RAM LADDR 1 SKIP FI2WROLEVEN BC >= 8,even or od 3D5 58131F16735F800013D6 3248 > X2 LIT AND RAM LAST LASTBIT SKIP FI2WBC2NLAST BC<8,is it last? 3249 >>>>>>>>>>>>>>>>>>>>> 3250 >>>>>>>>>>>>>>>>>>>>> 3D6 58331000733F00001E58 3251 >FI2WBC2NLAST X2 INDX FI2WODDINT not last,1 word int 3D7 5A130E8362D9000013D8 3252 > X2 SCR8 IOR RAM SCR8 PBITIM last, disallow interr 3253 >>>>>>>>>>>>>>>>>>>>> 3D8 4A310C0062F7000013D9 3254 SCR8 IMR 3D9 D8131E856358008013DA 3255 X2 LIT IOR RAM RAM PRTST DMANBZ set port not busy 3DA 5B130D9662F8800813DB 3256 X2 SCRC ADD LIT RAM LAST (LASTBIT + 8) store value for last 3DB 48321C156378FFF8BEF0 3257 I,X2 LIT RAM BCNT -8 POP DIDNTPOP set BCNT & return 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 82 PPU5/REV 26 microcode File# 0 FIFO Input processor for Double Data Word Store Mode 3259 ***************************************************************************************************** 3260 * When we get here, we know that the BCNT is more than 8. * 3261 ***************************************************************************************************** 3262 3263 SKIPORG 3264 >>>>>>>>>>>>>>>>>>>>> 3DC D8131F15735F000413DE 3265 >FI2WROLEVEN X2 LIT AND RAM BCNT 4 SKIP FI2WEVNOADJ even adr, do we ne 3DD 58131F15735F000413E3 3266 > X2 LIT AND RAM BCNT 4 SKIP FI2WODDADJBC odd adr,do we nee 3267 >>>>>>>>>>>>>>>>>>>>> 3268 >>>>>>>>>>>>>>>>>>>>> 3DE D8321C00633F0000BEF0 3269 >FI2WEVNOADJ IP POP DIDNTPOP everything ok, exit 3DF D8131D956358FFFC13E0 3270 > X2 LIT ADD RAM RAM BCNT -4 BCNT needs adjustment 3271 >>>>>>>>>>>>>>>>>>>>> 3E0 D8131D96635800049EF0 3272 X2 LIT ADD RAM RAM LAST 4 POP DIDNTPOP LAST needs adjustment 3273 SKIPORG 3E1 4FF31C00637903E113E1 3273$ WSTE0043 LIT SCR1F * * ****** wasted ****** 3274 >>>>>>>>>>>>>>>>>>>>> 3E2 58331000733F00001E58 3275 > X2 INDX FI2WODDINT BCNT okay, set odd 3E3 58131D956358FFFC13E4 3276 >FI2WODDADJBC X2 LIT ADD RAM RAM BCNT -4 BCNT needs adjustment 3277 >>>>>>>>>>>>>>>>>>>>> 3E4 58131196735800041E58 3278 X2 LIT ADD RAM RAM LAST 4 INDX FI2WODDINT LAST needs adjustme 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 83 PPU5/REV 26 microcode File# 0 FIFO Input processor for Double Data Word Store Mode 3280 ***************************************************************************************************** 3281 * * 3282 * FIFO Input processor for Double Data Word Store Mode - First odd Address Store * 3283 * * 3284 ***************************************************************************************************** 3286 VECTOR 3287 >>>>>>>>>>>>>>>>>>>>> F40 50213C176350000013E6 3288 >FINPINT2WODD X2,C,P RAM SBHC HADDR FIWRITE2WODD RTO cleared, star F41 50213C176350000013E6 3289 > X2,C,P RAM SBHC HADDR FIWRITE2WODD RTO cleared, star F42 50213C176350000013E6 3290 > X2,C,P RAM SBHC HADDR FIWRITE2WODD RTO cleared, star F43 50213C176350000013E6 3291 > X2,C,P RAM SBHC HADDR FIWRITE2WODD RTO cleared, star F44 D8321C00633F0000BEF0 3292 > IP POP DIDNTPOP RTO set, wait for it F45 D8321C00633F0000BEF0 3293 > IP POP DIDNTPOP RTO set, wait for it F46 D8321C00633F0000BEF0 3294 > IP POP DIDNTPOP RTO set, wait for it F47 D8321C00633F0000BEF0 3295 > IP POP DIDNTPOP RTO set, wait for it F48 D8331C00653903E55309 3296 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F49 D8331C00653903E55309 3297 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F4A D8331C00653903E55309 3298 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F4B D8331C00653903E55309 3299 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F4C D8331C00653903E55309 3300 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F4D D8331C00653903E55309 3301 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F4E D8331C00653903E55309 3302 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go F4F D8331C00653903E55309 3303 > SBST SCR0 FINPERR3,P CONGODIE BUS Parity Error, go 3304 >>>>>>>>>>>>>>>>>>>>> 3305 ENDVECTOR 3306 3307 FINPERR3 HALT Bus Parity Error Set on Interrupt for Single Data Word Store in Double Dat 3E5 4FF31C00637903E513E5 3307$ FINPERR3 LIT SCR1F * * Bus Parity Error Set 3308 3309 3E6 D0211C186351000013E7 3310 FIWRITE2WODD X2,P RAM SBLC LADDR complete the WRITE 3E7 58311C0060EE000013E8 3311 X2,T2 DPIN SBHD 3E8 50311C146355000013E9 3312 X2 RAM SBCB SLOT 3E9 58311C0060EF000013EA 3313 X2,T2 DPIN SBLD 3EA 581311957358FFFC1E5C 3314 X2 LIT ADD RAM RAM BCNT -4 INDX SETBACKINT2W dec BCNT, set to 3316 BLOCK 4,SBI2WIOR 3317 >>>>>>>>>>>>>>>>>>>>> E5C 48331C1C637A0F3013EB 3318 >SETBACKINT2W X2 LIT IADR PRT0IADR FINPINT2W FI2WODCKEND set port 0 interru E5D C8331C18637A0F3013EB 3319 > X2 LIT IADR PRT1IADR FINPINT2W FI2WODCKEND set port 1 interru E5E C8331C14637A0F3013EB 3320 > X2 LIT IADR PRT2IADR FINPINT2W FI2WODCKEND set port 2 interru E5F 48331C10637A0F3013EB 3321 > X2 LIT IADR PRT3IADR FINPINT2W FI2WODCKEND set port 3 interru 3322 >>>>>>>>>>>>>>>>>>>>> 3323 ENDBLOCK 3324 3325 STARTSKP 3EB 58131F15735FFFF813EC 3326 FI2WODCKEND X2 LIT AND RAM BCNT -8 SKIP FI2WODNOTEND check for end 3327 >>>>>>>>>>>>>>>>>>>>> 3EC D8021D9863580001BEF0 3328 >FI2WODNOTEND IP,X2,P LIT ADD RAM RAM LADDR 1 POP DIDNTPOP not end,inc addr,retu 3ED D8031D986358000113BB 3329 > X2,P LIT ADD RAM RAM LADDR 1 FI2WCKWORD end inc addr,check 3330 >>>>>>>>>>>>>>>>>>>>> 3331 TITLE.MAC FIFO Output processor 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 84 PPU5/REV 26 microcode File# 0 FIFO Output processor 3332 ***************************************************************************************************** 3333 * * 3334 * FIFO output interrupt processor - Single Word Fetch. * 3335 * * 3336 ***************************************************************************************************** 3338 BLOCK 4,OUT1WIOR 3339 >>>>>>>>>>>>>>>>>>>>> E40 48321C1C637A0F50BEF0 3340 >FOSI1WIP I LIT IADR PRT0IADR FOUTI1W POP DIDNTPOP set output- port 0 E41 C8321C18637A0F50BEF0 3341 > I LIT IADR PRT1IADR FOUTI1W POP DIDNTPOP E42 C8321C14637A0F50BEF0 3342 > I LIT IADR PRT2IADR FOUTI1W POP DIDNTPOP E43 48321C10637A0F50BEF0 3343 > I LIT IADR PRT3IADR FOUTI1W POP DIDNTPOP set output- port 3 3344 >>>>>>>>>>>>>>>>>>>>> 3345 ENDBLOCK 3347 VECTOR 3348 >>>>>>>>>>>>>>>>>>>>> F50 58133E176350100013EF 3349 >FOUTI1W X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start RE F51 58133E176350100013EF 3350 > X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start RE F52 58133E176350100013EF 3351 > X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start RE F53 58133E176350100013EF 3352 > X2,C LIT XOR RAM SBHC HADDR XORCF1W FOREAD1W RTO cleared, start RE F54 D8321C00633F0000BEF0 3353 > IP POP DIDNTPOP RTO set, wait for it F55 D8321C00633F0000BEF0 3354 > IP POP DIDNTPOP RTO set, wait for it F56 D8321C00633F0000BEF0 3355 > IP POP DIDNTPOP RTO set, wait for it F57 D8321C00633F0000BEF0 3356 > IP POP DIDNTPOP RTO set, wait for it F58 58331C00653903EE5309 3357 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F59 58331C00653903EE5309 3358 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F5A 58331C00653903EE5309 3359 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F5B 58331C00653903EE5309 3360 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F5C 58331C00653903EE5309 3361 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F5D 58331C00653903EE5309 3362 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F5E 58331C00653903EE5309 3363 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go F5F 58331C00653903EE5309 3364 > SBST SCR0 FOUTERR1,P CONGODIE BUS Parity Error, go 3365 >>>>>>>>>>>>>>>>>>>>> 3366 ENDVECTOR 3368 FOUTERR1 HALT Bus Parity Error Set on Interrupt for Single Word Fetch 3EE 4FF31C00637903EE13EE 3368$ FOUTERR1 LIT SCR1F * * Bus Parity Error Set 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 85 PPU5/REV 26 microcode File# 0 FIFO Output processor 3370 3EF 50231018735100001E44 3371 FOREAD1W X2,P RAM SBLC LADDR INDX FOSETIN2 setup for Double Word 3373 BLOCK 4,OUTIOR2 3374 >>>>>>>>>>>>>>>>>>>>> E44 48331C1C637A0F6013F0 3375 >FOSETIN2 LIT IADR PRT0IADR FOUTINT FOSBCB1W set output- port 0 E45 C8331C18637A0F6013F0 3376 > LIT IADR PRT1IADR FOUTINT FOSBCB1W E46 C8331C14637A0F6013F0 3377 > LIT IADR PRT2IADR FOUTINT FOSBCB1W E47 48331C10637A0F6013F0 3378 > LIT IADR PRT3IADR FOUTINT FOSBCB1W set output- port 3 3379 >>>>>>>>>>>>>>>>>>>>> 3380 ENDBLOCK 3F0 D8101E146355000413F1 3382 FOSBCB1W X2 LIT XOR RAM SBCB SLOT XORFF1W complete the READ 3F1 48331C08637A0F8013F2 3383 LIT IADR IBFIADR ONEWORD & setup for only 1 wo 3384 3F2 58131D957358FFFC13F4 3385 X2 LIT ADD RAM RAM BCNT -4 SKIP FOEXIT1W decrement BC & check 3386 SKIPORG 3F3 4FF31C00637903F313F3 3386$ WSTE0044 LIT SCR1F * * ****** wasted ****** 3387 >>>>>>>>>>>>>>>>>>>>> 3F4 D8021D9863580001BEF0 3388 >FOEXIT1W I,X2,P LIT ADD RAM RAM LADDR 1 POP DIDNTPOP not end, inc address 3F5 58131F16735F800013FD 3389 > X2 LIT AND RAM LAST LASTBIT SKIP FONLAST end, last BC? 3390 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 86 PPU5/REV 26 microcode File# 0 FIFO Output processor 3392 3393 ***************************************************************************************************** 3394 * * 3395 * FIFO output interrupt processor - Double Word Fetch. * 3396 * * 3397 ***************************************************************************************************** 3399 VECTOR 3400 >>>>>>>>>>>>>>>>>>>>> F60 50213C176350000013F7 3401 >FOUTINT X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start RE F61 50213C176350000013F7 3402 > X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start RE F62 50213C176350000013F7 3403 > X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start RE F63 50213C176350000013F7 3404 > X2,C,P RAM SBHC HADDR FOREAD RTO cleared, start RE F64 D8321C00633F0000BEF0 3405 > IP POP DIDNTPOP RTO set, wait for it F65 D8321C00633F0000BEF0 3406 > IP POP DIDNTPOP RTO set, wait for it F66 D8321C00633F0000BEF0 3407 > IP POP DIDNTPOP RTO set, wait for it F67 D8321C00633F0000BEF0 3408 > IP POP DIDNTPOP RTO set, wait for it F68 58331C00653903F65309 3409 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F69 58331C00653903F65309 3410 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F6A 58331C00653903F65309 3411 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F6B 58331C00653903F65309 3412 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F6C 58331C00653903F65309 3413 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F6D 58331C00653903F65309 3414 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F6E 58331C00653903F65309 3415 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go F6F 58331C00653903F65309 3416 > SBST SCR0 FOUTERR2,P CONGODIE BUS Parity Error, go 3417 >>>>>>>>>>>>>>>>>>>>> 3418 ENDVECTOR 3420 FOUTERR2 HALT Bus Parity Error Set on Interrupt for Double Word Fetch 3F6 4FF31C00637903F613F6 3420$ FOUTERR2 LIT SCR1F * * Bus Parity Error Set 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 87 PPU5/REV 26 microcode File# 0 FIFO Output processor 3F7 50311C146355000013F8 3422 FOREAD X2 RAM SBCB SLOT complete the READ 3F8 D0211C186351000013F9 3423 X2,P RAM SBLC LADDR 3F9 58131D957358FFF813FA 3424 X2 LIT ADD RAM RAM BCNT -8 SKIP FOEXIT decrement BC & check 3425 SKIPORG 3426 >>>>>>>>>>>>>>>>>>>>> 3FA 58023D9863580002BEF0 3427 >FOEXIT I,X2,P,C LIT ADD RAM RAM LADDR 2 POP DIDNTPOP incr address & exit 3FB 58131F16735F800013FD 3428 > X2 LIT AND RAM LAST LASTBIT SKIP FONLAST last BC ? 3429 >>>>>>>>>>>>>>>>>>>>> 3430 >>>>>>>>>>>>>>>>>>>>> 3FC D8131E96735FFFFC1412 3431 > X2 LIT IOR RAM LAST #FFFC SKIP FOODDBC yes, odd byte count? 3FD D8131F16735F000813FF 3432 >FONLAST X2 LIT AND RAM LAST 8 SKIP FOODDWRD no, odd word? 3433 >>>>>>>>>>>>>>>>>>>>> 3434 3435 ***************************************************************************************************** 3436 * We get to FONOVRN if end of this BCNT (of double words) * 3437 * AND NOT last byte count. The lines from FONOVRN to the line * 3438 * just preceeding FONEXTBC have the effect of choosing whether * 3439 * we will be reading one or two words from memory. (We already * 3440 * sent a double word read to the memory.) * 3441 ***************************************************************************************************** 3442 3443 >>>>>>>>>>>>>>>>>>>>> 3FE 58033D98635800021401 3444 > X2,C,P LIT ADD RAM RAM LADDR 2 FONEXTBC no, adjust the memory 3FF 58031D98635800011400 3445 >FOODDWRD X2,P LIT ADD RAM RAM LADDR 1 yes, adjust the memor 3446 >>>>>>>>>>>>>>>>>>>>> 400 C8331C08637A0F801401 3447 LIT IADR IBFIADR ONEWORD & setup for only 1 wo 401 58131E92735F00001403 3448 FONEXTBC X2 LIT IOR RAM BCOVERUN 0 SKIP FONOVRN overrun? 3449 3450 SKIPORG 3451 >>>>>>>>>>>>>>>>>>>>> 402 5A130E8362D90000139C 3452 > X2 SCR8 IOR RAM SCR8 PBITIM FIORUN yes, not ready, ints 403 58131E85635800101404 3453 >FONOVRN X2 LIT IOR RAM RAM PRTST BCROLL signal BC rollover 3454 >>>>>>>>>>>>>>>>>>>>> 404 D8131C12637800001405 3455 X2 ZERO RAM BCOVERUN set overrun detector 405 53331C1A635900001406 3456 X2 RAM SCRC BCNT2 and move the rest of 406 4B330C1562F800001407 3457 X2 SCRC RAM BCNT the parameters over 407 4B330C0762F800001408 3458 X2 SCRC RAM CLKFIX set for clock adjuster 408 53331C1C635900001409 3459 X2 RAM SCRC HADDR2 409 CB230C1762F80000140A 3460 X2,P SCRC RAM HADDR 40A D3331C1963590000140B 3461 X2 RAM SCRC SLOT2 40B 4B330C1462F80000140C 3462 X2 SCRC RAM SLOT 40C 53331C1B63590000140D 3463 X2 RAM SCRC LAST2 40D 4B330C1662F80000140E 3464 X2 SCRC RAM LAST 40E D3331C1D63590000140F 3465 X2 RAM SCRC LADDR2 40F 58131F1D735F00011410 3466 X2 LIT AND RAM LADDR2 1 SKIP FONOT1W need to do a single f 3467 SKIPORG 3468 >>>>>>>>>>>>>>>>>>>>> 410 4B220C1862F80000BEF0 3469 >FONOT1W I,X2,P SCRC RAM LADDR POP DIDNTPOP no, exit 411 CB23001872F800001E40 3470 > X2,P SCRC RAM LADDR INDX FOSI1WIP yes, set vector & exit 3471 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 88 PPU5/REV 26 microcode File# 0 FIFO Output processor 3473 SKIPORG 3474 >>>>>>>>>>>>>>>>>>>>> 412 48331C08637A0F90141C 3475 >FOODDBC LIT IADR IBFIADR ODDWORD FOODDBC1 yes, setup for it & e 413 58131F16735F00081414 3476 > X2 LIT AND RAM LAST 8 SKIP no, double Fetch? 3477 >>>>>>>>>>>>>>>>>>>>> 3478 >>>>>>>>>>>>>>>>>>>>> 414 D8031D98635800011416 3479 > X2,P LIT ADD RAM RAM LADDR 1 *+2 no, correct memory a 415 58031D98635800021417 3480 > X2,P LIT ADD RAM RAM LADDR 2 *+2 yes, correct memory a 3481 >>>>>>>>>>>>>>>>>>>>> 3482 >>>>>>>>>>>>>>>>>>>>> 416 48331C08637A0F801417 3483 > LIT IADR IBFIADR ONEWORD setup for 1 word 417 58131E85635800B21418 3484 >FOLASTBC X2 LIT IOR RAM RAM PRTST LASTBC signal end and 3485 >>>>>>>>>>>>>>>>>>>>> 418 5A130E8362D900001419 3486 X2 SCR8 IOR RAM SCR8 PBITIM disallow interrupts 419 CA310C0062F70000141A 3487 SCR8 IMR 41A 58131C1563780000141B 3488 X2 ZERO RAM BCNT zero the byte count 41B 48321C1663788000BEF0 3489 I,X2 LIT RAM LAST LASTBIT POP DIDNTPOP exit, clear last bcnt 3490 41C 53331C16635900001417 3491 FOODDBC1 X2 RAM SCRC LAST FOLASTBC save this for IBF int 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 89 PPU5/REV 26 microcode File# 0 FIFO Output processor 3493 3494 ***************************************************************************************************** 3495 * * 3496 * Here if fetching two words (double word fetch) * 3497 * * 3498 ***************************************************************************************************** 3500 VECTOR 3501 >>>>>>>>>>>>>>>>>>>>> F70 58131E85635801001F71 3502 >TWOWORDS X2 LIT IOR RAM RAM PRTST MPECODE BPE*, RTO* but Abnorm F71 D8311C0065EB0000141E 3503 > X2 SBHC DPOUT TWOWRDS1 BPE*, RTO* and Normal F72 D8331C006539041D5306 3504 > SBST SCR0 MEM1ERR,P BFGODIE BPE*, RTO* but Comman F73 D8331C006539041D5306 3505 > SBST SCR0 MEM1ERR,P BFGODIE BPE*, RTO* but Illega F74 D8331C006539041D5309 3506 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go F75 D8331C006539041D5309 3507 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go F76 D8331C006539041D5309 3508 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go F77 D8331C006539041D5309 3509 > SBST SCR0 MEM1ERR,P CONGODIE BPE* but RTO! go F78 D8331C006539041D5305 3510 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F79 D8331C006539041D5305 3511 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F7A D8331C006539041D5305 3512 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F7B D8331C006539041D5305 3513 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F7C D8331C006539041D5305 3514 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F7D D8331C006539041D5305 3515 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F7E D8331C006539041D5305 3516 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go F7F D8331C006539041D5305 3517 > SBST SCR0 MEM1ERR,P PEGODIE BUS Parity Error, go 3518 >>>>>>>>>>>>>>>>>>>>> 3519 ENDVECTOR 3521 MEM1ERR HALT Bad Flags, Bus Parity Error, or RTO Set on Double Word IBF Interrupt 41D 4FF31C006379041D141D 3521$ MEM1ERR LIT SCR1F * * Bad Flags, Bus Parity 41E D8311C00666B0000141F 3523 TWOWRDS1 X2 SBLC DPOUT 41F 58311C0066EB00001420 3524 X2 SBHD DPOUT 420 D8321C00676B0000BEF0 3525 IP,X2 SBLD DPOUT POP DIDNTPOP & exit 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 90 PPU5/REV 26 microcode File# 0 FIFO Output processor 3527 3528 ***************************************************************************************************** 3529 * * 3530 * Here if only fetching one word * 3531 * * 3532 ***************************************************************************************************** 3534 VECTOR 3535 >>>>>>>>>>>>>>>>>>>>> F80 DC731C00653900001423 3536 >ONEWORD SBST SCR11 ONEWORDCKPE BPE*, RTO* but Abn F81 58311C0065EB00001426 3537 > X2 SBHC DPOUT ONEWORD1 BPE*, RTO* and Normal F82 D8331C00653904215306 3538 > SBST SCR0 MEM2ERR,P BFGODIE BPE*, RTO* but Comman F83 D8331C00653904215306 3539 > SBST SCR0 MEM2ERR,P BFGODIE BPE*, RTO* but Illega F84 D8331C00653904215309 3540 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go F85 D8331C00653904215309 3541 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go F86 D8331C00653904215309 3542 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go F87 D8331C00653904215309 3543 > SBST SCR0 MEM2ERR,P CONGODIE BPE* but RTO! go F88 D8331C00653904215305 3544 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F89 D8331C00653904215305 3545 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F8A D8331C00653904215305 3546 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F8B D8331C00653904215305 3547 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F8C D8331C00653904215305 3548 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F8D D8331C00653904215305 3549 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F8E D8331C00653904215305 3550 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go F8F D8331C00653904215305 3551 > SBST SCR0 MEM2ERR,P PEGODIE BUS Parity Error, go 3552 >>>>>>>>>>>>>>>>>>>>> 3553 ENDVECTOR 3555 MEM2ERR HALT Bad Flags, Bus Parity Error, or RTO Set on Single Word IBF Interrupt 421 4FF31C00637904211421 3555$ MEM2ERR LIT SCR1F * * Bad Flags, Bus Parity 3557 STARTSKP 422 4FF31C00637904221422 3557$ WSTE0045 LIT SCR1F * * ****** wasted ****** 423 DC530F0072FF10001424 3558 ONEWORDCKPE SCR11 AND LIT WORD1DATA SKIP ONEWORDPE abnormal data flags 3559 >>>>>>>>>>>>>>>>>>>>> 424 58131E85635801001425 3560 >ONEWORDPE X2 LIT IOR RAM RAM PRTST MPECODE word 1 is abnormal da 425 58311C0065EB00001426 3561 > X2 SBHC DPOUT word is normal data 3562 >>>>>>>>>>>>>>>>>>>>> 426 58311C00666B00001427 3563 ONEWORD1 X2 SBLC DPOUT finish outputting 427 C8321C08637A0F70BEF0 3564 I LIT IADR IBFIADR TWOWORDS POP DIDNTPOP reset the vector & ex 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 91 PPU5/REV 26 microcode File# 0 FIFO Output processor 3566 3567 ***************************************************************************************************** 3568 * * 3569 * Here if fetching an odd number of bytes * 3570 * * 3571 ***************************************************************************************************** 3573 VECTOR 3574 >>>>>>>>>>>>>>>>>>>>> F90 DB130D8062F9FFFB1429 3575 >ODDWORD X2 SCRC ADD LIT SCRC -5 OWCKIFONE BPE*, RTO* and Abnor F91 DB130F0072FF00041430 3576 >ODDWORDOK X2 SCRC AND LIT 4 SKIP OWISONE BPE*, RTO* and Normal F92 D8331C00653904285306 3577 > SBST SCR0 MEM3ERR,P BFGODIE BPE*, RTO* but Comman F93 D8331C00653904285306 3578 > SBST SCR0 MEM3ERR,P BFGODIE BPE*, RTO* but Illega F94 D8331C00653904285309 3579 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go F95 D8331C00653904285309 3580 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go F96 D8331C00653904285309 3581 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go F97 D8331C00653904285309 3582 > SBST SCR0 MEM3ERR,P CONGODIE BPE* but RTO! go F98 D8331C00653904285305 3583 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F99 D8331C00653904285305 3584 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F9A D8331C00653904285305 3585 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F9B D8331C00653904285305 3586 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F9C D8331C00653904285305 3587 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F9D D8331C00653904285305 3588 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F9E D8331C00653904285305 3589 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go F9F D8331C00653904285305 3590 > SBST SCR0 MEM3ERR,P PEGODIE BUS Parity Error, go 3591 >>>>>>>>>>>>>>>>>>>>> 3592 ENDVECTOR 3594 MEM3ERR HALT Bad Flags, Bus Parity Error, or RTO Set on Odd Bytes IBF Interrupt 428 4FF31C00637904281428 3594$ MEM3ERR LIT SCR1F * * Bad Flags, Bus Parity 3596 STARTSKP 429 DB130F0072FF8000142B 3597 OWCKIFONE X2 SCRC AND LIT #8000 SKIP OWPENOTONE check if 1 or 2 wor 3598 >>>>>>>>>>>>>>>>>>>>> 42A 5C731C0065390000142D 3599 > SBST SCR11 ODDWORDCKPE 1 word used,get fl 42B 58131E8563580100142C 3600 >OWPENOTONE X2 LIT IOR RAM RAM PRTST MPECODE 2 words used,set pari 3601 >>>>>>>>>>>>>>>>>>>>> 42C 5B130D8062F900051431 3602 X2 SCRC ADD LIT SCRC 5 OWNOTONE correct SCRC, finish 3603 3604 STARTSKP 42D DC530F0072FF1000142E 3605 ODDWORDCKPE SCR11 AND LIT WORD1DATA SKIP ODDWORDPE abnormal data flags 3606 >>>>>>>>>>>>>>>>>>>>> 42E 58131E8563580100142F 3607 >ODDWORDPE X2 LIT IOR RAM RAM PRTST MPECODE word 1 is abnormal da 42F DB130D8062F900051F91 3608 > X2 SCRC ADD LIT SCRC 5 ODDWORDOK no PE on word 1,fini 3609 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 92 PPU5/REV 26 microcode File# 0 FIFO Output processor 3611 SKIPORG 3612 >>>>>>>>>>>>>>>>>>>>> 430 DB130E9662F9000C1438 3613 >OWISONE X2 SCRC IOR LIT SCRC LAST OW1BCIOR OWISONE1 less than 1 word, pro 431 58311C0065EB00001432 3614 >OWNOTONE X2 SBHC DPOUT more than 1, save the 3615 >>>>>>>>>>>>>>>>>>>>> 432 58311C00666B00001433 3616 X2 SBLC DPOUT 433 5B130D8062F9FFFC1434 3617 X2 SCRC ADD LIT SCRC -4 reflect it in the cou 434 58031D98635800021435 3618 X2,P LIT ADD RAM RAM LADDR 2 make sure the address 435 5B130E8062F900081436 3619 X2 SCRC IOR LIT SCRC OW2BCIOR process the 2nd word 436 CB33080072FF00001E48 3620 SCRC DB0 OWIS2BC 3621 BLOCK 4,OW2BCIOR 3622 >>>>>>>>>>>>>>>>>>>>> 3623 >OWIS2BC HALT should never get here E48 4FF31C0063790E481E48 3623$>OWIS2BC LIT SCR1F * * should never get here E49 D8311C0046EB0000143B 3624 > X2 SBHD DPOUT,H OWEXIT move 1 byte E4A 58311C0066EB0000143B 3625 > X2 SBHD DPOUT OWEXIT move 2 bytes E4B 58311C0066EB00001437 3626 > X2 SBHD DPOUT OWIS2BC1 move 3 bytes 3627 >>>>>>>>>>>>>>>>>>>>> 3628 ENDBLOCK 437 D8311C00476B0000143B 3630 OWIS2BC1 X2 SBLD DPOUT,H OWEXIT 438 58031D98635800011439 3632 OWISONE1 X2,P LIT ADD RAM RAM LADDR 1 make sure the address 439 4B33080072FF00001E4C 3633 SCRC DB0 OWIS1BC 3635 BLOCK 4,OW1BCIOR 3636 >>>>>>>>>>>>>>>>>>>>> 3637 >OWIS1BC HALT should never get here E4C 4FF31C0063790E4C1E4C 3637$>OWIS1BC LIT SCR1F * * should never get here E4D D8311C0045EB0000143B 3638 > X2 SBHC DPOUT,H OWEXIT move 1 byte E4E 58311C0065EB0000143B 3639 > X2 SBHC DPOUT OWEXIT move 2 bytes E4F D8311C0065EB0000143A 3640 > X2 SBHC DPOUT OWIS1BC1 move 3 bytes 3641 >>>>>>>>>>>>>>>>>>>>> 3642 ENDBLOCK 43A 58311C00466B0000143B 3644 OWIS1BC1 X2 SBLC DPOUT,H OWEXIT 43B C8321C08637A0F70BEF0 3646 OWEXIT I LIT IADR IBFIADR TWOWORDS POP DIDNTPOP reset the vector & ex 3647 TITLE.MAC Diagnostic Section 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 93 PPU5/REV 26 microcode File# 0 Diagnostic Section 3648 ***************************************************************************************************** 3649 * * 3650 * PPU self-test diagnostics * 3651 * * 3652 ***************************************************************************************************** 3653 3654 ***************************************************************************************************** 3655 * End of test stuff * 3656 ***************************************************************************************************** 3657 43C 58331C00633B0000143D 3658 ENDTEST T4 SBRST clear the BUS interfa 43D D9931C0063790000143E 3659 ZERO SCR6 clear PPU Internal St 43E DFD31C0063790000143F 3660 ZERO SCR1F clear last halt addre 3661 * since value in SCR1F is not va 3662 43F CA731C00637900F01440 3663 LIT SCR9 #F0 indicate controllers 440 CA710C0062F200001441 3664 SCR9 DPOE ensure controllers en 3665 441 48331C00637900031442 3666 LIT SCR0 3 clear WRU responses, 442 C8310C0062F300001445 3667 SCR0 INDX1 WRULOOP1 touch the Self-test r 3668 443 78131C2B637800001444 3669 WRULOOPA X1 ZERO RAM WRURES4B 444 78131C2A637800001445 3670 X1 ZERO RAM WRURES4A 445 78131C29637800001446 3671 WRULOOP1 X1 ZERO RAM WRURES3B 446 78131C28637800001447 3672 X1 ZERO RAM WRURES3A 447 78131C27637800001448 3673 X1 ZERO RAM WRURES2B 448 78131C26637800001449 3674 X1 ZERO RAM WRURES2A 449 78131C2563780000144A 3675 X1 ZERO RAM WRURES1B 44A 78131C2463780000144B 3676 X1 ZERO RAM WRURES1A check for end of loop 44B D8130D8072F9FFFF144C 3677 SCR0 ADD LIT SCR0 #FFFF SKIP WRULOOP not yet, continue 3678 SKIPORG 3679 >>>>>>>>>>>>>>>>>>>>> 44C C8310C0062F300001443 3680 >WRULOOP SCR0 INDX1 WRULOOPA back to the fray 44D D8311C00633F00001013 3681 > RESTART SELF-TEST complete, r 3682 >>>>>>>>>>>>>>>>>>>>> 3683 44E 48311C006377FFFF144E 3684 LIT IMR -1 * just a useful instruc 044E 3686 MAXPCLOW EQU *-1 maximum PC in low RAM (0-7FF) 0450 3687 SELFTESTSTART EQU #450 3689 IF MAXPCLOW GE SELFTESTSTART, we've run out of code space 3691 ***************************************************************************************************** 3692 * All of the microcode that follows this point is in the last half * 3693 * of the prom space. * 3694 ***************************************************************************************************** 3696 EXPAND ON 3697 RESET TITLESTRING,PPU/REV 26 microcode *** second half of prom *** 3698 EXPAND OFF 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 94 PPU5/REV 26 microcode File# 0 Diagnostic Section 3700 TITLE.MAC SELFTEST Definitions 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 95 PPU/REV 26 microcode *** second half of prom *** File# 0 SELFTEST Definitions 3701 * slot configuration and 64 bit floating 1-RFI/floating zero-RFR 3702 0010 3703 PINTCK EQU #10 RAM 10 = expected port interrupt # 0014 3704 VECTCK EQU #14 RAM 14 = vector interrupt address check 0018 3705 WDCNT EQU #18 RAM 18,19,1A,1B=P0,P1,P2,P3 # words written 001C 3706 PTFULL EQU #1C RAM 1C = 33 = all 4 output FIFOs should be full 0020 3707 ID EQU #20 RAM 20 = expected N, PB, TO, and FROM in 0040 3708 HW1 EQU #40 RAM 40 = high word 1 (OUT) 0044 3709 LW1 EQU #44 RAM 44 = low word 1 (OUT) 0060 3710 HW2 EQU #60 RAM 60 = high word 2 (OUT) 0070 3711 LW2 EQU #70 RAM 70 = low word 2 (OUT) 0050 3712 TCON EQU #50 RAM 50 = test control counter 0080 3713 EXSTAT EQU #80 RAM 80 = expected completion superbus status 0090 3714 EXSTAT2 EQU #90 RAM 90 = expected completion SBFT status 00A0 3715 BUSBITS EQU #A0 RAM A0 = superbus control bits 00B0 3716 TESTTEMP EQU #B0 RAM B0 = temporary usage by selftest 00AC 3717 ERRFLAG EQU WRURES4B RAM WRURES4B+3 = selftest flag = 0 = no errors, + = error code 3718 0450 3719 ORG SELFTESTSTART 3720 3721 INCLUDE UCODE.HRDPP5:SELFTEST.REV26 1 TITLE.MAC PPU5 SELFTEST Revisions Log 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 96 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Revisions Log 2 3 ***************************************************************************************************** 4 * * 5 * LOG OF CHANGES * 6 * * 7 * * 8 * Revision 13 Mar, 1985 * 9 * -------- -- ---- ---- * 10 * * 11 * Initial release of PPU5 ucode. * 12 * Totally new PPU5 selftest developed by Bill Oliver in January 1985. * 13 * * 14 * * 15 * Revision 14 Mar, 1986 ECN 1627 * 16 * -------- -- ---- ---- --- ---- * 17 * * 18 * Modified by Bill Oliver in August 1985 to keep controllers * 19 * in reset until the entire selftest is complete. This is to keep * 20 * other boards (most notably wirewrap PPUs) from causing this PPU's * 21 * controller's PFW line from toggling because the BSE is toggling. If * 22 * the controllers are held in reset while this is happening, then they * 23 * should experience no ill effects (like failure to pass their own * 24 * selftest). * 25 * * 26 * Modified by Bill Oliver in November 1985 to make the * 27 * selftest take more time than wire wrap PPU's selftest. This is to * 28 * keep wire wrap PPUs from causing the controller's PFW line to toggle * 29 * before reset is released. This was done by lengthening the * 30 * interrupt test. The selftest now takes about one and a quarter * 31 * seconds to complete. * 32 * * 33 * * 34 * Revision 16 Dec, 1986 ECN 1644 * 35 * -------- -- ---- ---- --- ---- * 36 * * 37 * No change. * 38 * * 39 * Revision 18 Feb, 1990 ECN 1716 * 40 * -------- -- ---- ---- --- ---- * 41 * * 42 * Modified by Ron Crandall to release the controllers after * 43 * 1 second. This is after any BSE activation caused by another bus * 44 * device. The PPU3 microcode has been modified to activate Bus * 45 * Error for only a short time at the beginning of its selftest, * 46 * so the problem of Bus Error disturbing controllers selftest * 47 * should not happen any longer (assuming that a PPU5 is not run * 48 * in a system with an old PPU3). This change is needed to give * 49 * the Video Tape controller time to complete its selftest before * 50 * the system starts running during a boot. * 51 * * 52 * Revision 26 Jul, 1991 ECN 1725 * 53 * -------- -- ---- ---- --- ---- * 54 * * 55 * No change. Revision levels now in decimal in documentation. * 56 * * 57 ***************************************************************************************************** 58 TITLE.MAC PPU5 SELFTEST Description 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 97 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Description 59 60 ***************************************************************************************************** 61 * * 62 * PPU5 Selftest * 63 * * 64 * The error code that this routine returns in SCR0 or WRU 15 is * 65 * the microcode address of the place where it failed. * 66 * * 67 * This selftest attempts to test everything in the PPU that is * 68 * needed for correct operation. This test has a few weaknesses which * 69 * I will try to discuss. First of all, this selftest is just plain * 70 * big. It takes up over half the PROM space as it is constructed now. * 71 * If more space is needed for regular microcode, parts of the selftest * 72 * may be reduced. In particular, the number of "BUSMACROS" macros may * 73 * be reduced, some things could be rearranged to more efficiently use * 74 * space, the "SKIPORG" and "STARTSKIP" macros could be used instead of * 75 * "ODD" and "EVEN" to reuse lost space, and the RAM and SCRATCH PAD * 76 * tests might be reduced in size somehow. The second weakness that * 77 * this test has is rooted as much in the hardware as anywhere else. * 78 * There are no hardware hooks available to test out the logic going to * 79 * and from the ports on either the DATA PATH or the COMMAND/STATUS * 80 * PATH. This selftest does do some simple port status checks, but it * 81 * could do a lot more port status checks than it does. * 82 * * 83 * If changes are needed to this selftest, I expect them to fall * 84 * mainly in the categories of reducing the PROM space required by the * 85 * selftest and better testing of the port logic. * 86 * * 87 * * 88 * This selftest holds the controllers hooked up to the ports * 89 * in reset until after it is done with the majority of the * 90 * selftest. This is because the VRA BUS's bus error signal gets * 91 * OR'ed into the PFW- signal that is fed to the controllers. If * 92 * the controllers are not held in reset while this is happening, * 93 * they may not pass their selftest. The particular case I am * 94 * thinking of is the BFDC which may or may not pass its selftest * 95 * if PFW- toggles back and forth after RESET- is released. The * 96 * CTC also seems to have this same problem. One board in * 97 * particular that may cause BSE to toggle a lot causing the * 98 * controllers PFW to toggle is another PPU. In particular, older * 99 * versions of the selftest (only in wire wrap PPUs) cause BSE to * 100 * toggle for quite a long time after selftest is started. * 101 * * 102 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 98 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Description 104 ***************************************************************************************************** 105 * First we initialize RADR and the 4 RBIR'S to zero. * 106 ***************************************************************************************************** 107 450 C8311C00637200001451 108 SELFTEST LIT DPOE 0000 hold controllers in r 451 C8311C00637400001452 109 LIT RADR 0 init RADR<-0 452 C8311C00636D00001453 110 LIT INDX2 0 point to port 0 453 C8331C00637C00001454 111 LIT RBIR 0 init RBIR0<-0 454 48311C00636D00011455 112 LIT INDX2 1 point to port 1 455 48331C00637C00001456 113 LIT RBIR 0 init RBIR1<-0 456 C8311C00636D00021457 114 LIT INDX2 2 point to port 2 457 C8331C00637C00001458 115 LIT RBIR 0 init RBIR2<-0 458 C8311C00636D00031459 116 LIT INDX2 3 point to port 3 459 48331C00637C0000145A 117 LIT RBIR 0 TESTERRFLAG initialize RBIR3<-0 118 119 ***************************************************************************************************** 120 * Next we test SCR0 and RAM location ERRFLAG. * 121 ***************************************************************************************************** 122 123 EVEN 45A 58331C00633B0000145B 124 TESTERRFLAG T4 SBRST 45B C8311C0063730003145C 125 LIT INDX1 #0003 X1 = 3 45C D8101C0063750000145D 126 ZERO SBCB 45D 48311C00636D0003145E 127 LIT INDX2 #0003 X2 = 3 45E 58131C0063790000145F 128 ZERO SCR0 SCR0<-0 45F 58130E8072FF00001460 129 SCR0 IOR LIT 0 SKIP SCR0=0? 460 D8311C00633F00001460 130 * no, stop can't do ERR 461 58311C00633F00001462 131 NOP yes 462 D8131F80637900001463 132 ONES SCR0 SCR0<-FFFF 463 D8130F0072FFFFFF1464 133 SCR0 AND LIT #FFFF SKIP SCR0=FFFF? 464 58311C00633F00001464 134 * no, stop can't do ERR 465 D8311C00633F00001466 135 NOP yes, next test 466 E8331C2B637800001467 136 X1 LIT RAM ERRFLAG #0000 set error location 467 F8131E2B735300001468 137 X1 LIT XOR RAM INDX1 ERRFLAG #0000 SKIP is it 0? (X1 = 0) 468 48331C00637904681C54 138 LIT SCR0 * ERRTN 469 48331C2B6378FFFF146B 139 X2 LIT RAM ERRFLAG #FFFF SKIPTEST assume error, until c 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 99 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Description 141 142 ***************************************************************************************************** 143 * This first test is a test of the basic skip logic. It also * 144 * uses the ONES and ZEROS opcodes of the ALU and checks them. * 145 ***************************************************************************************************** 146 147 ODD 46A 4FF31C006379046A146A 147$ WSTE0046 LIT SCR1F * * ****** wasted ****** 46B 58131F80737FFFFF146C 148 SKIPTEST ONES #FFFF SKIP skip (true) test 46C C8331C006379046C1C54 149 LIT SCR0 * ERRTN bad skip 46D 58131C00737F0000146E 150 ZERO 0000 SKIP skip (true) test 46E 48331C006379046E1C54 151 LIT SCR0 * ERRTN bad skip 46F D8131F80737F00001470 152 ONES 0000 SKIP skip (false) test 470 58131C00737FFFFF1473 153 ZERO #FFFF SKIP *+3 skip (false) test 471 C8331C00637904711C54 154 LIT SCR0 * ERRTN bad skip 472 C8331C00637904721C54 155 LIT SCR0 * ERRTN bad skip 473 58131F80737FFFFF1474 156 ONES #FFFF SKIP skip (true) test 474 C8331C00637904741C54 157 LIT SCR0 * ERRTN bad skip 475 58131C00737F00001476 158 ZERO 0000 SKIP skip (true) test 476 48331C00637904761C54 159 LIT SCR0 * ERRTN bad skip 477 58131F80737F00001478 160 ONES 0000 SKIP skip (false) test 478 D8131C00737FFFFF147B 161 ZERO #FFFF SKIP *+3 skip (false) test 479 48331C00637904791C54 162 LIT SCR0 * ERRTN bad skip 47A 48331C006379047A1C54 163 LIT SCR0 * ERRTN bad skip 47B D8311C00633F0000147D 164 NOP PUSHPOPTEST next test 165 166 ***************************************************************************************************** 167 * This is a simple PUSH and POP test. It simply pushes 4 * 168 * addresses and does 4 pops. * 169 ***************************************************************************************************** 170 171 ODD 47C 4FF31C006379047C147C 171$ WSTE0047 LIT SCR1F * * ****** wasted ****** 47D D8131C0063790489547E 172 PUSHPOPTEST ZERO SCR0 POP4,P 47E D8301C00633F0487547F 173 POP3,P 47F 58301C00633F04855480 174 POP2,P 480 D8301C00633F04835481 175 POP1,P 481 D8130D8062F900019482 176 SCR0 ADD LIT SCR0 #0001 POP 482 C8331C00637904821C54 177 LIT SCR0 * ERRTN 483 D8130D8062F900019484 178 POP1 SCR0 ADD LIT SCR0 #0001 POP 484 C8331C00637904841C54 179 LIT SCR0 * ERRTN 485 58130D8062F900019486 180 POP2 SCR0 ADD LIT SCR0 #0001 POP 486 48331C00637904861C54 181 LIT SCR0 * ERRTN 487 D8130D8062F900019488 182 POP3 SCR0 ADD LIT SCR0 #0001 POP 488 C8331C00637904881C54 183 LIT SCR0 * ERRTN 489 58130F0072F90004148A 184 POP4 SCR0 AND LIT SCR0 #0004 SKIP did we do 4 pops? 48A 48331C006379048A1C54 185 LIT SCR0 * ERRTN no, error 186 48B 58311C00633F0000148C 187 NOP INTRNLBUSTEST next test 188 TITLE.MAC PPU5 SELFTEST Internal Bus Diagnostics 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 100 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 189 ***************************************************************************************************** 190 * PPU-5 Internal Bus Diagnostics * 191 * * 192 * * 193 * This diagnostic consists of 10 basic tests: * 194 * 1. source 3 ANDED with source 2 * 195 * 2. source 3 IORED with source 2 * 196 * 3. source 3 ANDED with source 2, stored in SCR0, checked using step 1 and 2. * 197 * 4. source 3 ANDED with source 2, stored in RAM address 00, checked as in step 3. * 198 * 5. XOR function using steps 3 and 4 * 199 * 6. source 3 stored in SCR0 via NALU, checked using XOR * 200 * 7. source 3 stored in RAM via NALU, RAM stored in SCR0 via RAM-DEST drivers. * 201 * 8. source 1 stored in SCR0 (XLIT) * 202 * 9. XOR pattern test * 203 *10. simple ADD * 204 * * 205 ***************************************************************************************************** 206 209 210 ***************************************************************************************************** 211 * source 3 'AND' source 2 - ALU * 212 * source 3 'IOR' source 2 * 213 ***************************************************************************************************** 214 215 >>>>>>>>>>>>>>>>>>>>> 216 > MACRO ,,PARAM 217 > NAME LITANDLIT, RESET ALUOPCODE,AND 218 > NAME LITIORLIT, RESET ALUOPCODE,IOR 219 > IF (* BAND 1) EQ 0, NOP 220 > LIST MACROS 221 > LBOX 222 > LIT $ALUOPCODE LIT $PARAM(1) SKIP DO S3 $ALUOPCODE S2 = 223 > LIT SCR0 * ERRTN no 224 > ELBOX 225 > 226 > NOLIST MACROS 227 > EMAC 228 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 101 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 230 ***************************************************************************************************** 231 * Destination bus and SCR0 via ALU * 232 ***************************************************************************************************** 233 234 >>>>>>>>>>>>>>>>>>>>> 235 > MACRO ,,PARAM 236 > NAME SCRANDIORLIT, 237 > IF (* BAND 1) NE 0, NOP 238 > LIST MACROS 239 > LBOX 240 > LIT AND LIT SCR0 $PARAM(1) SCR0 = $PARAM(1) 241 > SCR0 IOR LIT $PARAM(1) SKIP *+2 SCR0 = $PARAM(1)?(IOR) 242 > SCR0 AND LIT $PARAM(1) SKIP *+2 SCR0 = $PARAM(1)?(AND) 243 > LIT SCR0 * ERRTN no, IOR failed 244 > LIT SCR0 * ERRTN no, AND failed 245 > ELBOX 246 > 247 > NOLIST MACROS 248 > EMAC 249 >>>>>>>>>>>>>>>>>>>>> 251 ***************************************************************************************************** 252 * RAM address #00 using IORS and ANDS - result in SCR0 * 253 ***************************************************************************************************** 254 255 >>>>>>>>>>>>>>>>>>>>> 256 > MACRO ,,PARAM 257 > NAME LITANDIORRAM, 258 > IF (* BAND 1) NE 0, NOP 259 > LIST MACROS 260 > LBOX 261 > LIT AND LIT RAM #00 $PARAM(1) (RAM 00) = $PARAM(1) 262 > LIT IOR RAM SCR0 #00 $PARAM(1) SKIP *+2 (RAM 00) = $PARAM(1)? 263 > LIT AND RAM SCR0 #00 $PARAM(1) SKIP *+2 (RAM 00) = $PARAM(1)? 264 > LIT SCR0 * ERRTN no, IOR failed 265 > LIT SCR0 * ERRTN no, AND failed 266 > ELBOX 267 > 268 > NOLIST MACROS 269 > EMAC 270 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 102 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 272 ***************************************************************************************************** 273 * XOR function using SCR0 and RAM 00 * 274 ***************************************************************************************************** 275 276 >>>>>>>>>>>>>>>>>>>>> 277 > MACRO ,,PARAM 278 > NAME SCRXORRAM, 279 > IF (* BAND 1) EQ 0, NOP 280 > LIST MACROS 281 > LBOX 282 > LIT AND LIT RAM #00 $PARAM(1) RAM = $PARAM(1) 283 > LIT AND LIT SCR0 $PARAM(1) SCR0 = $PARAM(1) 284 > SCR0 XOR RAM #00 #0000 SKIP $PARAM(1) XOR $PARAM( 285 > LIT SCR0 * ERRTN no 286 > ELBOX 287 > 288 > NOLIST MACROS 289 > EMAC 290 >>>>>>>>>>>>>>>>>>>>> 292 ***************************************************************************************************** 293 * source 3 bus - NALU - SCR0 * 294 ***************************************************************************************************** 295 296 >>>>>>>>>>>>>>>>>>>>> 297 > MACRO ,,PARAM 298 > NAME SCRXORRAMNALU, 299 > IF (* BAND 1) EQ 0, NOP 300 > LIST MACROS 301 > LBOX 302 > LIT SCR0 $PARAM(1) SCR0 (S3-NALU) = $PAR 303 > LIT AND LIT RAM #00 $PARAM(1) RAM thru ALU = $PARAM 304 > SCR0 XOR RAM #00 #0000 SKIP if SCR0 = RAM, ok 305 > LIT SCR0 * ERRTN bad S3-NALU data 306 > ELBOX 307 > 308 > NOLIST MACROS 309 > EMAC 310 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 103 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 312 ***************************************************************************************************** 313 * RAM to DEST to DEST2 to SCR0 * 314 ***************************************************************************************************** 315 316 >>>>>>>>>>>>>>>>>>>>> 317 > MACRO ,,PARAM 318 > NAME LITRAMSCRXOR, 319 > IF (* BAND 1) EQ 0, NOP 320 > LIST MACROS 321 > LBOX 322 > LIT RAM #00 $PARAM(1) RAM = $PARAM(1) 323 > RAM SCR0 $PARAM(1) SCR0 = $PARAM(1) 324 > SCR0 XOR RAM #00 #0000 SKIP if SCR0 = RAM, path ok 325 > LIT SCR0 * ERRTN bad 326 > ELBOX 327 > 328 > NOLIST MACROS 329 > EMAC 330 >>>>>>>>>>>>>>>>>>>>> 332 ***************************************************************************************************** 333 * source 1 to destination bus * 334 ***************************************************************************************************** 335 336 >>>>>>>>>>>>>>>>>>>>> 337 > MACRO ,,PARAM 338 > NAME XLITSCRRAMXOR, 339 > IF (* BAND 1) EQ 0, NOP 340 > LIST MACROS 341 > LBOX 342 > XLIT SCR0 $PARAM(1) SCR0 = $PARAM(1) via 343 > LIT RAM #00 $PARAM(1) RAM = $PARAM(1) 344 > SCR0 XOR RAM #00 #0000 SKIP S1 ok? 345 > LIT SCR0 * ERRTN bad 346 > ELBOX 347 > 348 > NOLIST MACROS 349 > EMAC 350 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 104 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 352 ***************************************************************************************************** 353 * more XOR patterns * 354 ***************************************************************************************************** 355 356 >>>>>>>>>>>>>>>>>>>>> 357 > MACRO ,,PARAM 358 > NAME LITRAMLITSCRXOR, 359 > IF (* BAND 1) EQ 0, NOP 360 > LIST MACROS 361 > LBOX 362 > LIT RAM #00 $PARAM(1) 363 > LIT SCR0 (#FFFF - $PARAM(1)) S3 = (#FFFF - $PARAM( 364 > SCR0 XOR RAM #00 #FFFF SKIP XOR ok? 365 > LIT SCR0 * ERRTN no 366 > ELBOX 367 > 368 > NOLIST MACROS 369 > EMAC 370 >>>>>>>>>>>>>>>>>>>>> 372 ***************************************************************************************************** 373 * Macro to generate all the above macros for a given value. * 374 ***************************************************************************************************** 375 376 >>>>>>>>>>>>>>>>>>>>> 377 > MACRO ,,PARAM 378 > NAME BUSMACROS 379 > 380 > LITANDLIT $PARAM 381 > LITIORLIT $PARAM 382 > SCRANDIORLIT $PARAM 383 > LITANDIORRAM $PARAM 384 > SCRXORRAM $PARAM 385 > SCRXORRAMNALU $PARAM 386 > LITRAMSCRXOR $PARAM 387 > XLITSCRRAMXOR $PARAM 388 > LITRAMLITSCRXOR $PARAM 389 > 390 > EMAC 391 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 105 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 48C C8311C00636D0000148D 393 INTRNLBUSTEST LIT INDX2 #0000 set INDX2 for next te 394 BUSMACROS #0000 395 BUSMACROS #FFFF 396 BUSMACROS #1111 397 BUSMACROS #2222 398 BUSMACROS #4444 399 BUSMACROS #8888 400 BUSMACROS #EEEE 401 BUSMACROS #DDDD 402 BUSMACROS #BBBB 403 BUSMACROS #7777 404 BUSMACROS #8421 405 BUSMACROS #1284 406 BUSMACROS #EDB7 407 BUSMACROS #7BDE 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 106 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Internal Bus Diagnostics 409 ***************************************************************************************************** 410 * simple ADD * 411 ***************************************************************************************************** 412 413 >>>>>>>>>>>>>>>>>>>>> 414 > MACRO ,,PARAM 415 > NAME SCRADDRAM, 416 > IF (* BAND 1) EQ 0, NOP 417 > LIST MACROS 418 > LBOX 419 > LIT SCR0 $PARAM(1) SCR0 should be $PARAM 420 > LIT RAM #00 $PARAM(1) $PARAM(1) in RAM 421 > SCR0 ADD RAM SCR0 #00 (($PARAM(1) + $PARAM(1)) BAND #FFFF) SKIP ok? 422 > LIT SCR0 * ERRTN bad ADD 423 > ELBOX 424 > 425 > NOLIST MACROS 426 > EMAC 427 >>>>>>>>>>>>>>>>>>>>> 428 429 430 SCRADDRAM #0001 431 SCRADDRAM #0002 432 SCRADDRAM #0004 433 SCRADDRAM #0008 434 SCRADDRAM #0010 435 SCRADDRAM #0020 436 SCRADDRAM #0040 437 SCRADDRAM #0080 438 SCRADDRAM #0100 439 SCRADDRAM #0200 440 SCRADDRAM #0400 441 SCRADDRAM #0800 442 SCRADDRAM #1000 443 SCRADDRAM #2000 444 SCRADDRAM #4000 445 SCRADDRAM #8000 446 449 TITLE.MAC PPU5 SELFTEST INDX,DB0,DB4 Branching Tests 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 107 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST INDX,DB0,DB4 Branching Tests 450 ***************************************************************************************************** 451 * Index register tests. The opposite index register is set to a * 452 * different value to provide a little interaction. * 453 * INDX1 first. * 454 ***************************************************************************************************** 455 6C5 D8131C006379000016C6 456 INDXTEST ZERO SCR0 assume no error 6C6 C8311C006373000016C7 457 LIT INDX1 0 X1<-0 6C7 C8311C00636D000316C8 458 LIT INDX2 3 X2<-3 6C8 F8331000733F06C95E30 459 X1 INDXTSTB,P INDX INDXBLK0 do INDX branch 460 461 ODD 6C9 D8130E8072FF000016CA 462 INDXTSTB SCR0 IOR LIT 0 SKIP error? 6CA D8311C00633F00001C54 463 ERRTN yes, error 464 6CB C8311C006373000116CC 465 LIT INDX1 1 X1<-1 6CC 48311C00636D000216CD 466 LIT INDX2 2 X2<-2 6CD 78331000733F06CF5E34 467 X1 INDXTSTD,P INDX INDXBLK1 do indx branch 468 469 ODD 6CE 4FF31C00637906CE16CE 469$ WSTE0048 LIT SCR1F * * ****** wasted ****** 6CF 58130E8072FF000016D0 470 INDXTSTD SCR0 IOR LIT 0 SKIP error? 6D0 D8311C00633F00001C54 471 ERRTN yes, error 472 6D1 C8311C006373000216D2 473 LIT INDX1 2 X1<-2 6D2 48311C00636D000116D3 474 LIT INDX2 1 X2<-1 6D3 F8331000733F06D55E38 475 X1 INDXTSTF,P INDX INDXBLK2 do INDX branch 476 477 ODD 6D4 4FF31C00637906D416D4 477$ WSTE0049 LIT SCR1F * * ****** wasted ****** 6D5 58130E8072FF000016D6 478 INDXTSTF SCR0 IOR LIT 0 SKIP error? 6D6 D8311C00633F00001C54 479 ERRTN yes, error 480 6D7 48311C006373000316D8 481 LIT INDX1 3 X1<-3 6D8 C8311C00636D000016D9 482 LIT INDX2 0 X2<-0 6D9 F8331000733F06DB5E3C 483 X1 INDXTSTH,P INDX INDXBLK3 do INDX branch 484 485 ODD 6DA 4FF31C00637906DA16DA 485$ WSTE0050 LIT SCR1F * * ****** wasted ****** 6DB 58130E8072FF000016DC 486 INDXTSTH SCR0 IOR LIT 0 SKIP error? 6DC D8311C00633F00001C54 487 ERRTN yes, error 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 108 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST INDX,DB0,DB4 Branching Tests 489 ***************************************************************************************************** 490 * Now do INDX2, enter with X1 = 3 and X2 = 0 * 491 ***************************************************************************************************** 492 6DD D8331000733F06DF5E30 493 X2 INDXTSTJ,P INDX INDXBLK0 do INDX branch 494 495 ODD 6DE 4FF31C00637906DE16DE 495$ WSTE0051 LIT SCR1F * * ****** wasted ****** 6DF 58130E8072FF000016E0 496 INDXTSTJ SCR0 IOR LIT 0 SKIP error? 6E0 D8311C00633F00001C54 497 ERRTN yes, error 498 6E1 C8311C00636D000116E2 499 LIT INDX2 1 X2<-1 6E2 48311C006373000216E3 500 LIT INDX1 2 X1<-2 6E3 58331000733F06E55E34 501 X2 INDXTSTL,P INDX INDXBLK1 do INDX branch 502 503 ODD 6E4 4FF31C00637906E416E4 503$ WSTE0052 LIT SCR1F * * ****** wasted ****** 6E5 58130E8072FF000016E6 504 INDXTSTL SCR0 IOR LIT 0 SKIP error? 6E6 D8311C00633F00001C54 505 ERRTN yes, error 506 6E7 C8311C00636D000216E8 507 LIT INDX2 2 X2<-2 6E8 48311C006373000116E9 508 LIT INDX1 1 X1<-1 6E9 D8331000733F06EB5E38 509 X2 INDXTSTN,P INDX INDXBLK2 do INDX branch 510 511 ODD 6EA 4FF31C00637906EA16EA 511$ WSTE0053 LIT SCR1F * * ****** wasted ****** 6EB 58130E8072FF000016EC 512 INDXTSTN SCR0 IOR LIT 0 SKIP error? 6EC D8311C00633F00001C54 513 ERRTN yes, error 514 6ED 48311C00636D000316EE 515 LIT INDX2 3 X2<-3 6EE C8311C006373000016EF 516 LIT INDX1 0 X1<-0 6EF D8331000733F06F15E3C 517 X2 INDXTSTP,P INDX INDXBLK3 do INDX branch 518 519 ODD 6F0 4FF31C00637906F016F0 519$ WSTE0054 LIT SCR1F * * ****** wasted ****** 6F1 58130E8072FF000016F2 520 INDXTSTP SCR0 IOR LIT 0 SKIP error? 6F2 D8311C00633F00001C54 521 ERRTN yes, error 522 * LIT INDX1 0 X1<-0 6F3 C8311C00636D000016F4 523 LIT INDX2 0 DB0TEST X2<-0 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 109 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST INDX,DB0,DB4 Branching Tests 525 BLOCK 4,IBLK0IOR 526 >>>>>>>>>>>>>>>>>>>>> E30 58301C00633F00009EF1 527 >INDXBLK0 POP STERR ok E31 48331C0063790E319EF1 528 > LIT SCR0 * POP STERR error E32 48331C0063790E329EF1 529 > LIT SCR0 * POP STERR error E33 C8331C0063790E339EF1 530 > LIT SCR0 * POP STERR error 531 >>>>>>>>>>>>>>>>>>>>> 532 ENDBLOCK 533 534 BLOCK 4,IBLK1IOR 535 >>>>>>>>>>>>>>>>>>>>> E34 48331C0063790E349EF1 536 >INDXBLK1 LIT SCR0 * POP STERR error E35 58301C00633F00009EF1 537 > POP STERR ok E36 C8331C0063790E369EF1 538 > LIT SCR0 * POP STERR error E37 48331C0063790E379EF1 539 > LIT SCR0 * POP STERR error 540 >>>>>>>>>>>>>>>>>>>>> 541 ENDBLOCK 542 543 BLOCK 4,IBLK2IOR 544 >>>>>>>>>>>>>>>>>>>>> E38 48331C0063790E389EF1 545 >INDXBLK2 LIT SCR0 * POP STERR error E39 C8331C0063790E399EF1 546 > LIT SCR0 * POP STERR error E3A 58301C00633F00009EF1 547 > POP STERR ok E3B 48331C0063790E3B9EF1 548 > LIT SCR0 * POP STERR error 549 >>>>>>>>>>>>>>>>>>>>> 550 ENDBLOCK 551 552 BLOCK 4,IBLK3IOR 553 >>>>>>>>>>>>>>>>>>>>> E3C C8331C0063790E3C9EF1 554 >INDXBLK3 LIT SCR0 * POP STERR error E3D 48331C0063790E3D9EF1 555 > LIT SCR0 * POP STERR error E3E 48331C0063790E3E9EF1 556 > LIT SCR0 * POP STERR error E3F 58301C00633F00009EF1 557 > POP STERR ok 558 >>>>>>>>>>>>>>>>>>>>> 559 ENDBLOCK 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 110 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST INDX,DB0,DB4 Branching Tests 561 ***************************************************************************************************** 562 * Now for the DB0 and DB4 tests. * 563 ***************************************************************************************************** 564 565 6F4 C8731C006379000F16F8 566 DB0TEST LIT SCR1 #000F DB0LOOP init. br. addr. = F 567 ODD 6F5 78130E0072DF000016F6 568 DB0LPA X1 SCR0 XOR RAM #00 #0000 SKIP correct branch? 6F6 48331C00637906F61C54 569 LIT SCR0 * ERRTN bad branch addr 570 6F7 D8530D8072F9FFFF16F8 571 SCR1 ADD LIT SCR1 #FFFF SKIP addr=addr-1, done? 6F8 6873080072F806F55E20 572 DB0LOOP X1 SCR1 RAM #00 DB0LPA,P DB0 DB0BLOCK branch via DEST(3-0) 573 * done, test DB4 6F9 C8731C00637900F016FE 574 LIT SCR1 #00F0 DB4LOOP init DB4 br. addr. = 575 ODD 6FA 4FF31C00637906FA16FA 575$ WSTE0055 LIT SCR1F * * ****** wasted ****** 6FB 78130E0072DF000016FC 576 DB4LPA X1 SCR0 XOR RAM #00 #0000 SKIP correct branch? 6FC 48331C00637906FC1C54 577 LIT SCR0 * ERRTN bad branch addr 578 6FD D8530D8072F9FFF016FE 579 SCR1 ADD LIT SCR1 #FFF0 SKIP addr=addr-10, done? 6FE E873040072F806FB5E10 580 DB4LOOP X1 SCR1 RAM #00 DB4LPA,P DB4 DB4BLOCK branch via DEST(7-4) 6FF D0311C00636D00001700 581 LIT INDX2 #0000 XCHG init X2 to 0, next te 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 111 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST INDX,DB0,DB4 Branching Tests 583 BLOCK 16 584 >>>>>>>>>>>>>>>>>>>>> E20 C8331C00637900009E21 585 >DB0BLOCK LIT SCR0 #0000 POP E21 48331C00637900019E22 586 > LIT SCR0 #0001 POP E22 C8331C00637900029E23 587 > LIT SCR0 #0002 POP E23 C8331C00637900039E24 588 > LIT SCR0 #0003 POP E24 C8331C00637900049E25 589 > LIT SCR0 #0004 POP E25 48331C00637900059E26 590 > LIT SCR0 #0005 POP E26 C8331C00637900069E27 591 > LIT SCR0 #0006 POP E27 48331C00637900079E28 592 > LIT SCR0 #0007 POP E28 C8331C00637900089E29 593 > LIT SCR0 #0008 POP E29 48331C00637900099E2A 594 > LIT SCR0 #0009 POP E2A C8331C006379000A9E2B 595 > LIT SCR0 #000A POP E2B C8331C006379000B9E2C 596 > LIT SCR0 #000B POP E2C C8331C006379000C9E2D 597 > LIT SCR0 #000C POP E2D 48331C006379000D9E2E 598 > LIT SCR0 #000D POP E2E C8331C006379000E9E2F 599 > LIT SCR0 #000E POP E2F C8331C006379000F9E30 600 > LIT SCR0 #000F POP 601 >>>>>>>>>>>>>>>>>>>>> 602 ENDBLOCK 604 BLOCK 16 605 >>>>>>>>>>>>>>>>>>>>> E10 C8331C00637900009E11 606 >DB4BLOCK LIT SCR0 #0000 POP E11 48331C00637900109E12 607 > LIT SCR0 #0010 POP E12 C8331C00637900209E13 608 > LIT SCR0 #0020 POP E13 C8331C00637900309E14 609 > LIT SCR0 #0030 POP E14 C8331C00637900409E15 610 > LIT SCR0 #0040 POP E15 48331C00637900509E16 611 > LIT SCR0 #0050 POP E16 C8331C00637900609E17 612 > LIT SCR0 #0060 POP E17 48331C00637900709E18 613 > LIT SCR0 #0070 POP E18 C8331C00637900809E19 614 > LIT SCR0 #0080 POP E19 48331C00637900909E1A 615 > LIT SCR0 #0090 POP E1A C8331C00637900A09E1B 616 > LIT SCR0 #00A0 POP E1B C8331C00637900B09E1C 617 > LIT SCR0 #00B0 POP E1C C8331C00637900C09E1D 618 > LIT SCR0 #00C0 POP E1D 48331C00637900D09E1E 619 > LIT SCR0 #00D0 POP E1E C8331C00637900E09E1F 620 > LIT SCR0 #00E0 POP E1F 48331C00637900F09E20 621 > LIT SCR0 #00F0 POP 622 >>>>>>>>>>>>>>>>>>>>> 623 ENDBLOCK 624 TITLE.MAC PPU5 SELFTEST "EXCHANGE" Function Test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 112 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST "EXCHANGE" Function Test 625 ***************************************************************************************************** 626 * * 627 * The 'EXCHANGE' (,X) option in the ALU field puts * 628 * ALU (15-8) on DEST2 (7-0) and ALU (7-0) on * 629 * DEST2 (15-8). * 630 * This test will see if the exchange is functional * 631 * by swapping the pattern #ABCD, then checking for * 632 * #CDAB. Then we will check the 'B' inputs to the * 633 * exchange MUX with an incrementing pattern. * 634 * * 635 ***************************************************************************************************** 636 637 EVEN 638 700 C8331C006379ABCD1701 639 XCHG LIT SCR0 #ABCD SCR0 = #ABCD 701 48731C006379CDAB1702 640 LIT SCR1 #CDAB expected patt in SCR1 702 D8130F00E2F8FFFF1703 641 X2 SCR0 AND,X LIT RAM #00 #FFFF SCR0=ABCD, RAM=CDAB 703 58530E0072DF00001704 642 X2 SCR1 XOR RAM #00 #0000 SKIP ok? 704 48331C00637907041C54 643 LIT SCR0 * ERRTN no 644 705 C8731C00637900FF1706 645 LIT SCR1 #00FF SCR1=starting pattern 706 C8B31C006379FF00170A 646 LIT SCR2 #FF00 XCHG0 SCR2=known good patte 647 648 EVEN 707 4FF31C00637907071707 648$ WSTE0056 LIT SCR1F * * ****** wasted ****** 708 58930D8062F9FF001709 649 XCHG0A SCR2 ADD LIT SCR2 #FF00 known good -1 (-100) 709 D8530D8072F9FFFF170A 650 SCR1 ADD LIT SCR1 #FFFF SKIP kick test patt-1 70A D8301C00633F0708570C 651 XCHG0 XCHG0A,P XCHGTST call to do xchng 70B D8311C00633F00001712 652 HBLB done, next test 653 654 655 EVEN 70C 48730C0062F80000170D 656 XCHGTST X2 SCR1 RAM #00 pattern to RAM 0 70D D8131F00E359FFFF170E 657 X2 LIT AND,X RAM SCR0 #00 #FFFF switch patt to SCR0 70E C8B30C0062F80000170F 658 X2 SCR2 RAM #00 expected patt to ram 70F 58130E0072DF00001711 659 X2 SCR0 XOR RAM #00 #0000 SKIP *+2 ok? 710 58301C00633F00009EF1 660 POP STERR ok 711 C8331C00637907111C54 661 LIT SCR0 * ERRTN no 662 663 ***************************************************************************************************** 664 * * 665 * Register usage * 666 * * 667 * SCR0 - bad pattern after exchange * 668 * SCR1 - pattern under test B/4 exchange * 669 * SCR2 - expected pattern after exchange * 670 * * 671 ***************************************************************************************************** 672 TITLE.MAC PPU5 SELFTEST High-byte/Low-byte Option Test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 113 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST High-byte/Low-byte Option Test 673 ***************************************************************************************************** 674 * * 675 * The store high byte (,H) or store low byte (,L) options in the * 676 * destination bus field cause either bits (15-8) or (7-0) respectively * 677 * to be stored in the RAM or scratch pads. The register contents not * 678 * being stored remains unchanged. * 679 * * 680 ***************************************************************************************************** 681 682 EVEN 683 712 C8331C006379FF001713 684 HBLB LIT SCR0 #FF00 init. DATA(7-0) = 00 713 C8331C006378FFFF1714 685 HBLB1 LIT RAM #00 #FFFF init. RAM B/4 store 714 48330C0022F800001715 686 SCR0 RAM,L store 7-0 only 715 D8130E0072DF00001716 687 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = FFXX? 716 48331C00637907161C54 688 LIT SCR0 * ERRTN no 717 58130F0072FFFFFF1718 689 SCR0 AND LIT #FFFF SKIP last pattern? 718 D8130D8062F900011713 690 SCR0 ADD LIT SCR0 #0001 HBLB1 loop 691 719 58311C00633F0000171A 692 NOP 71A 48331C00637900FF171B 693 LIT SCR0 #00FF init. DATA(15-8) = 00 71B 48331C006378FFFF171C 694 HBLB2 LIT RAM #00 #FFFF init. RAM B/4 store 71C C8330C0042F80000171D 695 SCR0 RAM,H store 15-8 only 71D 58130E0072DF0000171E 696 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = XXFF? 71E C8331C006379071E1C54 697 LIT SCR0 * ERRTN no 71F D8130F0072FFFFFF1720 698 SCR0 AND LIT #FFFF SKIP last pattern? 720 58130D8062F90100171B 699 SCR0 ADD LIT SCR0 #0100 HBLB2 loop 700 721 D8311C00633F00001722 701 NOP 722 48331C006378FF001723 702 LIT RAM #00 #FF00 init. DATA(7-0) = 00 723 48331C006379FFFF1724 703 HBLB3 LIT SCR0 #FFFF init. SCR0 B/4 store 724 D0331C00235900001725 704 RAM SCR0,L store SCR0(7-0) only 725 D8130E0072DF00001726 705 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = FFXX? 726 48331C00637907261C54 706 LIT SCR0 * ERRTN no 727 58131F00735FFFFF1728 707 X2 LIT AND RAM #00 #FFFF SKIP last pattern? 728 58131D80635800011723 708 X2 LIT ADD RAM RAM #00 #0001 HBLB3 loop on inc pattern 709 729 58311C00633F0000172A 710 NOP 72A C8331C00637800FF172B 711 LIT RAM #00 #00FF init. DATA(15-8) = 00 72B C8331C006379FFFF172C 712 HBLB4 LIT SCR0 #FFFF init. SCR0 B/4 store 72C 50331C0043590000172D 713 RAM SCR0,H store SCR0(15-8) only 72D 58130E0072DF0000172E 714 SCR0 XOR RAM #00 #0000 SKIP SCR0 & RAM = XXFF? 72E C8331C006379072E1C54 715 LIT SCR0 * ERRTN no 72F 58131F00735FFFFF1730 716 X2 LIT AND RAM #00 #FFFF SKIP last pattern? 730 D8131D8063580100172B 717 X2 LIT ADD RAM RAM #00 #0100 HBLB4 loop on inc pattern 731 58311C00633F00001732 718 SCRADDRTST next test 719 TITLE.MAC PPU5 SELFTEST Scratch Pad Register Test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 114 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Scratch Pad Register Test 720 ***************************************************************************************************** 721 * Store the patterns 0000 - 001F in scratch pads 0 - 1F * 722 * read the scratch pads back and verify that the patterns are unchanged. * 723 ***************************************************************************************************** 724 725 EVEN 726 732 48331C00637900001733 727 SCRADDRTST LIT SCR0 #0000 SCR0 = 0000 733 C8731C00637900011734 728 LIT SCR1 #0001 SCR1 = 0001 734 48B31C00637900021735 729 LIT SCR2 #0002 SCR2 = 0002 735 48F31C00637900031736 730 LIT SCR3 #0003 SCR3 = 0003 736 C9331C00637900041737 731 LIT SCR4 #0004 SCR4 = 0004 737 C9731C00637900051738 732 LIT SCR5 #0005 SCR5 = 0005 738 49B31C00637900061739 733 LIT SCR6 #0006 SCR6 = 0006 739 49F31C0063790007173A 734 LIT SCR7 #0007 SCR7 = 0007 73A CA331C0063790008173B 735 LIT SCR8 #0008 SCR8 = 0008 73B 4A731C0063790009173C 736 LIT SCR9 #0009 SCR9 = 0009 73C CAB31C006379000A173D 737 LIT SCRA #000A SCRA = 000A 73D CAF31C006379000B173E 738 LIT SCRB #000B SCRB = 000B 73E 4B331C006379000C173F 739 LIT SCRC #000C SCRC = 000C 73F CB731C006379000D1740 740 LIT SCRD #000D SCRD = 000D 740 4BB31C006379000E1741 741 LIT SCRE #000E SCRE = 000E 741 4BF31C006379000F1742 742 LIT SCRF #000F SCRF = 000F 742 CC331C00637900101743 743 LIT SCR10 #0010 SCR10 = 0010 743 4C731C00637900111744 744 LIT SCR11 #0011 SCR11 = 0011 744 CCB31C00637900121745 745 LIT SCR12 #0012 SCR12 = 0012 745 CCF31C00637900131746 746 LIT SCR13 #0013 SCR13 = 0013 746 4D331C00637900141747 747 LIT SCR14 #0014 SCR14 = 0014 747 4D731C00637900151748 748 LIT SCR15 #0015 SCR15 = 0015 748 CDB31C00637900161749 749 LIT SCR16 #0016 SCR16 = 0016 749 CDF31C0063790017174A 750 LIT SCR17 #0017 SCR17 = 0017 74A 4E331C0063790018174B 751 LIT SCR18 #0018 SCR18 = 0018 74B CE731C0063790019174C 752 LIT SCR19 #0019 SCR19 = 0019 74C 4EB31C006379001A174D 753 LIT SCR1A #001A SCR1A = 001A 74D 4EF31C006379001B174E 754 LIT SCR1B #001B SCR1B = 001B 74E CF331C006379001C174F 755 LIT SCR1C #001C SCR1C = 001C 74F 4F731C006379001D1750 756 LIT SCR1D #001D SCR1D = 001D 750 CFB31C006379001E1751 757 LIT SCR1E #001E SCR1E = 001E 751 CFF31C006379001F1752 758 LIT SCR1F #001F SCR1F = 001F 759 752 C8331C00637800001753 760 LIT RAM #00 #0000 1st check value = 0 753 D8130E0072DF00001754 761 SCR0 XOR RAM #00 #0000 SKIP SCR0 = 0000? 754 48331C00637907541C54 762 LIT SCR0 * ERRTN no 755 D8311C00633F00001756 763 NOP 764 756 C8331C00637800011757 765 LIT RAM #00 #0001 check pattern = #0001 757 58530E0072DF00001758 766 SCR1 XOR RAM #00 #0000 SKIP SCR1 = 0001? 758 48331C00637907581C54 767 LIT SCR0 * ERRTN no 759 D8311C00633F0000175A 768 NOP 769 75A C8331C0063780002175B 770 LIT RAM #00 #0002 check pattern = #0002 75B D8930E0072DF0000175C 771 SCR2 XOR RAM #00 #0000 SKIP SCR2 = 0002? 75C C8331C006379075C1C54 772 LIT SCR0 * ERRTN no 75D 58311C00633F0000175E 773 NOP 774 75E C8331C0063780003175F 775 LIT RAM #00 #0003 check pattern = #0003 75F 58D30E0072DF00001760 776 SCR3 XOR RAM #00 #0000 SKIP SCR3 = 0003? 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 115 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Scratch Pad Register Test 760 C8331C00637907601C54 777 LIT SCR0 * ERRTN no 761 58311C00633F00001762 778 NOP 779 762 48331C00637800041763 780 LIT RAM #00 #0004 check pattern = #0004 763 59130E0072DF00001764 781 SCR4 XOR RAM #00 #0000 SKIP SCR4 = 0004? 764 48331C00637907641C54 782 LIT SCR0 * ERRTN no 765 D8311C00633F00001766 783 NOP 784 766 48331C00637800051767 785 LIT RAM #00 #0005 check pattern = #0005 767 D9530E0072DF00001768 786 SCR5 XOR RAM #00 #0000 SKIP SCR5 = 0005? 768 48331C00637907681C54 787 LIT SCR0 * ERRTN no 769 D8311C00633F0000176A 788 NOP 789 76A 48331C0063780006176B 790 LIT RAM #00 #0006 check pattern = #0006 76B 59930E0072DF0000176C 791 SCR6 XOR RAM #00 #0000 SKIP SCR6 = 0006? 76C C8331C006379076C1C54 792 LIT SCR0 * ERRTN no 76D 58311C00633F0000176E 793 NOP 794 76E 48331C0063780007176F 795 LIT RAM #00 #0007 check pattern = #0007 76F 59D30E0072DF00001770 796 SCR7 XOR RAM #00 #0000 SKIP SCR7 = 0007? 770 48331C00637907701C54 797 LIT SCR0 * ERRTN no 771 D8311C00633F00001772 798 NOP 799 772 C8331C00637800081773 800 LIT RAM #00 #0008 check pattern = #0008 773 DA130E0072DF00001774 801 SCR8 XOR RAM #00 #0000 SKIP SCR8 = 0008? 774 C8331C00637907741C54 802 LIT SCR0 * ERRTN no 775 58311C00633F00001776 803 NOP 804 776 C8331C00637800091777 805 LIT RAM #00 #0009 check pattern = #0009 777 5A530E0072DF00001778 806 SCR9 XOR RAM #00 #0000 SKIP SCR9 = 0009? 778 C8331C00637907781C54 807 LIT SCR0 * ERRTN no 779 58311C00633F0000177A 808 NOP 809 77A C8331C006378000A177B 810 LIT RAM #00 #000A check pattern = #000A 77B DA930E0072DF0000177C 811 SCRA XOR RAM #00 #0000 SKIP SCRA = 000A? 77C 48331C006379077C1C54 812 LIT SCR0 * ERRTN no 77D D8311C00633F0000177E 813 NOP 814 77E C8331C006378000B177F 815 LIT RAM #00 #000B check pattern = #000B 77F 5AD30E0072DF00001780 816 SCRB XOR RAM #00 #0000 SKIP SCRB = 000B? 780 48331C00637907801C54 817 LIT SCR0 * ERRTN no 781 D8311C00633F00001782 818 NOP 819 782 48331C006378000C1783 820 LIT RAM #00 #000C check pattern = #000C 783 5B130E0072DF00001784 821 SCRC XOR RAM #00 #0000 SKIP SCRC = 000C? 784 C8331C00637907841C54 822 LIT SCR0 * ERRTN no 785 58311C00633F00001786 823 NOP 824 786 48331C006378000D1787 825 LIT RAM #00 #000D check pattern = #000D 787 DB530E0072DF00001788 826 SCRD XOR RAM #00 #0000 SKIP SCRD = 000D? 788 C8331C00637907881C54 827 LIT SCR0 * ERRTN no 789 58311C00633F0000178A 828 NOP 829 78A 48331C006378000E178B 830 LIT RAM #00 #000E check pattern = #000E 78B 5B930E0072DF0000178C 831 SCRE XOR RAM #00 #0000 SKIP SCRE = 000E? 78C 48331C006379078C1C54 832 LIT SCR0 * ERRTN no 78D D8311C00633F0000178E 833 NOP 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 116 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Scratch Pad Register Test 834 78E 48331C006378000F178F 835 LIT RAM #00 #000F check pattern = #000F 78F 5BD30E0072DF00001790 836 SCRF XOR RAM #00 #0000 SKIP SCRF = 000F? 790 C8331C00637907901C54 837 LIT SCR0 * ERRTN no 791 58311C00633F00001792 838 NOP 839 792 48331C00637800101793 840 LIT RAM #00 #0010 check pattern = #0010 793 5C130E0072DF00001794 841 SCR10 XOR RAM #00 #0000 SKIP SCR10 = 0010? 794 48331C00637907941C54 842 LIT SCR0 * ERRTN no 795 D8311C00633F00001796 843 NOP 844 796 48331C00637800111797 845 LIT RAM #00 #0011 check pattern = #0011 797 DC530E0072DF00001798 846 SCR11 XOR RAM #00 #0000 SKIP SCR11 = 0011? 798 48331C00637907981C54 847 LIT SCR0 * ERRTN no 799 D8311C00633F0000179A 848 NOP 849 79A 48331C0063780012179B 850 LIT RAM #00 #0012 check pattern = #0012 79B 5C930E0072DF0000179C 851 SCR12 XOR RAM #00 #0000 SKIP SCR12 = 0012? 79C C8331C006379079C1C54 852 LIT SCR0 * ERRTN no 79D 58311C00633F0000179E 853 NOP 854 79E 48331C0063780013179F 855 LIT RAM #00 #0013 check pattern = #0013 79F DCD30E0072DF000017A0 856 SCR13 XOR RAM #00 #0000 SKIP SCR13 = 0013? 7A0 C8331C00637907A01C54 857 LIT SCR0 * ERRTN no 7A1 58311C00633F000017A2 858 NOP 859 7A2 C8331C006378001417A3 860 LIT RAM #00 #0014 check pattern = #0014 7A3 DD130E0072DF000017A4 861 SCR14 XOR RAM #00 #0000 SKIP SCR14 = 0014? 7A4 48331C00637907A41C54 862 LIT SCR0 * ERRTN no 7A5 D8311C00633F000017A6 863 NOP 864 7A6 C8331C006378001517A7 865 LIT RAM #00 #0015 check pattern = #0015 7A7 5D530E0072DF000017A8 866 SCR15 XOR RAM #00 #0000 SKIP SCR15 = 0015? 7A8 48331C00637907A81C54 867 LIT SCR0 * ERRTN no 7A9 D8311C00633F000017AA 868 NOP 869 7AA C8331C006378001617AB 870 LIT RAM #00 #0016 check pattern = #0016 7AB DD930E0072DF000017AC 871 SCR16 XOR RAM #00 #0000 SKIP SCR16 = 0016? 7AC C8331C00637907AC1C54 872 LIT SCR0 * ERRTN no 7AD 58311C00633F000017AE 873 NOP 874 7AE C8331C006378001717AF 875 LIT RAM #00 #0017 check pattern = #0017 7AF DDD30E0072DF000017B0 876 SCR17 XOR RAM #00 #0000 SKIP SCR17 = 0017? 7B0 48331C00637907B01C54 877 LIT SCR0 * ERRTN no 7B1 D8311C00633F000017B2 878 NOP 879 7B2 48331C006378001817B3 880 LIT RAM #00 #0018 check pattern = #0018 7B3 5E130E0072DF000017B4 881 SCR18 XOR RAM #00 #0000 SKIP SCR18 = 0018? 7B4 C8331C00637907B41C54 882 LIT SCR0 * ERRTN no 7B5 58311C00633F000017B6 883 NOP 884 7B6 48331C006378001917B7 885 LIT RAM #00 #0019 check pattern = #0019 7B7 DE530E0072DF000017B8 886 SCR19 XOR RAM #00 #0000 SKIP SCR19 = 0019? 7B8 C8331C00637907B81C54 887 LIT SCR0 * ERRTN no 7B9 58311C00633F000017BA 888 NOP 889 7BA 48331C006378001A17BB 890 LIT RAM #00 #001A check pattern = #001A 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 117 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Scratch Pad Register Test 7BB 5E930E0072DF000017BC 891 SCR1A XOR RAM #00 #0000 SKIP SCR1A = 001A? 7BC 48331C00637907BC1C54 892 LIT SCR0 * ERRTN no 7BD D8311C00633F000017BE 893 NOP 894 7BE 48331C006378001B17BF 895 LIT RAM #00 #001B check pattern = #001B 7BF 5ED30E0072DF000017C0 896 SCR1B XOR RAM #00 #0000 SKIP SCR1B = 001B? 7C0 C8331C00637907C01C54 897 LIT SCR0 * ERRTN no 7C1 58311C00633F000017C2 898 NOP 899 7C2 48331C006378001C17C3 900 LIT RAM #00 #001C check pattern = #001C 7C3 5F130E0072DF000017C4 901 SCR1C XOR RAM #00 #0000 SKIP SCR1C = 001C? 7C4 48331C00637907C41C54 902 LIT SCR0 * ERRTN no 7C5 D8311C00633F000017C6 903 NOP 904 7C6 48331C006378001D17C7 905 LIT RAM #00 #001D check pattern = #001D 7C7 DF530E0072DF000017C8 906 SCR1D XOR RAM #00 #0000 SKIP SCR1D = 001D? 7C8 48331C00637907C81C54 907 LIT SCR0 * ERRTN no 7C9 D8311C00633F000017CA 908 NOP 909 7CA 48331C006378001E17CB 910 LIT RAM #00 #001E check pattern = #001E 7CB 5F930E0072DF000017CC 911 SCR1E XOR RAM #00 #0000 SKIP SCR1E = 001E? 7CC C8331C00637907CC1C54 912 LIT SCR0 * ERRTN no 7CD 58311C00633F000017CE 913 NOP 914 7CE 48331C006378001F17CF 915 LIT RAM #00 #001F check pattern = #001F 7CF 5FD30E0072DF000017D0 916 SCR1F XOR RAM #00 #0000 SKIP SCR1F = 001F? 7D0 48331C00637907D01C54 917 LIT SCR0 * ERRTN no 7D1 C8311C00636D000017D2 918 LIT INDX2 #0000 SCRTST next test, set index 919 TITLE.MAC PPU5 SELFTEST -- Scratch Pad Floating Ones and Zeros Patterns 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 118 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Scratch Pad Floating Ones and Zeros Pattern 920 ***************************************************************************************************** 921 * * 922 * This exerciser will test the 32 scratch pads with floating 1, * 923 * floating 0, and incrementing patterns. * 924 * * 925 ***************************************************************************************************** 926 927 ***************************************************************************************************** 928 * Floating Ones * 929 ***************************************************************************************************** 930 931 7D2 48331C006378000117D4 932 SCRTST X2 LIT RAM #00 #0001 SCRTST1 RAM 0 = 1st flt 1 patt 933 ODD 7D3 58130D8072D8000017D4 934 SCRTST1A X2 SCR0 ADD RAM RAM #00 #0000 SKIP shift left 1, done? 7D4 58301C00633F07D357DC 935 SCRTST1 SCRTST1A,P WSCR hit it 936 937 ***************************************************************************************************** 938 * Floating Zeroes * 939 ***************************************************************************************************** 940 7D5 C8331C006378FFFE17DA 941 X2 LIT RAM #00 #FFFE SCRTST2 RAM 0=1ST FLT. 0 PAT 7D6 58131E006359FFFF17D7 942 SCRTST2A X2 LIT XOR RAM SCR0 #FFFF invert pattern 7D7 48330C0062F8000017D8 943 X2 SCR0 RAM #00 RAM 0=SCR0 for add 7D8 D8130D8062D9000017D9 944 X2 SCR0 ADD RAM SCR0 #00 shift pattern left 1 7D9 D8130E0072F8FFFF17DA 945 X2 SCR0 XOR LIT RAM #00 #FFFF SKIP invert for FLT0, done? 7DA 58301C00633F07D657DC 946 SCRTST2 SCRTST2A,P WSCR write the scratch pads 7DB D8311C00633F0000183F 947 TESTCARY next test 948 TITLE.MAC PPU5 SELFTEST -- Subroutine to Write, Read, and Test Scratch Pads 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 119 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutine to Write, Read, and Test Scratch 949 ***************************************************************************************************** 950 * Subroutine to write, read, and test scratch pads * 951 ***************************************************************************************************** 952 7DC D0331C006359000017DD 953 WSCR X2 RAM SCR0 #00 7DD 50731C006359000017DE 954 X2 RAM SCR1 #00 7DE D0B31C006359000017DF 955 X2 RAM SCR2 #00 7DF 50F31C006359000017E0 956 X2 RAM SCR3 #00 7E0 51331C006359000017E1 957 X2 RAM SCR4 #00 7E1 D1731C006359000017E2 958 X2 RAM SCR5 #00 7E2 51B31C006359000017E3 959 X2 RAM SCR6 #00 7E3 51F31C006359000017E4 960 X2 RAM SCR7 #00 7E4 D2331C006359000017E5 961 X2 RAM SCR8 #00 7E5 52731C006359000017E6 962 X2 RAM SCR9 #00 7E6 D2B31C006359000017E7 963 X2 RAM SCRA #00 7E7 52F31C006359000017E8 964 X2 RAM SCRB #00 7E8 53331C006359000017E9 965 X2 RAM SCRC #00 7E9 D3731C006359000017EA 966 X2 RAM SCRD #00 7EA 53B31C006359000017EB 967 X2 RAM SCRE #00 7EB 53F31C006359000017EC 968 X2 RAM SCRF #00 7EC 54331C006359000017ED 969 X2 RAM SCR10 #00 7ED D4731C006359000017EE 970 X2 RAM SCR11 #00 7EE 54B31C006359000017EF 971 X2 RAM SCR12 #00 7EF 54F31C006359000017F0 972 X2 RAM SCR13 #00 7F0 55331C006359000017F1 973 X2 RAM SCR14 #00 7F1 D5731C006359000017F2 974 X2 RAM SCR15 #00 7F2 55B31C006359000017F3 975 X2 RAM SCR16 #00 7F3 55F31C006359000017F4 976 X2 RAM SCR17 #00 7F4 D6331C006359000017F5 977 X2 RAM SCR18 #00 7F5 56731C006359000017F6 978 X2 RAM SCR19 #00 7F6 D6B31C006359000017F7 979 X2 RAM SCR1A #00 7F7 56F31C006359000017F8 980 X2 RAM SCR1B #00 7F8 57331C006359000017F9 981 X2 RAM SCR1C #00 7F9 D7731C006359000017FA 982 X2 RAM SCR1D #00 7FA 57B31C006359000017FB 983 X2 RAM SCR1E #00 7FB D7F31C006359000017FD 984 X2 RAM SCR1F #00 RSCR 985 986 ODD 7FC 4FF31C00637907FC17FC 986$ WSTE0057 LIT SCR1F * * ****** wasted ****** 7FD D8130E0072DF000017FE 987 RSCR X2 SCR0 XOR RAM #00 #0000 SKIP SCR0 ok? 7FE 48331C00637907FE1C54 988 LIT SCR0 * ERRTN SCR0 bad 7FF D8530E0072DF00001800 989 X2 SCR1 XOR RAM #00 #0000 SKIP SCR1 ok? 800 C8331C00637908001C54 990 LIT SCR0 * ERRTN SCR1 bad 801 58930E0072DF00001802 991 X2 SCR2 XOR RAM #00 #0000 SKIP SCR2 ok? 802 48331C00637908021C54 992 LIT SCR0 * ERRTN SCR2 bad 803 D8D30E0072DF00001804 993 X2 SCR3 XOR RAM #00 #0000 SKIP SCR3 ok? 804 48331C00637908041C54 994 LIT SCR0 * ERRTN SCR3 bad 805 D9130E0072DF00001806 995 X2 SCR4 XOR RAM #00 #0000 SKIP SCR4 ok? 806 C8331C00637908061C54 996 LIT SCR0 * ERRTN SCR4 bad 807 D9530E0072DF00001808 997 X2 SCR5 XOR RAM #00 #0000 SKIP SCR5 ok? 808 48331C00637908081C54 998 LIT SCR0 * ERRTN SCR5 bad 809 59930E0072DF0000180A 999 X2 SCR6 XOR RAM #00 #0000 SKIP SCR6 ok? 80A C8331C006379080A1C54 1000 LIT SCR0 * ERRTN SCR6 bad 80B D9D30E0072DF0000180C 1001 X2 SCR7 XOR RAM #00 #0000 SKIP SCR7 ok? 80C C8331C006379080C1C54 1002 LIT SCR0 * ERRTN SCR7 bad 80D 5A130E0072DF0000180E 1003 X2 SCR8 XOR RAM #00 #0000 SKIP SCR8 ok? 80E 48331C006379080E1C54 1004 LIT SCR0 * ERRTN SCR8 bad 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 120 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutine to Write, Read, and Test Scratch 80F DA530E0072DF00001810 1005 X2 SCR9 XOR RAM #00 #0000 SKIP SCR9 ok? 810 48331C00637908101C54 1006 LIT SCR0 * ERRTN SCR9 bad 811 5A930E0072DF00001812 1007 X2 SCRA XOR RAM #00 #0000 SKIP SCRA ok? 812 C8331C00637908121C54 1008 LIT SCR0 * ERRTN SCRA bad 813 DAD30E0072DF00001814 1009 X2 SCRB XOR RAM #00 #0000 SKIP SCRB ok? 814 C8331C00637908141C54 1010 LIT SCR0 * ERRTN SCRB bad 815 DB130E0072DF00001816 1011 X2 SCRC XOR RAM #00 #0000 SKIP SCRC ok? 816 48331C00637908161C54 1012 LIT SCR0 * ERRTN SCRC bad 817 DB530E0072DF00001818 1013 X2 SCRD XOR RAM #00 #0000 SKIP SCRD ok? 818 C8331C00637908181C54 1014 LIT SCR0 * ERRTN SCRD bad 819 5B930E0072DF0000181A 1015 X2 SCRE XOR RAM #00 #0000 SKIP SCRE ok? 81A 48331C006379081A1C54 1016 LIT SCR0 * ERRTN SCRE bad 81B DBD30E0072DF0000181C 1017 X2 SCRF XOR RAM #00 #0000 SKIP SCRF ok? 81C 48331C006379081C1C54 1018 LIT SCR0 * ERRTN SCRF bad 81D DC130E0072DF0000181E 1019 X2 SCR10 XOR RAM #00 #0000 SKIP SCR10 ok? 81E C8331C006379081E1C54 1020 LIT SCR0 * ERRTN SCR10 bad 81F DC530E0072DF00001820 1021 X2 SCR11 XOR RAM #00 #0000 SKIP SCR11 ok? 820 48331C00637908201C54 1022 LIT SCR0 * ERRTN SCR11 bad 821 5C930E0072DF00001822 1023 X2 SCR12 XOR RAM #00 #0000 SKIP SCR12 ok? 822 C8331C00637908221C54 1024 LIT SCR0 * ERRTN SCR12 bad 823 DCD30E0072DF00001824 1025 X2 SCR13 XOR RAM #00 #0000 SKIP SCR13 ok? 824 C8331C00637908241C54 1026 LIT SCR0 * ERRTN SCR13 bad 825 DD130E0072DF00001826 1027 X2 SCR14 XOR RAM #00 #0000 SKIP SCR14 ok? 826 48331C00637908261C54 1028 LIT SCR0 * ERRTN SCR14 bad 827 DD530E0072DF00001828 1029 X2 SCR15 XOR RAM #00 #0000 SKIP SCR15 ok? 828 C8331C00637908281C54 1030 LIT SCR0 * ERRTN SCR15 bad 829 5D930E0072DF0000182A 1031 X2 SCR16 XOR RAM #00 #0000 SKIP SCR16 ok? 82A 48331C006379082A1C54 1032 LIT SCR0 * ERRTN SCR16 bad 82B DDD30E0072DF0000182C 1033 X2 SCR17 XOR RAM #00 #0000 SKIP SCR17 ok? 82C 48331C006379082C1C54 1034 LIT SCR0 * ERRTN SCR17 bad 82D 5E130E0072DF0000182E 1035 X2 SCR18 XOR RAM #00 #0000 SKIP SCR18 ok? 82E C8331C006379082E1C54 1036 LIT SCR0 * ERRTN SCR18 bad 82F DE530E0072DF00001830 1037 X2 SCR19 XOR RAM #00 #0000 SKIP SCR19 ok? 830 C8331C00637908301C54 1038 LIT SCR0 * ERRTN SCR19 bad 831 5E930E0072DF00001832 1039 X2 SCR1A XOR RAM #00 #0000 SKIP SCR1A ok? 832 48331C00637908321C54 1040 LIT SCR0 * ERRTN SCR1A bad 833 DED30E0072DF00001834 1041 X2 SCR1B XOR RAM #00 #0000 SKIP SCR1B ok? 834 48331C00637908341C54 1042 LIT SCR0 * ERRTN SCR1B bad 835 DF130E0072DF00001836 1043 X2 SCR1C XOR RAM #00 #0000 SKIP SCR1C ok? 836 C8331C00637908361C54 1044 LIT SCR0 * ERRTN SCR1C bad 837 DF530E0072DF00001838 1045 X2 SCR1D XOR RAM #00 #0000 SKIP SCR1D ok? 838 48331C00637908381C54 1046 LIT SCR0 * ERRTN SCR1D bad 839 5F930E0072DF0000183A 1047 X2 SCR1E XOR RAM #00 #0000 SKIP SCR1E ok? 83A C8331C006379083A1C54 1048 LIT SCR0 * ERRTN SCR1E bad 83B DFD30E0072DF0000183C 1049 X2 SCR1F XOR RAM #00 #0000 SKIP SCR1F ok? 83C C8331C006379083C1C54 1050 LIT SCR0 * ERRTN SCR1F bad 83D 58301C00633F00009EF1 1051 POP STERR return 1052 TITLE.MAC PPU5 SELFTEST -- Carry Logic Test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 121 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Carry Logic Test 1053 ***************************************************************************************************** 1054 * * 1055 * The next test does 2 consecutive adds W/O carry to see if carry * 1056 * in got set, then sets carry to see if carry in is functional. * 1057 * * 1058 * S1 ALU S2 DEST.(RESULT) * 1059 * CARRY OUT CARRY IN SCR4 ADD RAM RAM * 1060 * 1 0 + FFFF + 0001 = 0000 * 1061 * 0 0 + FFFF + 0000 = FFFF * 1062 * * 1063 ***************************************************************************************************** 1064 1065 ODD 83E 4FF31C006379083E183E 1065$ WSTE0058 LIT SCR1F * * ****** wasted ****** 1066 83F 49331C006379FFFF1840 1067 TESTCARY LIT SCR4 #FFFF SCR4 = #FFFF 840 48331C00637800011841 1068 X2 LIT RAM #00 #0001 (RAM #00) = #0001 841 59130D8072D800001843 1069 X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 ADD w/o carry = 0? 842 D9130D8072D8FFFF1844 1070 X2 SCR4 ADD RAM RAM #00 #FFFF SKIP *+2 did carry get set? 843 48331C00637908431C54 1071 LIT SCR0 * ERRTN #FFFF+1+0 <> 0 844 C8331C00637908441C54 1072 LIT SCR0 * ERRTN #FFFF+0+0 <> #FFFF 845 58311C00633F00001846 1073 NOP 846 49335C006379FFFF1847 1074 STC LIT SCR4 #FFFF SCR4 = ones, carry = 1 847 19130D8072F900001848 1075 TWC SCR4 ADD LIT SCR4 #0000 SKIP does FFFF + 0 + 1 = 0? 848 C8331C00637908481C54 1076 LIT SCR0 * ERRTN carry in logic failed 1077 1078 ***************************************************************************************************** 1079 * * 1080 * This sequence initializes carry in to a 0, generates a carry * 1081 * out with carry logic enabled, checking for no carry in, does another * 1082 * add, checking for carry in, and does one more add making sure carry * 1083 * got flushed out. * 1084 * * 1085 * S1 ALU S2 DEST.(RESULT) * 1086 * CARRY OUT CARRY IN SCR4 ADD RAM RAM * 1087 * 1 0 + FFFF + 0001 = 0000 * 1088 * 0 1 + FFFF + 0000 = 0000 * 1089 * 0 0 + FFFF + 0000 = FFFF * 1090 * * 1091 ***************************************************************************************************** 1092 849 58311C00633F0000184A 1093 NOP 84A C9331C006379FFFF184B 1094 LIT SCR4 #FFFF set SCR4 to ones 84B C8731C006379FFFE184C 1095 LIT SCR1 #FFFE *+1 use SCR1 for counter 84C 4833DC0063780001184D 1096 CLC,X2 LIT RAM #00 #0001 (RAM #00) = #0001 84D 19138D8072D80000184F 1097 TWC,CST,X2 SCR4 ADD RAM RAM #00 0 SKIP *+2 DEST SB 0,CRY=1 @ RDTS 84E 99138D8072D800001850 1098 CST,TWC,X2 SCR4 ADD RAM RAM #00 0 SKIP *+2 DEST SB 0,CRY=0 @ RDTS 84F 48331C006379084F1C54 1099 LIT SCR0 * ERRTN #FFFF+#0001+0 <> #0000 850 C8331C00637908501C54 1100 LIT SCR0 * ERRTN #FFFF+#0000+1 <> #0000 851 18530D8072D8FFFF1853 1101 TWC,X2 SCR1 ADD RAM RAM #00 #FFFF SKIP *+2 did carry clear? 852 58311C00633F00001854 1102 TESTCARY0 ok 853 C8331C00637908531C54 1103 LIT SCR0 * ERRTN #FFFF+#0000+0 <> #0000 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 122 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Carry Logic Test 1105 ***************************************************************************************************** 1106 * This test part will test the external carry logic connected to * 1107 * the 74S381's by doing the following add sequence: * 1108 * * 1109 * S1 ALU S2 DEST.(RESULT) * 1110 * CARRY IN SCR4 ADD RAM RAM * 1111 * 1 + 0 + 1 = 2 * 1112 * 1 + 0 + 3 = 4 * 1113 * 1 + 0 + 7 = 8 * 1114 * * 1115 * 1 + 0 + ETC = ETC * 1116 * * 1117 * 1 + 0 + 1FFF = 2000 * 1118 * 1 + 0 + 3FFF = 4000 * 1119 * 1 + 0 + 7FFF = 8000 * 1120 * * 1121 * The test repeats the same sequence with source 2 = 0. * 1122 ***************************************************************************************************** 1123 1124 EVEN 854 49331C00637900011855 1125 TESTCARY0 LIT SCR4 #0001 starting S1 pattern 855 C8F31C00637900021856 1126 LIT SCR3 #0002 starting known good 856 4833DC00637800001857 1127 TESTCARY1 CLC,X2 LIT RAM #00 #0000 S2 will be 0 this time 857 D8315C00633F00001858 1128 STC generate a carry 858 99130D8062D800001859 1129 TWC,X2 SCR4 ADD RAM RAM #00 S1 + 0 + 1 = S1 +1 859 D8D30E0072DF0000185B 1130 X2 SCR3 XOR RAM #00 #0000 SKIP *+2 okay? 85A D8311C00633F0000185C 1131 *+2 yes 85B 48331C006379085B1C54 1132 LIT SCR0 * ERRTN add with carry failed 1133 85C D1331C0063590000185D 1134 X2 RAM SCR4 #00 get old result in SCR4 85D D9130D8072D80000185F 1135 X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 new known good, done? 85E 58311C00633F00001861 1136 TESTCARY2 next test 85F D0F31C00635900001860 1137 X2 RAM SCR3 #00 save new known good 1138 * if not done 860 59131D806359FFFF1856 1139 X2 LIT ADD RAM SCR4 #00 #FFFF TESTCARY1 subtract 1 for new 1140 * pattern & loop 1141 1142 ODD 1143 861 C8B31C00637900011862 1144 TESTCARY2 LIT SCR2 #0001 starting S2 pattern 862 C8F31C00637900021863 1145 LIT SCR3 #0002 starting known good 863 49331C00637900001864 1146 TESTCARY3 LIT SCR4 #0000 S1 stayed 0 this time 864 C8B3CC0062F800001865 1147 CLC,X2 SCR2 RAM #00 S2 pattern to RAM 865 D8109D80637FFFFF1866 1148 CST LIT ADD LIT #FFFF generate a carry 866 19130D8062D800001867 1149 TWC,X2 SCR4 ADD RAM RAM #00 0 + S2 + 1 = S2 + 1 867 58D30E0072DF00001869 1150 X2 SCR3 XOR RAM #00 #0000 SKIP *+2 okay? 868 D8311C00633F0000186A 1151 *+2 okay 869 C8331C00637908691C54 1152 LIT SCR0 * ERRTN add with carry failed 1153 86A D1331C0063590000186B 1154 X2 RAM SCR4 #00 old result to SCR4 86B 59130D8072D80000186D 1155 X2 SCR4 ADD RAM RAM #00 #0000 SKIP *+2 double it, done? 86C D8311C00633F0000186F 1156 TESTCARY5 next test 86D 50F31C0063590000186E 1157 X2 RAM SCR3 #00 save it in SCR3 86E 58931D806359FFFF1863 1158 X2 LIT ADD RAM SCR2 #00 #FFFF TESTCARY3 new S2 patt & loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 123 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Carry Logic Test 1160 ***************************************************************************************************** 1161 * * 1162 * subtract source 1 from source 2 * 1163 * * 1164 ***************************************************************************************************** 1165 86F 49331C006379FFFF1870 1166 TESTCARY5 LIT SCR4 #FFFF set SCR4 = #FFFF 870 48335C00637800001871 1167 STC,X2 LIT RAM #00 #0000 RAM 0=0,CIN=0 for sub 871 99130C8072D900011872 1168 TWC,X2 SCR4 RSUB RAM SCR4 #00 1 SKIP 1 0000 (-) FFFF=0001? 872 C8331C00637908721C54 1169 LIT SCR0 * ERRTN sub S1 from S2 bad 1170 1171 ***************************************************************************************************** 1172 * * 1173 * subtract source 2 from source 1 * 1174 * * 1175 ***************************************************************************************************** 1176 873 C9331C00637900001874 1177 LIT SCR4 #0000 SCR4 = 0000 874 C8335C006378FFFF1875 1178 STC,X2 LIT RAM #00 #FFFF RAM 00 = FFFF 875 19130D0072D900011876 1179 TWC,X2 SCR4 SUB RAM SCR4 #00 1 SKIP 1 0000 (-) FFFF=0001? 876 48331C00637908761C54 1180 LIT SCR0 * ERRTN sub S2 from S1 bad 877 D8311C00633F00001878 1181 RAM89TEST next test 1182 TITLE.MAC PPU5 SELFTEST -- RAM Test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 124 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RAM Test 1183 ***************************************************************************************************** 1184 * * 1185 * The major purpose of this test is to test out the RAM. * 1186 * * 1187 * Variable assignments: * 1188 * SCR10 - data to store or check. * 1189 * SCR1 - usually, index register value * 1190 * SCR2 - data check to do (zeros, ones, address, complement address) * 1191 * SCR3 - address pointer used by subroutines that use RAM address register. * 1192 * SCR4 - type of write to be done * 1193 * SCR5 - type of read to be done * 1194 * * 1195 * SCR2, SCR4, and SCR5 all have a constant (generated by the * 1196 * BLOCK macro) IOR'ed in with the starting value because these three * 1197 * registers are used for indexed jumps into blocks that are not 16 in * 1198 * length. These constants are needed to allow the indexed jumps into * 1199 * the proper block. * 1200 * * 1201 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 125 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RAM Test 1203 ***************************************************************************************************** 1204 * floating all ones and one zero * 1205 ***************************************************************************************************** 1206 878 49331C00637900001879 1207 RAM89TEST LIT SCR4 WRALL89IOR first write type 879 C9731C0063790000187A 1208 RAM89TESTA LIT SCR5 RRALL89IOR first read type 1209 87A 48B31C0063790040187B 1210 LIT SCR2 (#0000+(DATAMODIOR*#10)) set data mod flags 87B D8301C00633F087C58E4 1211 *+1,P DATAMOD GET FIRST DATA 87C 58301C00633F087D58A0 1212 *+1,P WRALL89 write RAM 87D 48B31C0063790040187E 1213 RRAM89 LIT SCR2 (#0000+(DATAMODIOR*#10)) set data mod flags 87E D8301C00633F087F58E4 1214 *+1,P DATAMOD get first data 87F 58301C00633F088058A1 1215 *+1,P RRALL89 read & check RAM 880 59530F0072FF00031882 1216 SCR5 AND LIT #0003 SKIP RRAM89LOOP all rd types? 1217 1218 >>>>>>>>>>>>>>>>>>>>> 1219 > EVEN 881 4FF31C00637908811881 1219$>WSTE0059 LIT SCR1F * * ****** wasted ****** 882 59530D8062F90001187D 1220 >RRAM89LOOP SCR5 ADD LIT SCR5 #0001 RRAM89 no,nxt rd typ,loop 883 49731C00637900001884 1221 > LIT SCR5 RRALL89IOR yes,first read type 1222 >>>>>>>>>>>>>>>>>>>>> 1224 ***************************************************************************************************** 1225 * Floating all zeros and a one * 1226 ***************************************************************************************************** 1227 884 48B31C00637900501885 1228 WONE89 LIT SCR2 (#0010+(DATAMODIOR*#10)) set data mod flags 885 D8301C00633F088658E4 1229 *+1,P DATAMOD get first data 886 58301C00633F088758A0 1230 *+1,P WRALL89 write RAM 887 C8B31C00637900501888 1231 RONE89 LIT SCR2 (#0010+(DATAMODIOR*#10)) set data mod flags 888 D8301C00633F088958E4 1232 *+1,P DATAMOD get first data 889 58301C00633F088A58A1 1233 *+1,P RRALL89 read&check RAM 88A D9530F0072FF0003188C 1234 SCR5 AND LIT #0003 SKIP RONE89LOOP all rd types? 1235 1236 >>>>>>>>>>>>>>>>>>>>> 1237 > EVEN 88B 4FF31C006379088B188B 1237$>WSTE0060 LIT SCR1F * * ****** wasted ****** 88C 59530D8062F900011887 1238 >RONE89LOOP SCR5 ADD LIT SCR5 #0001 RONE89 no,nxt rd typ,loop 88D 49731C0063790000188E 1239 > LIT SCR5 RRALL89IOR yes,first read type 1240 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 126 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RAM Test 1242 ***************************************************************************************************** 1243 * Address * 1244 ***************************************************************************************************** 1245 88E 48B31C0063790060188F 1246 LIT SCR2 (#0020+(DATAMODIOR*#10)) set data mod flag 88F CC331C00637900001890 1247 LIT SCR10 #0000 initial data=0 890 D8301C00633F089158A0 1248 *+1,P WRALL89 write RAM 891 4C331C00637900001892 1249 RADR89 LIT SCR10 #0000 initial data=0 892 D8301C00633F089358A1 1250 *+1,P RRALL89 read&check RAM 893 D9530F0072FF00031894 1251 SCR5 AND LIT #0003 SKIP RADR89LOOP all rd types? 1252 1253 >>>>>>>>>>>>>>>>>>>>> 1254 > EVEN 894 D9530D8062F900011891 1255 >RADR89LOOP SCR5 ADD LIT SCR5 #0001 RADR89 no,nxt rd typ,loop 895 49731C00637900001896 1256 > LIT SCR5 RRALL89IOR yes,first read type 1257 >>>>>>>>>>>>>>>>>>>>> 1259 ***************************************************************************************************** 1260 * complement address * 1261 ***************************************************************************************************** 1262 896 C8B31C00637900701897 1263 WCADR89 LIT SCR2 (#0030+(DATAMODIOR*#10)) set data mod flag 897 4C331C006379FFFF1898 1264 LIT SCR10 #FFFF initial data=FFFF 898 58301C00633F089958A0 1265 *+1,P WRALL89 write RAM 899 CC331C006379FFFF189A 1266 RCADR89 LIT SCR10 #FFFF initial data=FFFF 89A 58301C00633F089B58A1 1267 *+1,P RRALL89 read & check RAM 89B 59530F0072FF0003189C 1268 SCR5 AND LIT #0003 SKIP RCADR89LOOP all rd types? 1269 1270 >>>>>>>>>>>>>>>>>>>>> 1271 > EVEN 89C 59530D8062F900011899 1272 >RCADR89LOOP SCR5 ADD LIT SCR5 #0001 RCADR89 no,nxt rd type,loop 89D 59130F0072FF0005189E 1273 > SCR4 AND LIT #0005 SKIP RAM89WRITELOOP yes,al wrt type 1274 >>>>>>>>>>>>>>>>>>>>> 1275 1276 >>>>>>>>>>>>>>>>>>>>> 1277 > EVEN 89E 59130D8062F900011879 1278 >RAM89WRITELOOP SCR4 ADD LIT SCR4 #0001 RAM89TESTA no,nxt wrt type,loop 89F D8311C00633F0000194A 1279 > CONFIG yes,next test 1280 >>>>>>>>>>>>>>>>>>>>> 1281 TITLE.MAC PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 127 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1282 1283 ***************************************************************************************************** 1284 * * 1285 * There subroutines read or write RAM from addresses 0 to 3FF. * 1286 * They pick the type of read or write to do based on the value in SCR4 * 1287 * (for writing) or SCR5 (for reading). There are convenient IOR * 1288 * constants to use to set SCR4 and SCR5 correctly. It will be assumed * 1289 * that the calling routine already IOR'ed in the correct constant * 1290 * before the subroutine was called. * 1291 * * 1292 * SCR10 should be initialized to the first data value before calling * 1293 * these subroutines. * 1294 * SCR2 should be initialized to the correct value before calling * 1295 * these subroutines. * 1296 * * 1297 ***************************************************************************************************** 1298 8A0 4933080072FF00001E00 1299 WRALL89 SCR4 DB0 WRALL89BLOCK pick a subroutine 8A1 C973080072FF00001DF0 1300 RRALL89 SCR5 DB0 RRALL89BLOCK pick a subroutine 1301 1302 >>>>>>>>>>>>>>>>>>>>> 1303 > BLOCK 8,WRALL89IOR E00 D8311C00633F0000190D 1304 >WRALL89BLOCK WRALLRADRX1 SCR4=0 E01 D8311C00633F00001919 1305 > WRALLRADRX1R SCR4=1 E02 D8311C00633F00001925 1306 > WRALLRADRX2 SCR4=2 E03 D8311C00633F00001931 1307 > WRALLRADRX2R SCR4=3 E04 58311C00633F000018A2 1308 > WRALLX1 SCR4=4 E05 D8311C00633F000018AC 1309 > WRALLX2 SCR4=5 E06 58311C00633F00001EF1 1310 > STERR shouldn't get here E07 58311C00633F00001EF1 1311 > STERR shouldn't get here 1312 > ENDBLOCK 1313 >>>>>>>>>>>>>>>>>>>>> 1314 1315 >>>>>>>>>>>>>>>>>>>>> 1316 > BLOCK 4,RRALL89IOR DF0 58311C00633F000018E9 1317 >RRALL89BLOCK RRALLRADRX1 SCR5=0 DF1 D8311C00633F000018F5 1318 > RRALLRADRX2 SCR5=1 DF2 58311C00633F000018C2 1319 > RRALLX1 SCR5=2 DF3 58311C00633F000018CE 1320 > RRALLX2 SCR5=3 1321 > ENDBLOCK 1322 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 128 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1324 1325 ***************************************************************************************************** 1326 * * 1327 * These subroutines are used by RAM89TEST to write the RAM using * 1328 * the RAM address field of the instruction. * 1329 * * 1330 * These subroutines were derived from * 1331 * DIAGNOSTIC.HRDPP5:SECTION5.SOURCE, but they were changed somewhat to * 1332 * conserve space. In particular, the RAM and ",R" opcodes are both * 1333 * used randomly rather than having a separate subroutine for each. * 1334 * * 1335 * SCR10 and SCR2 should be initialized before these subroutines are called. * 1336 * * 1337 ***************************************************************************************************** 1338 1339 ***************************************************************************************************** 1340 * Write RAM using X1 and RAM OPCODE and RAM ADDRESS field of instruction * 1341 ***************************************************************************************************** 1342 8A2 48F31C006379000018A3 1343 WRALLX1 LIT SCR3 #0000 addr ptr=0 8A3 48731C006379000018A4 1344 LIT SCR1 #0000 INDEX = 0 8A4 C8710C0062F3000018A5 1345 WRALLX1A SCR1 INDX1 set X1 8A5 58D00F0062F4030018A6 1346 SCR3 AND LIT RADR #0300 set RADR bits 8:9 8A6 C8F3080072FF08A75DE0 1347 SCR3 *+1,P DB0 WRAX1LSBLK go do write 8A7 58D30F0072FF03FF18A9 1348 SCR3 AND LIT #03FF SKIP WRALLX1C done yet? 1349 >>>>>>>>>>>>>>>>>>>>> 1350 > EVEN 8A8 58D30D8062F9000118E4 1351 > SCR3 ADD LIT SCR3 #0001 DATAMOD done,update data 8A9 58D30D8062F9000118AA 1352 >WRALLX1C SCR3 ADD LIT SCR3 #0001 no,addr + 1 1353 >>>>>>>>>>>>>>>>>>>>> 8AA 58530D8062F9000118AB 1354 SCR1 ADD LIT SCR1 #0001 INDEX + 1 8AB D8530F0062F9000318A4 1355 SCR1 AND LIT SCR1 #0003 WRALLX1A clr bits 2:15,loop 1356 1357 >>>>>>>>>>>>>>>>>>>>> 1358 > BLOCK 16 DE0 48F3040072FF00001DD0 1359 >WRAX1LSBLK SCR3 DB4 WRAX1MS0BLK SCR3 bits 2:3=0 DE1 48F3040072FF00001DD0 1360 > SCR3 DB4 WRAX1MS0BLK SCR3 bits 2:3=0 DE2 48F3040072FF00001DD0 1361 > SCR3 DB4 WRAX1MS0BLK SCR3 bits 2:3=0 DE3 48F3040072FF00001DD0 1362 > SCR3 DB4 WRAX1MS0BLK SCR3 bits 2:3=0 DE4 C8F3040072FF00001DC0 1363 > SCR3 DB4 WRAX1MS1BLK SCR3 bits 2:3=1 DE5 C8F3040072FF00001DC0 1364 > SCR3 DB4 WRAX1MS1BLK SCR3 bits 2:3=1 DE6 C8F3040072FF00001DC0 1365 > SCR3 DB4 WRAX1MS1BLK SCR3 bits 2:3=1 DE7 C8F3040072FF00001DC0 1366 > SCR3 DB4 WRAX1MS1BLK SCR3 bits 2:3=1 DE8 48F3040072FF00001DB0 1367 > SCR3 DB4 WRAX1MS2BLK SCR3 bits 2:3=2 DE9 48F3040072FF00001DB0 1368 > SCR3 DB4 WRAX1MS2BLK SCR3 bits 2:3=2 DEA 48F3040072FF00001DB0 1369 > SCR3 DB4 WRAX1MS2BLK SCR3 bits 2:3=2 DEB 48F3040072FF00001DB0 1370 > SCR3 DB4 WRAX1MS2BLK SCR3 bits 2:3=2 DEC C8F3040072FF00001DA0 1371 > SCR3 DB4 WRAX1MS3BLK SCR3 bits 2:3=3 DED C8F3040072FF00001DA0 1372 > SCR3 DB4 WRAX1MS3BLK SCR3 bits 2:3=3 DEE C8F3040072FF00001DA0 1373 > SCR3 DB4 WRAX1MS3BLK SCR3 bits 2:3=3 DEF C8F3040072FF00001DA0 1374 > SCR3 DB4 WRAX1MS3BLK SCR3 bits 2:3=3 1375 > ENDBLOCK 1376 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 129 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1378 >>>>>>>>>>>>>>>>>>>>> 1379 > BLOCK 16 DD0 6C330C0062F8000018E4 1380 >WRAX1MS0BLK X1 SCR10 RAM #00 DATAMOD DD1 EC3B0C0462F9000018E4 1381 > X1 SCR10 SCR10,R #10 DATAMOD DD2 EC330C0862F8000018E4 1382 > X1 SCR10 RAM #20 DATAMOD DD3 6C330C0C62F8000018E4 1383 > X1 SCR10 RAM #30 DATAMOD DD4 EC3B0C1062F9000018E4 1384 > X1 SCR10 SCR10,R #40 DATAMOD DD5 6C3B0C1462F9000018E4 1385 > X1 SCR10 SCR10,R #50 DATAMOD DD6 6C330C1862F8000018E4 1386 > X1 SCR10 RAM #60 DATAMOD DD7 EC330C1C62F8000018E4 1387 > X1 SCR10 RAM #70 DATAMOD DD8 EC330C2062F8000018E4 1388 > X1 SCR10 RAM #80 DATAMOD DD9 6C3B0C2462F9000018E4 1389 > X1 SCR10 SCR10,R #90 DATAMOD DDA 6C3B0C2862F9000018E4 1390 > X1 SCR10 SCR10,R #A0 DATAMOD DDB EC3B0C2C62F9000018E4 1391 > X1 SCR10 SCR10,R #B0 DATAMOD DDC 6C330C3062F8000018E4 1392 > X1 SCR10 RAM #C0 DATAMOD DDD EC3B0C3462F9000018E4 1393 > X1 SCR10 SCR10,R #D0 DATAMOD DDE EC3B0C3862F9000018E4 1394 > X1 SCR10 SCR10,R #E0 DATAMOD DDF 6C330C3C62F8000018E4 1395 > X1 SCR10 RAM #F0 DATAMOD 1396 > ENDBLOCK 1397 >>>>>>>>>>>>>>>>>>>>> 1399 >>>>>>>>>>>>>>>>>>>>> 1400 > BLOCK 16 DC0 EC3B0C0162F9000018E4 1401 >WRAX1MS1BLK X1 SCR10 SCR10,R #04 DATAMOD DC1 6C330C0562F8000018E4 1402 > X1 SCR10 RAM #14 DATAMOD DC2 6C3B0C0962F9000018E4 1403 > X1 SCR10 SCR10,R #24 DATAMOD DC3 EC3B0C0D62F9000018E4 1404 > X1 SCR10 SCR10,R #34 DATAMOD DC4 6C330C1162F8000018E4 1405 > X1 SCR10 RAM #44 DATAMOD DC5 EC330C1562F8000018E4 1406 > X1 SCR10 RAM #54 DATAMOD DC6 EC3B0C1962F9000018E4 1407 > X1 SCR10 SCR10,R #64 DATAMOD DC7 6C3B0C1D62F9000018E4 1408 > X1 SCR10 SCR10,R #74 DATAMOD DC8 6C3B0C2162F9000018E4 1409 > X1 SCR10 SCR10,R #84 DATAMOD DC9 EC330C2562F8000018E4 1410 > X1 SCR10 RAM #94 DATAMOD DCA EC330C2962F8000018E4 1411 > X1 SCR10 RAM #A4 DATAMOD DCB 6C330C2D62F8000018E4 1412 > X1 SCR10 RAM #B4 DATAMOD DCC EC3B0C3162F9000018E4 1413 > X1 SCR10 SCR10,R #C4 DATAMOD DCD 6C3B0C3562F9000018E4 1414 > X1 SCR10 SCR10,R #D4 DATAMOD DCE 6C3B0C3962F9000018E4 1415 > X1 SCR10 SCR10,R #E4 DATAMOD DCF EC3B0C3D62F9000018E4 1416 > X1 SCR10 SCR10,R #F4 DATAMOD 1417 > ENDBLOCK 1418 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 130 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1420 >>>>>>>>>>>>>>>>>>>>> 1421 > BLOCK 16 DB0 EC3B0C0262F9000018E4 1422 >WRAX1MS2BLK X1 SCR10 SCR10,R #08 DATAMOD DB1 6C3B0C0662F9000018E4 1423 > X1 SCR10 SCR10,R #18 DATAMOD DB2 6C3B0C0A62F9000018E4 1424 > X1 SCR10 SCR10,R #28 DATAMOD DB3 EC3B0C0E62F9000018E4 1425 > X1 SCR10 SCR10,R #38 DATAMOD DB4 6C330C1262F8000018E4 1426 > X1 SCR10 RAM #48 DATAMOD DB5 EC330C1662F8000018E4 1427 > X1 SCR10 RAM #58 DATAMOD DB6 EC330C1A62F8000018E4 1428 > X1 SCR10 RAM #68 DATAMOD DB7 6C3B0C1E62F9000018E4 1429 > X1 SCR10 SCR10,R #78 DATAMOD DB8 6C3B0C2262F9000018E4 1430 > X1 SCR10 SCR10,R #88 DATAMOD DB9 EC3B0C2662F9000018E4 1431 > X1 SCR10 SCR10,R #98 DATAMOD DBA EC330C2A62F8000018E4 1432 > X1 SCR10 RAM #A8 DATAMOD DBB 6C330C2E62F8000018E4 1433 > X1 SCR10 RAM #B8 DATAMOD DBC EC3B0C3262F9000018E4 1434 > X1 SCR10 SCR10,R #C8 DATAMOD DBD 6C3B0C3662F9000018E4 1435 > X1 SCR10 SCR10,R #D8 DATAMOD DBE 6C330C3A62F8000018E4 1436 > X1 SCR10 RAM #E8 DATAMOD DBF EC330C3E62F8000018E4 1437 > X1 SCR10 RAM #F8 DATAMOD 1438 > ENDBLOCK 1439 >>>>>>>>>>>>>>>>>>>>> 1441 >>>>>>>>>>>>>>>>>>>>> 1442 > BLOCK 16 DA0 6C330C0362F8000018E4 1443 >WRAX1MS3BLK X1 SCR10 RAM #0C DATAMOD DA1 EC3B0C0762F9000018E4 1444 > X1 SCR10 SCR10,R #1C DATAMOD DA2 EC3B0C0B62F9000018E4 1445 > X1 SCR10 SCR10,R #2C DATAMOD DA3 6C330C0F62F8000018E4 1446 > X1 SCR10 RAM #3C DATAMOD DA4 EC330C1362F8000018E4 1447 > X1 SCR10 RAM #4C DATAMOD DA5 6C3B0C1762F9000018E4 1448 > X1 SCR10 SCR10,R #5C DATAMOD DA6 6C3B0C1B62F9000018E4 1449 > X1 SCR10 SCR10,R #6C DATAMOD DA7 EC330C1F62F8000018E4 1450 > X1 SCR10 RAM #7C DATAMOD DA8 EC330C2362F8000018E4 1451 > X1 SCR10 RAM #8C DATAMOD DA9 6C3B0C2762F9000018E4 1452 > X1 SCR10 SCR10,R #9C DATAMOD DAA 6C3B0C2B62F9000018E4 1453 > X1 SCR10 SCR10,R #AC DATAMOD DAB EC330C2F62F8000018E4 1454 > X1 SCR10 RAM #BC DATAMOD DAC 6C330C3362F8000018E4 1455 > X1 SCR10 RAM #CC DATAMOD DAD EC3B0C3762F9000018E4 1456 > X1 SCR10 SCR10,R #DC DATAMOD DAE EC3B0C3B62F9000018E4 1457 > X1 SCR10 SCR10,R #EC DATAMOD DAF 6C330C3F62F8000018E4 1458 > X1 SCR10 RAM #FC DATAMOD 1459 > ENDBLOCK 1460 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 131 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1462 ***************************************************************************************************** 1463 * Write RAM using X2 and RAM OPCODE and RAM ADDRESS field of instruction * 1464 ***************************************************************************************************** 1465 8AC C8F31C006379000018AD 1466 WRALLX2 LIT SCR3 #0000 addr ptr=0 8AD 48731C006379000018AE 1467 LIT SCR1 #0000 index = 0 8AE 58D30F00E2F9FFFF18AF 1468 WRALLX2D SCR3 AND,X LIT SCR3 #FFFF exchange bytes 8AF 48311C00636D000018B0 1469 LIT INDX2 #0000 X2=0 8B0 C8F30C0062FC000018B1 1470 SCR3 RBIR RBIR#0=SCR3 bits 8:9 8B1 48311C00636D000118B2 1471 LIT INDX2 #0001 X2=1 8B2 48F30C0062FC000018B3 1472 SCR3 RBIR RBIR#1=SCR3 bits 8:9 8B3 48311C00636D000218B4 1473 LIT INDX2 #0002 X2=2 8B4 48F30C0062FC000018B5 1474 SCR3 RBIR RBIR#2=SCR3 bits 8:9 8B5 48311C00636D000318B6 1475 LIT INDX2 #0003 X2=3 8B6 C8F30C0062FC000018B7 1476 SCR3 RBIR RBIR#3=SCR3 bits 8:9 8B7 58D30F00E2F9FFFF18B8 1477 SCR3 AND,X LIT SCR3 #FFFF exchange bytes 8B8 48710C0062ED000018B9 1478 WRALLX2A SCR1 INDX2 set X2 8B9 48F3080072FF08BA5D90 1479 SCR3 *+1,P DB0 WRAX2LSBLK go do write 8BA 58D30F0072FF03FF18BD 1480 SCR3 AND LIT #03FF SKIP WRALLX2C done yet? 1481 >>>>>>>>>>>>>>>>>>>>> 1482 > EVEN 8BB 4FF31C00637908BB18BB 1482$>WSTE0061 LIT SCR1F * * ****** wasted ****** 8BC 58D30D8062F9000118E4 1483 > SCR3 ADD LIT SCR3 #0001 DATAMOD done,update data 8BD D8530D8062F9000118BE 1484 >WRALLX2C SCR1 ADD LIT SCR1 #0001 no, index + 1 1485 >>>>>>>>>>>>>>>>>>>>> 8BE D8530F0062F9000318BF 1486 SCR1 AND LIT SCR1 #0003 clr bits 2:15 1487 8BF 58D30F0072FF00FF18C0 1488 SCR3 AND LIT #00FF SKIP WRALLX2E need new RBIR's? 1489 >>>>>>>>>>>>>>>>>>>>> 1490 > EVEN 8C0 58D30D8062F9000118B8 1491 >WRALLX2E SCR3 ADD LIT SCR3 #0001 WRALLX2A no,addr+1,loop 8C1 D8D30D8062F9000118AE 1492 > SCR3 ADD LIT SCR3 #0001 WRALLX2D yes,addr+1,loop 1493 >>>>>>>>>>>>>>>>>>>>> 1494 1495 >>>>>>>>>>>>>>>>>>>>> 1496 > BLOCK 16 D90 48F3040072FF00001D80 1497 >WRAX2LSBLK SCR3 DB4 WRAX2MS0BLK SCR3 bits 2:3=0 D91 48F3040072FF00001D80 1498 > SCR3 DB4 WRAX2MS0BLK SCR3 bits 2:3=0 D92 48F3040072FF00001D80 1499 > SCR3 DB4 WRAX2MS0BLK SCR3 bits 2:3=0 D93 48F3040072FF00001D80 1500 > SCR3 DB4 WRAX2MS0BLK SCR3 bits 2:3=0 D94 48F3040072FF00001D70 1501 > SCR3 DB4 WRAX2MS1BLK SCR3 bits 2:3=1 D95 48F3040072FF00001D70 1502 > SCR3 DB4 WRAX2MS1BLK SCR3 bits 2:3=1 D96 48F3040072FF00001D70 1503 > SCR3 DB4 WRAX2MS1BLK SCR3 bits 2:3=1 D97 48F3040072FF00001D70 1504 > SCR3 DB4 WRAX2MS1BLK SCR3 bits 2:3=1 D98 C8F3040072FF00001D60 1505 > SCR3 DB4 WRAX2MS2BLK SCR3 bits 2:3=2 D99 C8F3040072FF00001D60 1506 > SCR3 DB4 WRAX2MS2BLK SCR3 bits 2:3=2 D9A C8F3040072FF00001D60 1507 > SCR3 DB4 WRAX2MS2BLK SCR3 bits 2:3=2 D9B C8F3040072FF00001D60 1508 > SCR3 DB4 WRAX2MS2BLK SCR3 bits 2:3=2 D9C C8F3040072FF00001D50 1509 > SCR3 DB4 WRAX2MS3BLK SCR3 bits 2:3=3 D9D C8F3040072FF00001D50 1510 > SCR3 DB4 WRAX2MS3BLK SCR3 bits 2:3=3 D9E C8F3040072FF00001D50 1511 > SCR3 DB4 WRAX2MS3BLK SCR3 bits 2:3=3 D9F C8F3040072FF00001D50 1512 > SCR3 DB4 WRAX2MS3BLK SCR3 bits 2:3=3 1513 > ENDBLOCK 1514 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 132 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1516 >>>>>>>>>>>>>>>>>>>>> 1517 > BLOCK 16 D80 CC3B0C0062F9000018E4 1518 >WRAX2MS0BLK X2 SCR10 SCR10,R #00 DATAMOD D81 4C330C0462F8000018E4 1519 > X2 SCR10 RAM #10 DATAMOD D82 4C3B0C0862F9000018E4 1520 > X2 SCR10 SCR10,R #20 DATAMOD D83 CC3B0C0C62F9000018E4 1521 > X2 SCR10 SCR10,R #30 DATAMOD D84 4C330C1062F8000018E4 1522 > X2 SCR10 RAM #40 DATAMOD D85 CC330C1462F8000018E4 1523 > X2 SCR10 RAM #50 DATAMOD D86 CC330C1862F8000018E4 1524 > X2 SCR10 RAM #60 DATAMOD D87 4C3B0C1C62F9000018E4 1525 > X2 SCR10 SCR10,R #70 DATAMOD D88 4C3B0C2062F9000018E4 1526 > X2 SCR10 SCR10,R #80 DATAMOD D89 CC3B0C2462F9000018E4 1527 > X2 SCR10 SCR10,R #90 DATAMOD D8A CC3B0C2862F9000018E4 1528 > X2 SCR10 SCR10,R #A0 DATAMOD D8B 4C330C2C62F8000018E4 1529 > X2 SCR10 RAM #B0 DATAMOD D8C CC330C3062F8000018E4 1530 > X2 SCR10 RAM #C0 DATAMOD D8D 4C330C3462F8000018E4 1531 > X2 SCR10 RAM #D0 DATAMOD D8E 4C330C3862F8000018E4 1532 > X2 SCR10 RAM #E0 DATAMOD D8F CC3B0C3C62F9000018E4 1533 > X2 SCR10 SCR10,R #F0 DATAMOD 1534 > ENDBLOCK 1535 >>>>>>>>>>>>>>>>>>>>> 1537 >>>>>>>>>>>>>>>>>>>>> 1538 > BLOCK 16 D70 4C330C0162F8000018E4 1539 >WRAX2MS1BLK X2 SCR10 RAM #04 DATAMOD D71 CC3B0C0562F9000018E4 1540 > X2 SCR10 SCR10,R #14 DATAMOD D72 CC3B0C0962F9000018E4 1541 > X2 SCR10 SCR10,R #24 DATAMOD D73 4C3B0C0D62F9000018E4 1542 > X2 SCR10 SCR10,R #34 DATAMOD D74 CC330C1162F8000018E4 1543 > X2 SCR10 RAM #44 DATAMOD D75 4C330C1562F8000018E4 1544 > X2 SCR10 RAM #54 DATAMOD D76 4C330C1962F8000018E4 1545 > X2 SCR10 RAM #64 DATAMOD D77 CC3B0C1D62F9000018E4 1546 > X2 SCR10 SCR10,R #74 DATAMOD D78 CC3B0C2162F9000018E4 1547 > X2 SCR10 SCR10,R #84 DATAMOD D79 4C3B0C2562F9000018E4 1548 > X2 SCR10 SCR10,R #94 DATAMOD D7A 4C3B0C2962F9000018E4 1549 > X2 SCR10 SCR10,R #A4 DATAMOD D7B CC330C2D62F8000018E4 1550 > X2 SCR10 RAM #B4 DATAMOD D7C 4C330C3162F8000018E4 1551 > X2 SCR10 RAM #C4 DATAMOD D7D CC3B0C3562F9000018E4 1552 > X2 SCR10 SCR10,R #D4 DATAMOD D7E CC330C3962F8000018E4 1553 > X2 SCR10 RAM #E4 DATAMOD D7F 4C3B0C3D62F9000018E4 1554 > X2 SCR10 SCR10,R #F4 DATAMOD 1555 > ENDBLOCK 1556 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 133 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- WRALL89 and RRALL89 Subroutines 1558 >>>>>>>>>>>>>>>>>>>>> 1559 > BLOCK 16 D60 4C3B0C0262F9000018E4 1560 >WRAX2MS2BLK X2 SCR10 SCR10,R #08 DATAMOD D61 CC330C0662F8000018E4 1561 > X2 SCR10 RAM #18 DATAMOD D62 CC3B0C0A62F9000018E4 1562 > X2 SCR10 SCR10,R #28 DATAMOD D63 4C3B0C0E62F9000018E4 1563 > X2 SCR10 SCR10,R #38 DATAMOD D64 CC330C1262F8000018E4 1564 > X2 SCR10 RAM #48 DATAMOD D65 4C330C1662F8000018E4 1565 > X2 SCR10 RAM #58 DATAMOD D66 4C330C1A62F8000018E4 1566 > X2 SCR10 RAM #68 DATAMOD D67 CC3B0C1E62F9000018E4 1567 > X2 SCR10 SCR10,R #78 DATAMOD D68 CC330C2262F8000018E4 1568 > X2 SCR10 RAM #88 DATAMOD D69 4C3B0C2662F9000018E4 1569 > X2 SCR10 SCR10,R #98 DATAMOD D6A 4C3B0C2A62F9000018E4 1570 > X2 SCR10 SCR10,R #A8 DATAMOD D6B CC330C2E62F8000018E4 1571 > X2 SCR10 RAM #B8 DATAMOD D6C 4C330C3262F8000018E4 1572 > X2 SCR10 RAM #C8 DATAMOD D6D CC3B0C3662F9000018E4 1573 > X2 SCR10 SCR10,R #D8 DATAMOD D6E CC330C3A62F8000018E4 1574 > X2 SCR10 RAM #E8 DATAMOD D6F 4C3B0C3E62F9000018E4 1575 > X2 SCR10 SCR10,R #F8 DATAMOD 1576 > ENDBLOCK 1577 >>>>>>>>>>>>>>>>>>>>> 1579 >>>>>>>>>>>>>>>>>>>>> 1580 > BLOCK 16 D50 CC3B0C0362F9000018E4 1581 >WRAX2MS3BLK X2 SCR10 SCR10,R #0C DATAMOD D51 4C330C0762F8000018E4 1582 > X2 SCR10 RAM #1C DATAMOD D52 4C3B0C0B62F9000018E4 1583 > X2 SCR10 SCR10,R #2C DATAMOD D53 CC3B0C0F62F9000018E4 1584 > X2 SCR10 SCR10,R #3C DATAMOD D54 4C330C1362F8000018E4 1585 > X2 SCR10 RAM #4C DATAMOD D55 CC330C1762F8000018E4 1586 > X2 SCR10 RAM #5C DATAMOD D56 CC3B0C1B62F9000018E4 1587 > X2 SCR10 SCR10,R #6C DATAMOD D57 4C3B0C1F62F9000018E4 1588 > X2 SCR10 SCR10,R #7C DATAMOD D58 4C3B0C2362F9000018E4 1589 > X2 SCR10 SCR10,R #8C DATAMOD D59 CC3B0C2762F9000018E4 1590 > X2 SCR10 SCR10,R #9C DATAMOD D5A CC3B0C2B62F9000018E4 1591 > X2 SCR10 SCR10,R #AC DATAMOD D5B 4C330C2F62F8000018E4 1592 > X2 SCR10 RAM #BC DATAMOD D5C CC330C3362F8000018E4 1593 > X2 SCR10 RAM #CC DATAMOD D5D 4C330C3762F8000018E4 1594 > X2 SCR10 RAM #DC DATAMOD D5E 4C3B0C3B62F9000018E4 1595 > X2 SCR10 SCR10,R #EC DATAMOD D5F CC330C3F62F8000018E4 1596 > X2 SCR10 RAM #FC DATAMOD 1597 > ENDBLOCK 1598 >>>>>>>>>>>>>>>>>>>>> 1599 TITLE.MAC PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM address field 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 134 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1600 ***************************************************************************************************** 1601 * * 1602 * This subroutine is used by RAM89TEST, the ram address test that * 1603 * uses ram address bits 8:9. This subroutine does the read using X1 * 1604 * (i.e. ram address bits 8:9 come from the ram address register). * 1605 * This subroutine reads and checks address 0-3FF. In case of a bad * 1606 * read, SCR10 contains expected data, SCR1 contains the index value * 1607 * used, SCR3 contains the address. * 1608 * * 1609 * SCR10 should be initialized to the first data value before calling * 1610 * these subroutines. * 1611 * SCR2 should be initialized to the correct value before calling * 1612 * these subroutines. * 1613 * * 1614 ***************************************************************************************************** 1615 8C2 48F31C006379000018C3 1616 RRALLX1 LIT SCR3 #0000 addr ptr=0 8C3 48731C006379000018C4 1617 LIT SCR1 #0000 index = 0 8C4 58D00F0062F4030018C5 1618 RRALLX1A SCR3 AND LIT RADR #0300 set RADR bits 8:9 8C5 C8710C0062F3000018C6 1619 SCR1 INDX1 set X1 8C6 C8F3080072FF08C75D40 1620 SCR3 *+1,P DB0 RRAX1LSBLOCK go do read 8C7 58D30F0072FF03FF18C9 1621 SCR3 AND LIT #03FF SKIP RRALLX1B done yet? 1622 1623 >>>>>>>>>>>>>>>>>>>>> 1624 > EVEN 8C8 58D30D8062F9000118E4 1625 > SCR3 ADD LIT SCR3 #0001 DATAMOD done, update data 8C9 58D30D8062F9000118CA 1626 >RRALLX1B SCR3 ADD LIT SCR3 #0001 increment addr 1627 >>>>>>>>>>>>>>>>>>>>> 8CA 58530D8062F9000118CB 1628 SCR1 ADD LIT SCR1 #0001 index + 1 8CB D8530F0062F9000318C4 1629 SCR1 AND LIT SCR1 #0003 RRALLX1A clr bits 2:15,loop 1630 1631 >>>>>>>>>>>>>>>>>>>>> 1632 > BLOCK 16 D40 C8F3040072FF00001D30 1633 >RRAX1LSBLOCK SCR3 DB4 RRAX1MS0BLOCK SCR3 bits 2:3 = 0 D41 C8F3040072FF00001D30 1634 > SCR3 DB4 RRAX1MS0BLOCK SCR3 bits 2:3 = 0 D42 C8F3040072FF00001D30 1635 > SCR3 DB4 RRAX1MS0BLOCK SCR3 bits 2:3 = 0 D43 C8F3040072FF00001D30 1636 > SCR3 DB4 RRAX1MS0BLOCK SCR3 bits 2:3 = 0 D44 48F3040072FF00001D20 1637 > SCR3 DB4 RRAX1MS1BLOCK SCR3 bits 2:3 = 1 D45 48F3040072FF00001D20 1638 > SCR3 DB4 RRAX1MS1BLOCK SCR3 bits 2:3 = 1 D46 48F3040072FF00001D20 1639 > SCR3 DB4 RRAX1MS1BLOCK SCR3 bits 2:3 = 1 D47 48F3040072FF00001D20 1640 > SCR3 DB4 RRAX1MS1BLOCK SCR3 bits 2:3 = 1 D48 48F3040072FF00001D10 1641 > SCR3 DB4 RRAX1MS2BLOCK SCR3 bits 2:3 = 2 D49 48F3040072FF00001D10 1642 > SCR3 DB4 RRAX1MS2BLOCK SCR3 bits 2:3 = 2 D4A 48F3040072FF00001D10 1643 > SCR3 DB4 RRAX1MS2BLOCK SCR3 bits 2:3 = 2 D4B 48F3040072FF00001D10 1644 > SCR3 DB4 RRAX1MS2BLOCK SCR3 bits 2:3 = 2 D4C C8F3040072FF00001D00 1645 > SCR3 DB4 RRAX1MS3BLOCK SCR3 bits 2:3 = 3 D4D C8F3040072FF00001D00 1646 > SCR3 DB4 RRAX1MS3BLOCK SCR3 bits 2:3 = 3 D4E C8F3040072FF00001D00 1647 > SCR3 DB4 RRAX1MS3BLOCK SCR3 bits 2:3 = 3 D4F C8F3040072FF00001D00 1648 > SCR3 DB4 RRAX1MS3BLOCK SCR3 bits 2:3 = 3 1649 > ENDBLOCK 1650 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 135 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1652 >>>>>>>>>>>>>>>>>>>>> 1653 > BLOCK 16 D30 FC130E0072DF000018CD 1654 >RRAX1MS0BLOCK X1 SCR10 XOR RAM #00 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 D31 7C130E0472DF000018CD 1655 > X1 SCR10 XOR RAM #10 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 D32 7C130E0872DF000018CD 1656 > X1 SCR10 XOR RAM #20 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 D33 FC130E0C72DF000018CD 1657 > X1 SCR10 XOR RAM #30 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 D34 7C130E1072DF000018CD 1658 > X1 SCR10 XOR RAM #40 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 D35 FC130E1472DF000018CD 1659 > X1 SCR10 XOR RAM #50 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 D36 FC130E1872DF000018CD 1660 > X1 SCR10 XOR RAM #60 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 D37 7C130E1C72DF000018CD 1661 > X1 SCR10 XOR RAM #70 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 D38 7C130E2072DF000018CD 1662 > X1 SCR10 XOR RAM #80 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 D39 FC130E2472DF000018CD 1663 > X1 SCR10 XOR RAM #90 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 D3A FC130E2872DF000018CD 1664 > X1 SCR10 XOR RAM #A0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A D3B 7C130E2C72DF000018CD 1665 > X1 SCR10 XOR RAM #B0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B D3C FC130E3072DF000018CD 1666 > X1 SCR10 XOR RAM #C0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C D3D 7C130E3472DF000018CD 1667 > X1 SCR10 XOR RAM #D0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D D3E 7C130E3872DF000018CD 1668 > X1 SCR10 XOR RAM #E0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E D3F FC130E3C72DF000018CD 1669 > X1 SCR10 XOR RAM #F0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1670 > ENDBLOCK 1671 >>>>>>>>>>>>>>>>>>>>> 1673 >>>>>>>>>>>>>>>>>>>>> 1674 > BLOCK 16 D20 7C130E0172DF000018CD 1675 >RRAX1MS1BLOCK X1 SCR10 XOR RAM #04 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 D21 FC130E0572DF000018CD 1676 > X1 SCR10 XOR RAM #14 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 D22 FC130E0972DF000018CD 1677 > X1 SCR10 XOR RAM #24 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 D23 7C130E0D72DF000018CD 1678 > X1 SCR10 XOR RAM #34 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 D24 FC130E1172DF000018CD 1679 > X1 SCR10 XOR RAM #44 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 D25 7C130E1572DF000018CD 1680 > X1 SCR10 XOR RAM #54 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 D26 7C130E1972DF000018CD 1681 > X1 SCR10 XOR RAM #64 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 D27 FC130E1D72DF000018CD 1682 > X1 SCR10 XOR RAM #74 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 D28 FC130E2172DF000018CD 1683 > X1 SCR10 XOR RAM #84 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 D29 7C130E2572DF000018CD 1684 > X1 SCR10 XOR RAM #94 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 D2A 7C130E2972DF000018CD 1685 > X1 SCR10 XOR RAM #A4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A D2B FC130E2D72DF000018CD 1686 > X1 SCR10 XOR RAM #B4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B D2C 7C130E3172DF000018CD 1687 > X1 SCR10 XOR RAM #C4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C D2D FC130E3572DF000018CD 1688 > X1 SCR10 XOR RAM #D4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D D2E FC130E3972DF000018CD 1689 > X1 SCR10 XOR RAM #E4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E D2F 7C130E3D72DF000018CD 1690 > X1 SCR10 XOR RAM #F4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1691 > ENDBLOCK 1692 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 136 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1694 >>>>>>>>>>>>>>>>>>>>> 1695 > BLOCK 16 D10 7C130E0272DF000018CD 1696 >RRAX1MS2BLOCK X1 SCR10 XOR RAM #08 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 D11 FC130E0672DF000018CD 1697 > X1 SCR10 XOR RAM #18 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 D12 FC130E0A72DF000018CD 1698 > X1 SCR10 XOR RAM #28 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 D13 7C130E0E72DF000018CD 1699 > X1 SCR10 XOR RAM #38 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 D14 FC130E1272DF000018CD 1700 > X1 SCR10 XOR RAM #48 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 D15 7C130E1672DF000018CD 1701 > X1 SCR10 XOR RAM #58 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 D16 7C130E1A72DF000018CD 1702 > X1 SCR10 XOR RAM #68 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 D17 FC130E1E72DF000018CD 1703 > X1 SCR10 XOR RAM #78 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 D18 FC130E2272DF000018CD 1704 > X1 SCR10 XOR RAM #88 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 D19 7C130E2672DF000018CD 1705 > X1 SCR10 XOR RAM #98 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 D1A 7C130E2A72DF000018CD 1706 > X1 SCR10 XOR RAM #A8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A D1B FC130E2E72DF000018CD 1707 > X1 SCR10 XOR RAM #B8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B D1C 7C130E3272DF000018CD 1708 > X1 SCR10 XOR RAM #C8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C D1D FC130E3672DF000018CD 1709 > X1 SCR10 XOR RAM #D8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D D1E FC130E3A72DF000018CD 1710 > X1 SCR10 XOR RAM #E8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E D1F 7C130E3E72DF000018CD 1711 > X1 SCR10 XOR RAM #F8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1712 > ENDBLOCK 1713 >>>>>>>>>>>>>>>>>>>>> 1715 >>>>>>>>>>>>>>>>>>>>> 1716 > BLOCK 16 D00 FC130E0372DF000018CD 1717 >RRAX1MS3BLOCK X1 SCR10 XOR RAM #0C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 D01 7C130E0772DF000018CD 1718 > X1 SCR10 XOR RAM #1C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 D02 7C130E0B72DF000018CD 1719 > X1 SCR10 XOR RAM #2C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 D03 FC130E0F72DF000018CD 1720 > X1 SCR10 XOR RAM #3C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 D04 7C130E1372DF000018CD 1721 > X1 SCR10 XOR RAM #4C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 D05 FC130E1772DF000018CD 1722 > X1 SCR10 XOR RAM #5C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 D06 FC130E1B72DF000018CD 1723 > X1 SCR10 XOR RAM #6C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 D07 7C130E1F72DF000018CD 1724 > X1 SCR10 XOR RAM #7C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 D08 7C130E2372DF000018CD 1725 > X1 SCR10 XOR RAM #8C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 D09 FC130E2772DF000018CD 1726 > X1 SCR10 XOR RAM #9C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 D0A FC130E2B72DF000018CD 1727 > X1 SCR10 XOR RAM #AC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A D0B 7C130E2F72DF000018CD 1728 > X1 SCR10 XOR RAM #BC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B D0C FC130E3372DF000018CD 1729 > X1 SCR10 XOR RAM #CC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C D0D 7C130E3772DF000018CD 1730 > X1 SCR10 XOR RAM #DC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D D0E 7C130E3B72DF000018CD 1731 > X1 SCR10 XOR RAM #EC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E D0F FC130E3F72DF000018CD 1732 > X1 SCR10 XOR RAM #FC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1733 > ENDBLOCK 1734 >>>>>>>>>>>>>>>>>>>>> 1736 EVEN 1737 >>>>>>>>>>>>>>>>>>>>> 8CC D8311C00633F000018E4 1738 > DATAMOD RAM ok,next data,rtn 8CD 48331C00637908CD1C54 1739 >RRAMBAD LIT SCR0 * ERRTN RAM bad 1740 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 137 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1742 ***************************************************************************************************** 1743 * * 1744 * This subroutine is used by RAM89TEST, the ram address test that * 1745 * uses ram address bits 8:9. This subroutine does the read using X2 * 1746 * (i.e. ram address bits 8:9 come from the ram bank index register * 1747 * pointed to by X2). This subroutine reads and checks addresses 0-3FF. * 1748 * In case of a bad read, SCR10 contains the expected data, SCR1 * 1749 * contains the index value used, and SCR3 contains the address. * 1750 * * 1751 * SCR10 should be initialized to the first data value before calling * 1752 * these subroutines. * 1753 * SCR2 should be initialized to the correct value before calling * 1754 * these subroutines. * 1755 * * 1756 * This subroutine uses the same 2 line skip block (labeled * 1757 * RRAMBAD) as the last subroutine. * 1758 * * 1759 ***************************************************************************************************** 1760 8CE 48F31C006379000018CF 1761 RRALLX2 LIT SCR3 #0000 addr ptr=0 8CF 48731C006379000018D0 1762 LIT SCR1 #0000 index = 0 8D0 58D30F00E2F9FFFF18D1 1763 RRALLX2D SCR3 AND,X LIT SCR3 #FFFF exchange bytes 8D1 C8311C00636D000018D2 1764 LIT INDX2 #0000 X2=0 8D2 48F30C0062FC000018D3 1765 SCR3 RBIR RBIR#0=SCR3 bits 8:9 8D3 48311C00636D000118D4 1766 LIT INDX2 #0001 X2=1 8D4 48F30C0062FC000018D5 1767 SCR3 RBIR RBIR#1=SCR3 bits 8:9 8D5 C8311C00636D000218D6 1768 LIT INDX2 #0002 X2=2 8D6 C8F30C0062FC000018D7 1769 SCR3 RBIR RBIR#2=SCR3 bits 8:9 8D7 C8311C00636D000318D8 1770 LIT INDX2 #0003 X2=3 8D8 48F30C0062FC000018D9 1771 SCR3 RBIR RBIR#3=SCR3 bits 8:9 8D9 D8D30F00E2F9FFFF18DA 1772 SCR3 AND,X LIT SCR3 #FFFF exchange bytes 8DA C8710C0062ED000018DB 1773 RRALLX2A SCR1 INDX2 set X2 8DB C8F3080072FF08DC5CF0 1774 SCR3 *+1,P DB0 RRAX2LSBLOCK go do read 8DC D8D30F0072FF03FF18DF 1775 SCR3 AND LIT #03FF SKIP RRALLX2B done yet? 1776 1777 >>>>>>>>>>>>>>>>>>>>> 1778 > EVEN 8DD 4FF31C00637908DD18DD 1778$>WSTE0062 LIT SCR1F * * ****** wasted ****** 8DE 58D30D8062F9000118E4 1779 > SCR3 ADD LIT SCR3 #0001 DATAMOD done, update data 8DF 58530D8062F9000118E0 1780 >RRALLX2B SCR1 ADD LIT SCR1 #0001 no,index + 1 1781 >>>>>>>>>>>>>>>>>>>>> 8E0 58530F0062F9000318E1 1782 SCR1 AND LIT SCR1 #0003 clr bits 2:15 1783 8E1 58D30F0072FF00FF18E2 1784 SCR3 AND LIT #00FF SKIP RRALLX2E need new RBIR? 1785 >>>>>>>>>>>>>>>>>>>>> 1786 > EVEN 8E2 D8D30D8062F9000118DA 1787 >RRALLX2E SCR3 ADD LIT SCR3 #0001 RRALLX2A no,addr+1,loop 8E3 D8D30D8062F9000118D0 1788 > SCR3 ADD LIT SCR3 #0001 RRALLX2D yes,addr+1,loop 1789 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 138 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1791 >>>>>>>>>>>>>>>>>>>>> 1792 > BLOCK 16 CF0 C8F3040072FF00001CE0 1793 >RRAX2LSBLOCK SCR3 DB4 RRAX2MS0BLOCK SCR3 bits 2:3 = 0 CF1 C8F3040072FF00001CE0 1794 > SCR3 DB4 RRAX2MS0BLOCK SCR3 bits 2:3 = 0 CF2 C8F3040072FF00001CE0 1795 > SCR3 DB4 RRAX2MS0BLOCK SCR3 bits 2:3 = 0 CF3 C8F3040072FF00001CE0 1796 > SCR3 DB4 RRAX2MS0BLOCK SCR3 bits 2:3 = 0 CF4 C8F3040072FF00001CD0 1797 > SCR3 DB4 RRAX2MS1BLOCK SCR3 bits 2:3 = 1 CF5 C8F3040072FF00001CD0 1798 > SCR3 DB4 RRAX2MS1BLOCK SCR3 bits 2:3 = 1 CF6 C8F3040072FF00001CD0 1799 > SCR3 DB4 RRAX2MS1BLOCK SCR3 bits 2:3 = 1 CF7 C8F3040072FF00001CD0 1800 > SCR3 DB4 RRAX2MS1BLOCK SCR3 bits 2:3 = 1 CF8 48F3040072FF00001CC0 1801 > SCR3 DB4 RRAX2MS2BLOCK SCR3 bits 2:3 = 2 CF9 48F3040072FF00001CC0 1802 > SCR3 DB4 RRAX2MS2BLOCK SCR3 bits 2:3 = 2 CFA 48F3040072FF00001CC0 1803 > SCR3 DB4 RRAX2MS2BLOCK SCR3 bits 2:3 = 2 CFB 48F3040072FF00001CC0 1804 > SCR3 DB4 RRAX2MS2BLOCK SCR3 bits 2:3 = 2 CFC C8F3040072FF00001CB0 1805 > SCR3 DB4 RRAX2MS3BLOCK SCR3 bits 2:3 = 3 CFD C8F3040072FF00001CB0 1806 > SCR3 DB4 RRAX2MS3BLOCK SCR3 bits 2:3 = 3 CFE C8F3040072FF00001CB0 1807 > SCR3 DB4 RRAX2MS3BLOCK SCR3 bits 2:3 = 3 CFF C8F3040072FF00001CB0 1808 > SCR3 DB4 RRAX2MS3BLOCK SCR3 bits 2:3 = 3 1809 > ENDBLOCK 1810 >>>>>>>>>>>>>>>>>>>>> 1812 >>>>>>>>>>>>>>>>>>>>> 1813 > BLOCK 16 CE0 5C130E0072DF000018CD 1814 >RRAX2MS0BLOCK X2 SCR10 XOR RAM #00 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 CE1 DC130E0472DF000018CD 1815 > X2 SCR10 XOR RAM #10 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 CE2 DC130E0872DF000018CD 1816 > X2 SCR10 XOR RAM #20 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 CE3 5C130E0C72DF000018CD 1817 > X2 SCR10 XOR RAM #30 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 CE4 DC130E1072DF000018CD 1818 > X2 SCR10 XOR RAM #40 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 CE5 5C130E1472DF000018CD 1819 > X2 SCR10 XOR RAM #50 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 CE6 5C130E1872DF000018CD 1820 > X2 SCR10 XOR RAM #60 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 CE7 DC130E1C72DF000018CD 1821 > X2 SCR10 XOR RAM #70 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 CE8 DC130E2072DF000018CD 1822 > X2 SCR10 XOR RAM #80 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 CE9 5C130E2472DF000018CD 1823 > X2 SCR10 XOR RAM #90 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 CEA 5C130E2872DF000018CD 1824 > X2 SCR10 XOR RAM #A0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A CEB DC130E2C72DF000018CD 1825 > X2 SCR10 XOR RAM #B0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B CEC 5C130E3072DF000018CD 1826 > X2 SCR10 XOR RAM #C0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C CED DC130E3472DF000018CD 1827 > X2 SCR10 XOR RAM #D0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D CEE DC130E3872DF000018CD 1828 > X2 SCR10 XOR RAM #E0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E CEF 5C130E3C72DF000018CD 1829 > X2 SCR10 XOR RAM #F0 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1830 > ENDBLOCK 1831 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 139 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1833 >>>>>>>>>>>>>>>>>>>>> 1834 > BLOCK 16 CD0 DC130E0172DF000018CD 1835 >RRAX2MS1BLOCK X2 SCR10 XOR RAM #04 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 CD1 5C130E0572DF000018CD 1836 > X2 SCR10 XOR RAM #14 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 CD2 5C130E0972DF000018CD 1837 > X2 SCR10 XOR RAM #24 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 CD3 DC130E0D72DF000018CD 1838 > X2 SCR10 XOR RAM #34 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 CD4 5C130E1172DF000018CD 1839 > X2 SCR10 XOR RAM #44 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 CD5 DC130E1572DF000018CD 1840 > X2 SCR10 XOR RAM #54 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 CD6 DC130E1972DF000018CD 1841 > X2 SCR10 XOR RAM #64 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 CD7 5C130E1D72DF000018CD 1842 > X2 SCR10 XOR RAM #74 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 CD8 5C130E2172DF000018CD 1843 > X2 SCR10 XOR RAM #84 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 CD9 DC130E2572DF000018CD 1844 > X2 SCR10 XOR RAM #94 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 CDA DC130E2972DF000018CD 1845 > X2 SCR10 XOR RAM #A4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A CDB 5C130E2D72DF000018CD 1846 > X2 SCR10 XOR RAM #B4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B CDC DC130E3172DF000018CD 1847 > X2 SCR10 XOR RAM #C4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C CDD 5C130E3572DF000018CD 1848 > X2 SCR10 XOR RAM #D4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D CDE 5C130E3972DF000018CD 1849 > X2 SCR10 XOR RAM #E4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E CDF DC130E3D72DF000018CD 1850 > X2 SCR10 XOR RAM #F4 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1851 > ENDBLOCK 1852 >>>>>>>>>>>>>>>>>>>>> 1854 >>>>>>>>>>>>>>>>>>>>> 1855 > BLOCK 16 CC0 DC130E0272DF000018CD 1856 >RRAX2MS2BLOCK X2 SCR10 XOR RAM #08 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 CC1 5C130E0672DF000018CD 1857 > X2 SCR10 XOR RAM #18 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 CC2 5C130E0A72DF000018CD 1858 > X2 SCR10 XOR RAM #28 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 CC3 DC130E0E72DF000018CD 1859 > X2 SCR10 XOR RAM #38 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 CC4 5C130E1272DF000018CD 1860 > X2 SCR10 XOR RAM #48 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 CC5 DC130E1672DF000018CD 1861 > X2 SCR10 XOR RAM #58 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 CC6 DC130E1A72DF000018CD 1862 > X2 SCR10 XOR RAM #68 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 CC7 5C130E1E72DF000018CD 1863 > X2 SCR10 XOR RAM #78 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 CC8 5C130E2272DF000018CD 1864 > X2 SCR10 XOR RAM #88 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 CC9 DC130E2672DF000018CD 1865 > X2 SCR10 XOR RAM #98 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 CCA DC130E2A72DF000018CD 1866 > X2 SCR10 XOR RAM #A8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A CCB 5C130E2E72DF000018CD 1867 > X2 SCR10 XOR RAM #B8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B CCC DC130E3272DF000018CD 1868 > X2 SCR10 XOR RAM #C8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C CCD 5C130E3672DF000018CD 1869 > X2 SCR10 XOR RAM #D8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D CCE 5C130E3A72DF000018CD 1870 > X2 SCR10 XOR RAM #E8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E CCF DC130E3E72DF000018CD 1871 > X2 SCR10 XOR RAM #F8 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1872 > ENDBLOCK 1873 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 140 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to Read and Check RAM with RAM 1875 >>>>>>>>>>>>>>>>>>>>> 1876 > BLOCK 16 CB0 5C130E0372DF000018CD 1877 >RRAX2MS3BLOCK X2 SCR10 XOR RAM #0C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=0 CB1 DC130E0772DF000018CD 1878 > X2 SCR10 XOR RAM #1C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=1 CB2 DC130E0B72DF000018CD 1879 > X2 SCR10 XOR RAM #2C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=2 CB3 5C130E0F72DF000018CD 1880 > X2 SCR10 XOR RAM #3C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=3 CB4 DC130E1372DF000018CD 1881 > X2 SCR10 XOR RAM #4C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=4 CB5 5C130E1772DF000018CD 1882 > X2 SCR10 XOR RAM #5C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=5 CB6 5C130E1B72DF000018CD 1883 > X2 SCR10 XOR RAM #6C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=6 CB7 DC130E1F72DF000018CD 1884 > X2 SCR10 XOR RAM #7C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=7 CB8 DC130E2372DF000018CD 1885 > X2 SCR10 XOR RAM #8C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=8 CB9 5C130E2772DF000018CD 1886 > X2 SCR10 XOR RAM #9C 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=9 CBA 5C130E2B72DF000018CD 1887 > X2 SCR10 XOR RAM #AC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=A CBB DC130E2F72DF000018CD 1888 > X2 SCR10 XOR RAM #BC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=B CBC 5C130E3372DF000018CD 1889 > X2 SCR10 XOR RAM #CC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=C CBD DC130E3772DF000018CD 1890 > X2 SCR10 XOR RAM #DC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=D CBE DC130E3B72DF000018CD 1891 > X2 SCR10 XOR RAM #EC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=E CBF 5C130E3F72DF000018CD 1892 > X2 SCR10 XOR RAM #FC 0 SKIP RRAMBAD RAM ok?,SCR3<4:7>=F 1893 > ENDBLOCK 1894 >>>>>>>>>>>>>>>>>>>>> 1895 1896 1897 TITLE.MAC PPU5 SELFTEST -- The DATAMOD Subroutine 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 141 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- The DATAMOD Subroutine 1898 ***************************************************************************************************** 1899 * * 1900 * This DATAMOD subroutine is similar to but different from the * 1901 * DATAMOD subroutine is DIAGNOSTIC.HRDPP5:SECTION5.SOURCE. This is * 1902 * actually a modified copy of that subroutine. * 1903 * * 1904 * This is the infamous DATAMOD subroutine. It picks a data value * 1905 * to put into SCR10 based on the value in SCR2. The test type is in * 1906 * SCR2 bits 4:7. SCR2 bits 0:3 are used as an internal counter for * 1907 * floating ones and zeros patterns. If the user wishes, he can * 1908 * initialize SCR2 bits 0:3 to start the floating ones or zeros * 1909 * patterns in different places. * 1910 * * 1911 * SCR2 BITS 6:7 Test Type * 1912 * 0 Floating 1 pattern * 1913 * 1 Floating 0 pattern * 1914 * 2 SCR10 = SCR10 + 1 for address test * 1915 * 3 SCR10 = NOT(1 + NOT SCR10) for complement address test * 1916 * * 1917 * There is a convenient constant (namely DATAMODIOR) that can be * 1918 * used to set SCR2 bits 4:5 correctly for the indexed jump on bits * 1919 * 4:7. It is assumed that the calling routine sets SCR2 correctly * 1920 * before calling this subroutine. * 1921 * * 1922 * Tests 2 and 3 are used by RAM89TEST that does use ram address bits 8:9. * 1923 * * 1924 ***************************************************************************************************** 1925 8E4 C8B3040072FF00001DF4 1926 DATAMOD SCR2 DB4 DATAMODTBL branch to test type 1927 1928 >>>>>>>>>>>>>>>>>>>>> 1929 > BLOCK 4,DATAMODIOR DF4 C8B3080072FF00001CA0 1930 >DATAMODTBL SCR2 DB0 DATAMOD1S floating ones pattern DF5 C8B3080072FF00001C90 1931 > SCR2 DB0 DATAMOD0S floating zero pattern DF6 DC130D8062F900019EF1 1932 > SCR10 ADD LIT SCR10 #0001 POP STERR SCR10 + 1 DF7 DC130E0062F9FFFF18E7 1933 > SCR10 XOR LIT SCR10 #FFFF DATAMOD3 compl addr test 1934 > ENDBLOCK 1935 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 142 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- The DATAMOD Subroutine 1937 >>>>>>>>>>>>>>>>>>>>> 1938 > BLOCK 16 CA0 CC331C006379FFFE18E5 1939 >DATAMOD1S LIT SCR10 #FFFE DATAMODINC patt = FFFE CA1 CC331C006379FFFD18E5 1940 > LIT SCR10 #FFFD DATAMODINC patt = FFFD CA2 CC331C006379FFFB18E5 1941 > LIT SCR10 #FFFB DATAMODINC patt = FFFB CA3 CC331C006379FFF718E5 1942 > LIT SCR10 #FFF7 DATAMODINC patt = FFF7 CA4 CC331C006379FFEF18E5 1943 > LIT SCR10 #FFEF DATAMODINC patt = FFEF CA5 CC331C006379FFDF18E5 1944 > LIT SCR10 #FFDF DATAMODINC patt = FFDF CA6 CC331C006379FFBF18E5 1945 > LIT SCR10 #FFBF DATAMODINC patt = FFBF CA7 CC331C006379FF7F18E5 1946 > LIT SCR10 #FF7F DATAMODINC patt = FF7F CA8 CC331C006379FEFF18E5 1947 > LIT SCR10 #FEFF DATAMODINC patt = FEFF CA9 CC331C006379FDFF18E5 1948 > LIT SCR10 #FDFF DATAMODINC patt = FDFF CAA CC331C006379FBFF18E5 1949 > LIT SCR10 #FBFF DATAMODINC patt = FBFF CAB CC331C006379F7FF18E5 1950 > LIT SCR10 #F7FF DATAMODINC patt = F7FF CAC CC331C006379EFFF18E5 1951 > LIT SCR10 #EFFF DATAMODINC patt = EFFF CAD CC331C006379DFFF18E5 1952 > LIT SCR10 #DFFF DATAMODINC patt = DFFF CAE CC331C006379BFFF18E5 1953 > LIT SCR10 #BFFF DATAMODINC patt = BFFF CAF CC331C0063797FFF18E6 1954 > LIT SCR10 #7FFF DATAMODF patt = 7FFF 1955 > ENDBLOCK 1956 >>>>>>>>>>>>>>>>>>>>> 1957 1958 >>>>>>>>>>>>>>>>>>>>> 1959 > BLOCK 16 C90 CC331C006379000118E5 1960 >DATAMOD0S LIT SCR10 #0001 DATAMODINC patt = 0001 C91 CC331C006379000218E5 1961 > LIT SCR10 #0002 DATAMODINC patt = 0002 C92 CC331C006379000418E5 1962 > LIT SCR10 #0004 DATAMODINC patt = 0004 C93 CC331C006379000818E5 1963 > LIT SCR10 #0008 DATAMODINC patt = 0008 C94 CC331C006379001018E5 1964 > LIT SCR10 #0010 DATAMODINC patt = 0010 C95 CC331C006379002018E5 1965 > LIT SCR10 #0020 DATAMODINC patt = 0020 C96 CC331C006379004018E5 1966 > LIT SCR10 #0040 DATAMODINC patt = 0040 C97 CC331C006379008018E5 1967 > LIT SCR10 #0080 DATAMODINC patt = 0080 C98 CC331C006379010018E5 1968 > LIT SCR10 #0100 DATAMODINC patt = 0100 C99 CC331C006379020018E5 1969 > LIT SCR10 #0200 DATAMODINC patt = 0200 C9A CC331C006379040018E5 1970 > LIT SCR10 #0400 DATAMODINC patt = 0400 C9B CC331C006379080018E5 1971 > LIT SCR10 #0800 DATAMODINC patt = 0800 C9C CC331C006379100018E5 1972 > LIT SCR10 #1000 DATAMODINC patt = 1000 C9D CC331C006379200018E5 1973 > LIT SCR10 #2000 DATAMODINC patt = 2000 C9E CC331C006379400018E5 1974 > LIT SCR10 #4000 DATAMODINC patt = 4000 C9F CC331C006379800018E6 1975 > LIT SCR10 #8000 DATAMODF patt = 8000 1976 > ENDBLOCK 1977 >>>>>>>>>>>>>>>>>>>>> 1978 8E5 D8930D8062F900019EF1 1979 DATAMODINC SCR2 ADD LIT SCR2 #0001 POP STERR patrn # + 1 1980 8E6 58930F0062F9FFF09EF1 1981 DATAMODF SCR2 AND LIT SCR2 #FFF0 POP STERR patrn # + 1 1982 8E7 DC130D8062F9000118E8 1983 DATAMOD3 SCR10 ADD LIT SCR10 #0001 addr + 1 8E8 DC130E0062F9FFFF9EF1 1984 SCR10 XOR LIT SCR10 #FFFF POP STERR complement & return 1985 TITLE.MAC PPU5 SELFTEST -- Subroutines to read and check RAM using RAM address regis 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 143 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to read and check RAM using RAM 1986 ***************************************************************************************************** 1987 * * 1988 * This subroutine reads and checks the data using X1 and the ram address * 1989 * register. The DATAMOD subroutine is used for data to check. * 1990 * This subroutine reads and checks addresses 0-3FF. * 1991 * * 1992 * SCR10 should be initialized to the first data value before calling * 1993 * these subroutines. * 1994 * SCR2 should be initialized to the correct value before calling * 1995 * these subroutines. * 1996 * * 1997 ***************************************************************************************************** 1998 8E9 C8F31C006379000018EA 1999 RRALLRADRX1 LIT SCR3 #0000 addr ptr=0 8EA C8731C006379000018EB 2000 LIT SCR1 #0000 index = 0 8EB D8D00F0062F4FFFC18EC 2001 RRAX1A SCR3 AND LIT RADR #FFFC set RAM addr reg 8EC C8710C0062F3000018ED 2002 SCR1 INDX1 set X1 8ED 7C170E0072DF000018EF 2003 A,X1 SCR10 XOR RAM #00 #0000 SKIP RRAX1C read ok with X1? 2004 >>>>>>>>>>>>>>>>>>>>> 2005 > EVEN 8EE D8D30F0072FF03FF18F1 2006 > SCR3 AND LIT #03FF SKIP RRAX1B yes,done yet? 8EF 48331C00637908EF1C54 2007 >RRAX1C LIT SCR0 * ERRTN bad read with X1 2008 >* address of bad read in in SCR3, data contents in SCR10, index 2009 >* number used in SCR1. 2010 >>>>>>>>>>>>>>>>>>>>> 2011 2012 >>>>>>>>>>>>>>>>>>>>> 2013 > EVEN 8F0 58D30D8062F9000118E4 2014 > SCR3 ADD LIT SCR3 #0001 DATAMOD done, update data 8F1 D8D30D8062F9000118F2 2015 >RRAX1B SCR3 ADD LIT SCR3 #0001 increment address 2016 >>>>>>>>>>>>>>>>>>>>> 8F2 D8530D8062F9000118F3 2017 SCR1 ADD LIT SCR1 #0001 index + 1 8F3 D8530F0062F9000318F4 2018 SCR1 AND LIT SCR1 #0003 clr bits 2:15 8F4 58301C00633F08EB58E4 2019 RRAX1A,P DATAMOD next data,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 144 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to read and check RAM using RAM 2021 ***************************************************************************************************** 2022 * * 2023 * This subroutine reads and checks the data using X1 and the ram address * 2024 * register. The DATAMOD subroutine is used for data to check. * 2025 * This subroutine reads and checks addresses 0-3FF. * 2026 * * 2027 * SCR10 should be initialized to the first data value before calling * 2028 * these subroutines. * 2029 * SCR2 should be initialized to the correct value before calling * 2030 * these subroutines. * 2031 * * 2032 ***************************************************************************************************** 2033 8F5 48F31C006379000018F6 2034 RRALLRADRX2 LIT SCR3 #0000 addr ptr=0 8F6 48731C006379000018F7 2035 LIT SCR1 #0000 index = 0 8F7 D8D30F00E2F9FFFF18F8 2036 RRAX2A SCR3 AND,X LIT SCR3 #FFFF exchange bytes 8F8 C8311C00636D000018F9 2037 LIT INDX2 #0000 X2=0 8F9 C8F30C0062FC000018FA 2038 SCR3 RBIR RBIR#0=SCR3 bits 8:9 8FA C8311C00636D000118FB 2039 LIT INDX2 #0001 X2=1 8FB C8F30C0062FC000018FC 2040 SCR3 RBIR RBIR#1=SCR3 bits 8:9 8FC C8311C00636D000218FD 2041 LIT INDX2 #0002 X2=2 8FD 48F30C0062FC000018FE 2042 SCR3 RBIR RBIR#2=SCR3 bits 8:9 8FE C8311C00636D000318FF 2043 LIT INDX2 #0003 X2=3 8FF 48F30C0062FC00001900 2044 SCR3 RBIR RBIR#3=SCR3 bits 8:9 900 58D30F00E2F9FFFF1901 2045 SCR3 AND,X LIT SCR3 #FFFF exchange bytes 901 58D00F0062F400FC1902 2046 RRAX2B SCR3 AND LIT RADR #00FC set RADR bits 2:7 902 48710C0062ED00001903 2047 SCR1 INDX2 set X2 903 DC170E0072DF00001905 2048 A,X2 SCR10 XOR RAM #00 #0000 SKIP RRAX2C read ok with X2? 2049 >>>>>>>>>>>>>>>>>>>>> 2050 > EVEN 904 58D30F0072FF03FF1907 2051 > SCR3 AND LIT #03FF SKIP RRAX2F yes,done yet? 905 48331C00637909051C54 2052 >RRAX2C LIT SCR0 * ERRTN bad read with X2 2053 >* address of bad read in SCR3, correct data in SCR10, index value in SCR1 2054 >>>>>>>>>>>>>>>>>>>>> 2055 2056 >>>>>>>>>>>>>>>>>>>>> 2057 > EVEN 906 58D30D8062F9000118E4 2058 > SCR3 ADD LIT SCR3 #0001 DATAMOD done, update data 907 D8530D8062F900011908 2059 >RRAX2F SCR1 ADD LIT SCR1 #0001 no,index + 1 2060 >>>>>>>>>>>>>>>>>>>>> 908 D8530F0062F900031909 2061 SCR1 AND LIT SCR1 #0003 clear bits 2:15 2062 909 D8D30F0072FF00FF190A 2063 SCR3 AND LIT #00FF SKIP RRAX2D need new RBIR? 2064 >>>>>>>>>>>>>>>>>>>>> 2065 > EVEN 90A D8301C00633F0901590C 2066 >RRAX2D RRAX2B,P RRAX2E no,loop to RRAX2B 90B 58301C00633F08F7590C 2067 > RRAX2A,P RRAX2E yes,loop to RRAX2A 2068 >>>>>>>>>>>>>>>>>>>>> 2069 90C 58D30D8062F9000118E4 2070 RRAX2E SCR3 ADD LIT SCR3 #0001 DATAMOD addr+1,next data 2071 TITLE.MAC PPU5 SELFTEST -- Subroutines to write RAM using RAM address register 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 145 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to write RAM using RAM address 2072 ***************************************************************************************************** 2073 * * 2074 * The next subroutines are for writing RAM using the ram address * 2075 * registers for addresses from #0 to #3FF. They increment the ram * 2076 * address register, the index, and SCR3 by 1 each time. * 2077 * * 2078 * SCR10 should be initialized to the first data value before calling * 2079 * these subroutines. * 2080 * SCR2 should be initialized to the correct value before calling * 2081 * these subroutines. * 2082 * * 2083 ***************************************************************************************************** 2084 90D 48F31C0063790000190E 2085 WRALLRADRX1 LIT SCR3 #0000 addr ptr=0 90E 48731C0063790000190F 2086 LIT SCR1 #0000 index=0 90F 58D00F0062F4FFFC1910 2087 WRARX1LOOP SCR3 AND LIT RADR #FFFC set RADR 910 48710C0062F300001911 2088 SCR1 INDX1 set X1 911 6C370C0062F800001912 2089 A,X1 SCR10 RAM #00 write RAM 912 58D30F0072FF03FF1915 2090 SCR3 AND LIT #03FF SKIP WRARX1NOTDONE done yet? 2091 >>>>>>>>>>>>>>>>>>>>> 2092 > EVEN 913 4FF31C00637909131913 2092$>WSTE0063 LIT SCR1F * * ****** wasted ****** 914 58D30D8062F9000118E4 2093 > SCR3 ADD LIT SCR3 #0001 DATAMOD yes,update data 915 D8530D8062F900011916 2094 >WRARX1NOTDONE SCR1 ADD LIT SCR1 #0001 index + 1 2095 >>>>>>>>>>>>>>>>>>>>> 916 D8530F0062F900031917 2096 SCR1 AND LIT SCR1 #0003 clear bits 2:15 917 D8D30D8062F900011918 2097 SCR3 ADD LIT SCR3 #0001 addr + 1 918 D8301C00633F090F58E4 2098 WRARX1LOOP,P DATAMOD next data,loop 2099 919 48F31C0063790000191A 2100 WRALLRADRX1R LIT SCR3 #0000 addr ptr=0 91A 48731C0063790000191B 2101 LIT SCR1 #0000 index=0 91B 58D00F0062F4FFFC191C 2102 WRARX1RLOOP SCR3 AND LIT RADR #FFFC set RADR 91C 48710C0062F30000191D 2103 SCR1 INDX1 set X1 91D 6C3F0C0062F90000191E 2104 A,X1 SCR10 SCR10,R write RAM 91E D8D30F0072FF03FF1921 2105 SCR3 AND LIT #03FF SKIP WRARX1RNOTDONE done yet? 2106 >>>>>>>>>>>>>>>>>>>>> 2107 > EVEN 91F 4FF31C006379091F191F 2107$>WSTE0064 LIT SCR1F * * ****** wasted ****** 920 58D30D8062F9000118E4 2108 > SCR3 ADD LIT SCR3 #0001 DATAMOD yes,update data 921 58530D8062F900011922 2109 >WRARX1RNOTDONE SCR1 ADD LIT SCR1 #0001 index + 1 2110 >>>>>>>>>>>>>>>>>>>>> 922 58530F0062F900031923 2111 SCR1 AND LIT SCR1 #0003 clear bits 2:15 923 D8D30D8062F900011924 2112 SCR3 ADD LIT SCR3 #0001 addr + 1 924 D8301C00633F091B58E4 2113 WRARX1RLOOP,P DATAMOD next data,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 146 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to write RAM using RAM address 2115 ***************************************************************************************************** 2116 * * 2117 * These subroutines set the other ram bank index registers to * 2118 * other values before doing the writes. * 2119 * * 2120 * SCR10 should be initialized to the first data value before calling * 2121 * these subroutines. * 2122 * SCR2 should be initialized to the correct value before calling * 2123 * these subroutines. * 2124 * * 2125 ***************************************************************************************************** 2126 925 C8731C00637900001926 2127 WRALLRADRX2 LIT SCR1 #0000 index = 0 926 C8F31C00637900001927 2128 LIT SCR3 #0000 addr ptr = 0 927 D8D00F0062F400FC1928 2129 WRARX2LOOP SCR3 AND LIT RADR #00FC set RADR bits 2:7 928 58301C00633F0929593D 2130 *+1,P SETRBIR set RBIR'S 929 4C370C0062F80000192A 2131 A,X2 SCR10 RAM #00 write ram 92A D8D30F0072FF03FF192D 2132 SCR3 AND LIT #03FF SKIP WRARX2NOTDONE done yet? 2133 >>>>>>>>>>>>>>>>>>>>> 2134 > EVEN 92B 4FF31C006379092B192B 2134$>WSTE0065 LIT SCR1F * * ****** wasted ****** 92C 58D30D8062F9000118E4 2135 > SCR3 ADD LIT SCR3 #0001 DATAMOD yes,update data 92D 58530D8062F90001192E 2136 >WRARX2NOTDONE SCR1 ADD LIT SCR1 #0001 index + 1 2137 >>>>>>>>>>>>>>>>>>>>> 92E 58530F0062F90003192F 2138 SCR1 AND LIT SCR1 #0003 clear bits 2:15 92F D8D30D8062F900011930 2139 SCR3 ADD LIT SCR3 #0001 addr + 1 930 D8301C00633F092758E4 2140 WRARX2LOOP,P DATAMOD update data,loop 2141 2142 ***************************************************************************************************** 2143 ***************************************************************************************************** 2144 931 C8731C00637900001932 2145 WRALLRADRX2R LIT SCR1 #0000 index = 0 932 C8F31C00637900001933 2146 LIT SCR3 #0000 addr ptr = 0 933 58D00F0062F400FC1934 2147 WRARX2RLOOP SCR3 AND LIT RADR #00FC set RADR bits 2:7 934 D8301C00633F0935593D 2148 *+1,P SETRBIR set RBIR'S 935 CC3F0C0062F900001936 2149 A,X2 SCR10 SCR10,R write RAM 936 D8D30F0072FF03FF1939 2150 SCR3 AND LIT #03FF SKIP WRARX2RNOTDONE done yet? 2151 >>>>>>>>>>>>>>>>>>>>> 2152 > EVEN 937 4FF31C00637909371937 2152$>WSTE0066 LIT SCR1F * * ****** wasted ****** 938 58D30D8062F9000118E4 2153 > SCR3 ADD LIT SCR3 #0001 DATAMOD yes,update data 939 58530D8062F90001193A 2154 >WRARX2RNOTDONE SCR1 ADD LIT SCR1 #0001 index + 1 2155 >>>>>>>>>>>>>>>>>>>>> 93A 58530F0062F90003193B 2156 SCR1 AND LIT SCR1 #0003 clear bits 2:15 93B D8D30D8062F90001193C 2157 SCR3 ADD LIT SCR3 #0001 addr + 1 93C D8301C00633F093358E4 2158 WRARX2RLOOP,P DATAMOD update data,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 147 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Subroutines to write RAM using RAM address 2160 ***************************************************************************************************** 2161 * * 2162 * This subroutine is used for setting the ram bank index registers for the * 2163 * RAM89TEST. * 2164 * This subroutine first sets all the ram bank index registers to the * 2165 * complement of SCR3 bits 8:9, and then sets the ram bank index register * 2166 * pointed to by SCR1 to the value of SCR3 bits 8:9. * 2167 * This subroutine also leaves X2 set to the value in SCR1 bits 0:1. * 2168 * * 2169 ***************************************************************************************************** 2170 93D D8D30E00E2F9FFFF193E 2171 SETRBIR SCR3 XOR,X LIT SCR3 #FFFF invert & xchng bytes 93E 48311C00636D0000193F 2172 LIT INDX2 #0000 X2=0 93F C8F30C0062FC00001940 2173 SCR3 RBIR set RBIR#0 940 C8311C00636D00011941 2174 LIT INDX2 #0001 X2=1 941 48F30C0062FC00001942 2175 SCR3 RBIR set RBIR#1 942 48311C00636D00021943 2176 LIT INDX2 #0002 X2=2 943 48F30C0062FC00001944 2177 SCR3 RBIR set RBIR#2 944 C8311C00636D00031945 2178 LIT INDX2 #0003 X2=3 945 C8F30C0062FC00001946 2179 SCR3 RBIR set RBIR#3 946 D8D30E0062F9FFFF1947 2180 SCR3 XOR LIT SCR3 #FFFF invert back 947 48710C0062ED00001948 2181 SCR1 INDX2 X2 <- SCR1 948 C8F30C0062FC00001949 2182 SCR3 RBIR set RBIR#X2 949 58D30F00E2F9FFFF9EF1 2183 SCR3 AND,X LIT SCR3 #FFFF POP STERR xchng bytes,return 2184 TITLE.MAC PPU5 SELFTEST Superbus configuration 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 148 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus configuration 2185 ***************************************************************************************************** 2186 * This routine configures some necessary things for the superbus tests. * 2187 * * 2188 * Basically ram address BUSBITS (with index=0) gets the slot * 2189 * number of this board put into bits 8-11 for use with SBCB and RAM * 2190 * address ID (index=0) gets the slot number put in bits 12-15, 4-7, * 2191 * and 0-3 for use with SBFT after doing a bus transfer to itself. * 2192 * * 2193 ***************************************************************************************************** 2194 2195 2196 ***************************************************************************************************** 2197 * First, we must initialize RADR and the 4 RBIR's to zero. * 2198 ***************************************************************************************************** 2199 94A C8311C0063740000194B 2200 CONFIG LIT RADR 0 init RADR<-0 94B C8311C00636D0003194C 2201 LIT INDX2 3 point to port 3 94C C8331C00637C0000194D 2202 LIT RBIR 0 init RBIR3<-0 94D C8311C00636D0002194E 2203 LIT INDX2 2 point to port 2 94E 48331C00637C0000194F 2204 LIT RBIR 0 init RBIR2<-0 94F C8311C00636D00011950 2205 LIT INDX2 1 point to port 1 950 48331C00637C00001951 2206 LIT RBIR 0 init RBIR1<-0 951 C8311C00636D00001952 2207 LIT INDX2 0 point to port 0 952 C8331C00637C00001953 2208 LIT RBIR 0 init RBIR0<-0 2209 953 C8311C00637300001954 2210 LIT INDX1 0 INDX1 <-0 954 D8331C0067B900001955 2211 SBFT SCR0 get N/T/F to SCR0 (wa 955 58130F0062F9F0001956 2212 SCR0 AND LIT SCR0 #F000 there's garbage there 956 78130F28E2F8F0001957 2213 X1 SCR0 AND,X LIT RAM BUSBITS #F000 RAM #10=TO=#00T0 957 F8130EA862D900001958 2214 X1 SCR0 IOR RAM SCR0 BUSBITS SCR0 = #N0T0 958 E8330C0862F800001959 2215 X1 SCR0 RAM ID part of ID = N0T0 (sa 959 48731C0063790003195C 2216 LIT SCR1 #0003 CONFIGRS -4 counter 2217 2218 EVEN 95A 78130DA862D80000195B 2219 X1 SCR0 ADD RAM RAM BUSBITS left one 4 times 95B 58530D8072F9FFFF195C 2220 SCR1 ADD LIT SCR1 #FFFF SKIP 7-4 in 11-8? 95C F0331C2863590000195A 2221 CONFIGRS X1 RAM SCR0 BUSBITS *-2 not in SBCB format yet 95D F8131F28E3590F00195E 2222 X1 LIT AND,X RAM SCR0 BUSBITS #0F00 SLOT = 0T00, SCR0 = 0 95E 78130E8862D80000195F 2223 X1 SCR0 IOR RAM RAM ID ID = N0TF = SBFT check 2224 TITLE.MAC PPU5 SELFTEST Super bus status checks 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 149 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Super bus status checks 2225 ***************************************************************************************************** 2226 * * 2227 * These are some initial status checks to make sure we can set * 2228 * and clear some things. * 2229 * * 2230 ***************************************************************************************************** 2231 CF40 2232 STSTATMASK EQU #CF40 status mask to mask off flags, parity bits, and DWT bit 2233 95F 58331C00633B00001960 2234 NOP,T4 SBRST reset bus logic 960 D8311C00633F00001961 2235 NOP need NOP after reset 961 C8311C00637500001962 2236 LIT SBCB #0000 962 48331C20637880001963 2237 LIT RAM EXSTAT #8000 PFW-IS 1,REST=0 963 58331C00653900001964 2238 SBST SCR0 964 D8130F0062F9CF401965 2239 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 965 58130E2072DF00001966 2240 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST1 ok? 2241 2242 EVEN 966 48331C00637909661C54 2243 SBSTTEST1 LIT SCR0 * ERRTN bad 2244 967 C8311C00636A00041968 2245 LIT SBRFI #0004 set RFI 968 C8331C20637881001969 2246 LIT RAM EXSTAT #8100 exp. status = PFW-,RFI 969 D8331C0065390000196A 2247 SBST SCR0 96A 58130F0062F9CF40196B 2248 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 96B 58130E2072DF0000196C 2249 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST2 RFI set? 2250 2251 EVEN 96C 48331C006379096C1C54 2252 SBSTTEST2 LIT SCR0 * ERRTN bad 2253 96D D8331C00633B0000196E 2254 NOP,T4 SBRST reset RFI 96E 58311C00633F0000196F 2255 NOP 96F 48311C00637500081970 2256 LIT SBCB #0008 set RFR 970 C8331C20637882001971 2257 LIT RAM EXSTAT #8200 exp. status = PFW,RFR 971 D8331C00653900001972 2258 SBST SCR0 972 58130F0062F9CF401973 2259 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 973 58130E2072DF00001974 2260 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST3 RFR set? 2261 2262 EVEN 974 48331C00637909741C54 2263 SBSTTEST3 LIT SCR0 * ERRTN bad 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 150 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Super bus status checks 2265 2266 ***************************************************************************************************** 2267 * It is okay to test this bus error signal this way because this * 2268 * is the internal signal generated from the OR of the parity checker * 2269 * logic (which is reset by SBRST) together with the SBCB line that * 2270 * sets bus error externally. In simpler terms, if another board is * 2271 * pulling on bus error, this board will still pass the next two skips * 2272 * in the test if it is working right. * 2273 ***************************************************************************************************** 2274 975 D8331C00633B00001976 2275 NOP,T4 SBRST reset bus logic 976 58311C00633F00001977 2276 NOP 977 C8311C00637520001978 2277 LIT SBCB #2000 set bus error 978 48331C206378C0001979 2278 LIT RAM EXSTAT #C000 exp. status = PFW-,BSE 979 58331C0065390000197A 2279 SBST SCR0 97A D8130F0062F9CF40197B 2280 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 97B D8130E2072DF0000197C 2281 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST4 BSE set? 2282 2283 EVEN 97C C8331C006379097C1C54 2284 SBSTTEST4 LIT SCR0 * ERRTN bad 2285 97D 48311C0063750000197E 2286 LIT SBCB #0000 97E D8331C00633B0000197F 2287 NOP,T4 SBRST reset bus error F/F 97F C8311C00636600011980 2288 LIT SBINT #0001 set int bit on bus 980 48331C20637880001981 2289 LIT RAM EXSTAT #8000 STAT = PFW- 981 D8331C00653900001982 2290 SBST SCR0 982 58130F0062F9CF401983 2291 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 983 58130E2072DF00001984 2292 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST5 bus error cleared? 2293 2294 EVEN 984 48331C00637909841C54 2295 SBSTTEST5 LIT SCR0 * ERRTN bad 2296 985 48311C00637500081986 2297 LIT SBCB #0008 set RFR 986 48311C00636A00041987 2298 LIT SBRFI #0004 set RFI 987 48331C20637883001988 2299 LIT RAM EXSTAT #8300 expected status=PFW,R 988 58331C00653900001989 2300 SBST SCR0 989 58130F0062F9CF40198A 2301 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 98A D8130E2072DF0000198C 2302 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST6 RFR,RFI set? 2303 2304 EVEN 98B 4FF31C006379098B198B 2304$ WSTE0067 LIT SCR1F * * ****** wasted ****** 98C C8331C006379098C1C54 2305 SBSTTEST6 LIT SCR0 * ERRTN bad 2306 98D 58331C00633B0000198E 2307 NOP,T4 SBRST bus reset 98E D8311C00633F0000198F 2308 NOP 98F 48331C20637880001990 2309 LIT RAM EXSTAT #8000 exp. status = PFW- 990 58331C00653900001991 2310 SBST SCR0 991 58130F0062F9CF401992 2311 SCR0 AND LIT SCR0 STSTATMASK SCR0=status & mask 992 C8311C00636600001993 2312 LIT SBINT #0000 gd place to clear int 993 D8130E2072DF00001994 2313 SCR0 XOR RAM EXSTAT #0000 SKIP SBSTTEST7 all ok? 2314 2315 EVEN 994 C8331C00637909941C54 2316 SBSTTEST7 LIT SCR0 * ERRTN bad 2317 TITLE.MAC PPU5 SELFTEST TO register test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 151 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST TO register test 2318 ***************************************************************************************************** 2319 * * 2320 * This routine checks that the 'TO' register can be accessed. * 2321 * However, the Q- outputs of the 'TO' register are read as * 2322 * status, therefore, there is no guarantee that the Q outputs of the * 2323 * 'TO' register are good. * 2324 * SCR1 - 'TO' in expected * 2325 * RAM0 - 'TO' in actual * 2326 * * 2327 ***************************************************************************************************** 2328 995 C8331C0063790F001996 2329 LIT SCR0 #0F00 initialize SCR0 996 C8731C00637900F0199E 2330 LIT SCR1 #00F0 TOENDLOOP initialize SCR1 2331 997 D8331C0067B800001998 2332 TOLOOP SBFT RAM #00 read 'TO' in 998 D8131F00635800F01999 2333 LIT AND RAM RAM #00 #00F0 isolate bits (7-4) 999 58130D8062F9FF00199A 2334 SCR0 ADD LIT SCR0 #FF00 out=out - 1 99A 58530E0072DF0000199C 2335 SCR1 XOR RAM #00 #0000 SKIP TOTESTFAIL ok? 2336 EVEN 99B 4FF31C006379099B199B 2336$ WSTE0068 LIT SCR1F * * ****** wasted ****** 99C 48331C006379099C1C54 2337 TOTESTFAIL LIT SCR0 * ERRTN bad 99D D8530D8072F9FFF0199E 2338 SCR1 ADD LIT SCR1 #FFF0 SKIP TOENDLOOP EX IN = EX IN - 1 99E 48310C0062F500001997 2339 TOENDLOOP SCR0 SBCB TOLOOP send 'TO' out 2340 TITLE.MAC PPU5 SELFTEST Bus parity tester 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 152 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Bus parity tester 2341 2342 ***************************************************************************************************** 2343 * * 2344 * This part of the test does force bus parity error to make sure * 2345 * that the parity error logic works correctly. This test forces bad * 2346 * parity on half words (16 bits) at a time. * 2347 * * 2348 * A floating one pattern is used for each half word of the * 2349 * transfer. The pattern is kept in RAM HW1. RAM EXSTAT2 is used to * 2350 * check the SBFT status. * 2351 * * 2352 * The bus parity tests are done for double and triple word transfers. * 2353 * * 2354 ***************************************************************************************************** 2355 99F CBF31C006379000019A0 2356 TESTBUSER LIT SCRF 0 DB0 branch adr target 9A0 48331C206378C0C319A1 2357 LIT RAM EXSTAT #C0C3 bus stat=PFW-,BPE,DW, 9A1 50331C086359000019A2 2358 RAM SCR0 ID 9A2 C8330C2462F8000019A3 2359 SCR0 RAM EXSTAT2 9A3 C8331C106378000119A4 2360 TESTBUSER1 LIT RAM HW1 #0001 initial pattern 9A4 CBF3080072FF00001C80 2361 TESTBUSER2 SCRF DB0 TESTBUSERBLOCK and send the pa 2362 2363 >>>>>>>>>>>>>>>>>>>>> 2364 > BLOCK 16 C80 58301C00633F09C659A5 2365 >TESTBUSERBLOCK TST2BUSERRFI,P TESTBUSER20 C81 58131F10735F000119AD 2366 > LIT AND RAM HW1 0001 SKIP TESTBUSER11 1st time? C82 D8131F10735F000119B7 2367 > LIT AND RAM HW1 0001 SKIP TESTBUSER12 1st time? C83 58131F10735F000119BF 2368 > LIT AND RAM HW1 0001 SKIP TESTBUSER13 1st time? C84 58131F10735F000119C8 2369 > LIT AND RAM HW1 0001 SKIP TESTBUSER31 1st time? C85 D8131F10735F000119D4 2370 > LIT AND RAM HW1 0001 SKIP TESTBUSER32 1st time? C86 58131F10735F000119DA 2371 > LIT AND RAM HW1 0001 SKIP TESTBUSER33 1st time? C87 D8131F10735F000119E1 2372 > LIT AND RAM HW1 0001 SKIP TESTBUSER34 1st time? C88 D8131F10735F000119E2 2373 > LIT AND RAM HW1 0001 SKIP TESTBUSER35 1st time? C89 58301C00633F09DD59C0 2374 > TESTBUSER43,P TESTBUSER23 push rtn addr,do it C8A 48331C00637900001A08 2375 > LIT SCR0 0 RAMP next test C8B 58311C00633F00001C8B 2376 > * should never get here C8C D8311C00633F00001C8C 2377 > * should never get here C8D 58311C00633F00001C8D 2378 > * should never get here C8E 58311C00633F00001C8E 2379 > * should never get here C8F D8311C00633F00001C8F 2380 > * should never get here 2381 > ENDBLOCK 2382 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 153 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Bus parity tester 2384 9A5 D0301C106350000019A6 2385 TESTBUSER20 RAM SBHC HW1 output hi word 1 9A6 D0301C106351000019A7 2386 RAM SBLC HW1 output LO word 1 9A7 50301C10634E000019A8 2387 RAM SBHD HW1 output HI word 2 9A8 C8311C006375400019A9 2388 LIT SBCB #4000 force bus error here 9A9 50301C10634F000019AA 2389 RAM SBLD HW1 output LO word 2 9AA 48301C00637500009EF1 2390 LIT SBCB #0000 POP STERR clear bit 14 here 2391 2392 EVEN 9AB 4FF31C00637909AB19AB 2392$ WSTE0069 LIT SCR1F * * ****** wasted ****** 2393 >>>>>>>>>>>>>>>>>>>>> 9AC 58131E206358000F19AD 2394 > LIT XOR RAM RAM EXSTAT #000F 1st time,change expec 9AD D8301C00633F09C659AE 2395 >TESTBUSER11 TST2BUSERRFI,P push return address 2396 >>>>>>>>>>>>>>>>>>>>> 2397 9AE D0301C106350000019AF 2398 TESTBUSER21 RAM SBHC HW1 output HI word 1 9AF D0301C106351000019B0 2399 RAM SBLC HW1 output LO word 1 9B0 C8311C006375400019B1 2400 LIT SBCB #4000 force bus error here 9B1 D0301C10634E000019B2 2401 RAM SBHD HW1 output HI word 2 9B2 C8311C006375000019B3 2402 LIT SBCB #0000 clear bit 14 here 9B3 D0331C10634F00009EF1 2403 RAM SBLD HW1 POP STERR output LO word 2 2404 2405 ODD 9B4 4FF31C00637909B419B4 2405$ WSTE0070 LIT SCR1F * * ****** wasted ****** 2406 9B5 D8131EA46358030019B7 2407 LIT IOR RAM RAM EXSTAT2 #0300 *+2 1st time, change expe 9B6 D8131F206358FFF019B5 2408 LIT AND RAM RAM EXSTAT #FFF0 *-1 1st time,change expec 9B7 58301C00633F09C659B8 2409 TESTBUSER12 TST2BUSERRFI,P push return address 2410 9B8 50301C106350000019B9 2411 TESTBUSER22 RAM SBHC HW1 not 1st time,output H 9B9 48311C006375400019BA 2412 LIT SBCB #4000 force bus error here 9BA 50301C106351000019BB 2413 RAM SBLC HW1 output LO word 1 9BB C8311C006375000019BC 2414 LIT SBCB #0000 clear bit 14 here 9BC D0301C10634E000019BD 2415 RAM SBHD HW1 output HI word 2 9BD D0331C10634F00009EF1 2416 RAM SBLD HW1 POP STERR output LO word 2 2417 2418 EVEN 2419 9BE D8131E2463580F0019BF 2420 LIT XOR RAM RAM EXSTAT2 #0F00 1st time,new expected 9BF 58301C00633F09C659C0 2421 TESTBUSER13 TST2BUSERRFI,P push return address 2422 9C0 48311C006375400019C1 2423 TESTBUSER23 LIT SBCB #4000 force bus error here 9C1 50301C106350000019C2 2424 RAM SBHC HW1 output HI word 1 9C2 48311C006375000019C3 2425 LIT SBCB #0000 clear bit 14 here 9C3 D0301C106351000019C4 2426 RAM SBLC HW1 output LO word 1 9C4 D0301C10634E000019C5 2427 RAM SBHD HW1 output HI word 2 9C5 D0331C10634F00009EF1 2428 RAM SBLD HW1 POP STERR output LO word 2 2429 9C6 C8311C00636A000419C7 2430 TST2BUSERRFI LIT SBRFI #0004 set RFI 9C7 C8331C006379000319E8 2431 LIT SCR0 #0003 TSTBEDOXFER DW+RTO 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 154 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Bus parity tester 2433 EVEN 2434 >>>>>>>>>>>>>>>>>>>>> 9C8 D8301C00633F09D059CC 2435 >TESTBUSER31 TESTBUSER41,P TESTBUSER40 push 1st return ad 9C9 C8331C206378C0C319CA 2436 > LIT RAM EXSTAT #C0C3 1st time,expected sta 2437 >>>>>>>>>>>>>>>>>>>>> 9CA 50331C086359000019CB 2438 RAM SCR0 ID get ID into ... 9CB 48330C2462F8000019C8 2439 SCR0 RAM EXSTAT2 TESTBUSER31 expected SBFT lo 2440 9CC 50301C106350000019CD 2441 TESTBUSER40 RAM SBHC HW1 output HI word 1 9CD D0301C106351000019CE 2442 RAM SBLC HW1 output LO word 1 9CE D0301C10634E000019CF 2443 RAM SBHD HW1 output HI word 2 9CF D0331C10634F00009EF1 2444 RAM SBLD HW1 POP STERR output LO word 2 2445 9D0 D0301C106348000019D1 2446 TESTBUSER41 RAM SBHW3 HW1 output HI word 3 9D1 C8311C006375400019D2 2447 LIT SBCB #4000 force bus error here 9D2 D0301C106349000019D3 2448 RAM SBLW3 HW1 output LO word 3 9D3 C8311C006375000019E5 2449 LIT SBCB #0000 TST3BUSERRFI clear bit 14 here 2450 2451 EVEN 2452 >>>>>>>>>>>>>>>>>>>>> 9D4 D8301C00633F09D659CC 2453 >TESTBUSER32 TESTBUSER42,P TESTBUSER40 push 1st return ad 9D5 D8131E206358000F19D4 2454 > LIT XOR RAM RAM EXSTAT #000F *-1 1st time,expected sta 2455 >>>>>>>>>>>>>>>>>>>>> 2456 9D6 C8311C006375400019D7 2457 TESTBUSER42 LIT SBCB #4000 force bus error here 9D7 D0301C106348000019D8 2458 RAM SBHW3 HW1 output HI word 3 9D8 C8311C006375000019D9 2459 LIT SBCB #0000 clear bit 14 here 9D9 D0301C106349000019E5 2460 RAM SBLW3 HW1 TST3BUSERRFI output LO word 3, 2461 2462 EVEN 2463 >>>>>>>>>>>>>>>>>>>>> 9DA 58301C00633F09DD59A5 2464 >TESTBUSER33 TESTBUSER43,P TESTBUSER20 push rtn addr,do it 9DB D8131F206358FFF019DC 2465 > LIT AND RAM RAM EXSTAT #FFF0 1st time,change expec 2466 >>>>>>>>>>>>>>>>>>>>> 9DC 58131EA46358030019DA 2467 LIT IOR RAM RAM EXSTAT2 #0300 *-2 change expected SBFT 2468 9DD D0301C106348000019DE 2469 TESTBUSER43 RAM SBHW3 HW1 output HI word 3 9DE D0301C106349000019E5 2470 RAM SBLW3 HW1 TST3BUSERRFI output LO word 3 2471 EVEN 9DF 4FF31C00637909DF19DF 2471$ WSTE0071 LIT SCR1F * * ****** wasted ****** 2472 >>>>>>>>>>>>>>>>>>>>> 9E0 58131E2463580F0019E1 2473 > LIT XOR RAM RAM EXSTAT2 #0F00 1st time,change expec 9E1 D8301C00633F09DD59AE 2474 >TESTBUSER34 TESTBUSER43,P TESTBUSER21 push rtn addr,do it 2475 >>>>>>>>>>>>>>>>>>>>> 2476 2477 EVEN 2478 >>>>>>>>>>>>>>>>>>>>> 9E2 58301C00633F09DD59B8 2479 >TESTBUSER35 TESTBUSER43,P TESTBUSER22 push rtn addr,do it 9E3 D8131F246358F0FF19E4 2480 > LIT AND RAM RAM EXSTAT2 #F0FF 1st time,change expec 2481 >>>>>>>>>>>>>>>>>>>>> 9E4 D8131F206358BFF019E2 2482 LIT AND RAM RAM EXSTAT #BFF0 TESTBUSER35 change expected st 9E5 C8311C00636A000419E6 2484 TST3BUSERRFI LIT SBRFI #0004 set RFI 9E6 D8301C006327000019E7 2485 TWDTST enable 3 word TEST 9E7 48331C006379100319E8 2486 LIT SCR0 #1003 TSTBEDOXFER DW+RTO+TW 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 155 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Bus parity tester 9E8 58100EA862D5000019EA 2488 TSTBEDOXFER SCR0 IOR RAM SBCB BUSBITS TSTBENOTIBF DW+RTO+TO#,start x 2489 ODD 9E9 D8130F0072FF004019EA 2490 SCR0 AND LIT #0040 SKIP TSTBENOTIBF IBF set yet? 2491 >>>>>>>>>>>>>>>>>>>>> 9EA 58331C006539000019E9 2492 >TSTBENOTIBF SBST SCR0 *-1 no,get status 9EB 58331C00633F000019EC 2493 > T4 yes 2494 >>>>>>>>>>>>>>>>>>>>> 2495 9EC D8331C006539000019ED 2496 SBST SCR0 status to SCR0 9ED 59331C0065F9000019EE 2497 SBHC SCR4 HI word 1 to SCR4 9EE D9731C006679000019EF 2498 SBLC SCR5 LO word 1 to SCR5 9EF 58731C006539000019F0 2499 SBST SCR1 IBF clr status to SCR1 9F0 59B31C0066F9000019F1 2500 SBHD SCR6 HI word 2 to SCR6 9F1 D9F31C006779000019F2 2501 SBLD SCR7 LO word 2 to SCR7 9F2 58B31C0067B9000019F3 2502 SBFT SCR2 TESTBUSER5 N/T/F to SCR2 2503 2504 ODD 2505 9F3 D8130E2072DF000019F4 2506 TESTBUSER5 SCR0 XOR RAM EXSTAT #0000 SKIP IBF+? (STAT=EXSTAT?) 9F4 C8331C00637909F41C54 2507 LIT SCR0 * ERRTN bad 9F5 D9130E1072DF000019F6 2508 SCR4 XOR RAM HW1 #0000 SKIP H1 word 1 OK? 9F6 48331C00637909F61C54 2509 LIT SCR0 * ERRTN bad 9F7 D9530E1072DF000019F8 2510 SCR5 XOR RAM HW1 #0000 SKIP LO word 1 OK? 9F8 C8331C00637909F81C54 2511 LIT SCR0 * ERRTN bad 9F9 D8530E8072FFFFBF19FA 2512 SCR1 IOR LIT #FFBF SKIP IBF cleared by SBHC? 9FA 48331C00637909FA1C54 2513 LIT SCR0 * ERRTN bad 9FB 59930E1072DF000019FC 2514 SCR6 XOR RAM HW1 #0000 SKIP HI word 2 OK? 9FC 48331C00637909FC1C54 2515 LIT SCR0 * ERRTN bad 9FD 59D30E1072DF000019FE 2516 SCR7 XOR RAM HW1 #0000 SKIP LO word 2 OK? 9FE C8331C00637909FE1C54 2517 LIT SCR0 * ERRTN bad 9FF 58930E2472DF00001A00 2518 SCR2 XOR RAM EXSTAT2 #0000 SKIP N/P/T/F OK? A00 48331C0063790A001C54 2519 LIT SCR0 * ERRTN bad A01 D8331C00633B00001A02 2520 NOP,T4 SBRST loop on xfer if needed A02 58311C00633F00001A03 2521 NOP 2522 A03 50331C10635900001A04 2523 RAM SCR0 HW1 double the A04 58130D9062D800011A05 2524 SCR0 ADD RAM RAM HW1 #0001 DATA word A05 D8131E10735F00001A06 2525 LIT XOR RAM HW1 #0000 SKIP TESTBUSER7 last pattern? 2526 EVEN 2527 >>>>>>>>>>>>>>>>>>>>> A06 D8311C00633F000019A4 2528 >TESTBUSER7 TESTBUSER2 no A07 DBD30D8062F9000119A3 2529 > SCRF ADD LIT SCRF #0001 TESTBUSER1 kick branch addr+1, 2530 >>>>>>>>>>>>>>>>>>>>> 2531 TITLE.MAC PPU5 SELFTEST -- RAM parity tester 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 156 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RAM parity tester 2532 ***************************************************************************************************** 2533 * * 2534 * This routine is designed to test the RAM parity function. * 2535 * * 2536 * This routine does single word transfers to test the functioning * 2537 * of the ram parity hardware. The correct parity is stored into the * 2538 * location corresponding to the words to be used, and incorrect parity * 2539 * is stored in all the other locations. The patterns are done for all * 2540 * settings of the index (i.e. 0,1,2,3) and then the pattern is left * 2541 * shifted one bit. This routine first does a single one shifting in * 2542 * 31 zeros pattern using X2 to set the ram parity, and then does a * 2543 * single zero shifting in 31 ones pattern using X1 to set the ram * 2544 * parity. * 2545 * * 2546 * Register usage: * 2547 * SCR1 - used by TSTDOXFERCHK for contents of SBCB (not including to #) * 2548 * SCR2 - used by TSTDOXFERCHK for SBRFI. Must be #4 for this test. * 2549 * SCR10 - high half of pattern * 2550 * SCR11 - low half of pattern * 2551 * SCR12 - index into RAM * 2552 * SCR13 - used as a counter to make sure we did all index values * 2553 * * 2554 ***************************************************************************************************** 2555 A08 C8331C20637880401A09 2556 RAMP LIT RAM EXSTAT #8040 stat = IBF,PFW- A09 C8731C00637900011A0A 2557 LIT SCR1 #0001 SBCB will get only RTO A0A 48B31C00637900041A0B 2558 LIT SCR2 #0004 used by TSTDOXFERCHK 2559 2560 ***************************************************************************************************** 2561 * Pattern of all zeros and one one --- X1 is used for ram parity * 2562 ***************************************************************************************************** A0B 4C331C00637900001A0C 2563 LIT SCR10 0000 initial pattern 0000- A0C CC731C00637900011A0D 2564 LIT SCR11 0001 -0001 2565 A0D 4CB31C00637900031A0E 2566 RAMPLOOP1 LIT SCR12 #0003 start off w/ INDX=3 A0E CCB10C0062ED00001A0F 2567 SCR12 INDX2 set index A0F CC230C1062F800001A10 2568 RAMPLOOP2 X2,P SCR10 RAM HW1 high pattern to RAM A10 4C630C1162F800001A11 2569 X2,P SCR11 RAM LW1 low pattern to ram A11 4CF31C00637900021A13 2570 LIT SCR13 #0002 RAMPLOOP3 init counter 2571 2572 >>>>>>>>>>>>>>>>>>>>> 2573 > EVEN A12 5C930D8062F9FFFF1A18 2574 > SCR12 ADD LIT SCR12 -1 RAMP2 index - 1,go do xfer A13 5C930D8062F9FFFF1A14 2575 >RAMPLOOP3 SCR12 ADD LIT SCR12 -1 index - 1,loop 2576 >>>>>>>>>>>>>>>>>>>>> A14 4CB10C0062ED00001A15 2577 SCR12 INDX2 SET X2 A15 5C030E1062F815EA1A16 2578 X2,P SCR10 XOR LIT RAM HW1 #15EA store bad parity A16 DC430E1162F8C7381A17 2579 X2,P SCR11 XOR LIT RAM LW1 #C738 store bad parity A17 DCD30D8072F9FFFF1A13 2580 SCR13 ADD LIT SCR13 -1 SKIP RAMPLOOP3 cntr-1,done all inde 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 157 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RAM parity tester A18 4CB10C0062ED00001A19 2582 RAMP2 SCR12 INDX2 set X2 for xfer A19 DC930F0062F900031A1A 2583 SCR12 AND LIT SCR12 #0003 keep bits 0:1 only A1A DC900E0062F300031A1B 2584 SCR12 XOR LIT INDX1 #0003 set X1 different than A1B 50211C10635000001A1C 2585 X2,P RAM SBHC HW1 output HI word w/ par A1C D0211C11635100001A1D 2586 X2,P RAM SBLC LW1 output LO word w/ par A1D 48311C00636D00001A1E 2587 LIT INDX2 0 TSTDOXFERCHK uses X2=0 A1E 4C330C1062F800001A1F 2588 X2 SCR10 RAM HW1 for TSTDOXFERCHK A1F 4C730C1162F800001A20 2589 X2 SCR11 RAM LW1 for TSTDOXFERCHK A20 D8301C00633F0A215B24 2590 RAMP4,P TSTDOXFERCHK go do xfer 2591 2592 ODD A21 D8130E8072FF00001A22 2593 RAMP4 SCR0 IOR LIT 0 SKIP error from TSTDOXFERC 2594 >>>>>>>>>>>>>>>>>>>>> A22 D8311C00633F00001C54 2595 > ERRTN yes, error A23 DC930D8072F9FFFF1A24 2596 > SCR12 ADD LIT SCR12 -1 SKIP no,all indexes? 2597 >>>>>>>>>>>>>>>>>>>>> 2598 2599 >>>>>>>>>>>>>>>>>>>>> A24 CCB10C0062ED00001A0F 2600 > SCR12 INDX2 RAMPLOOP2 no,set X2,loop A25 DC538D9162D900001A26 2601 > CST SCR11 ADD RAM SCR11 LW1 yes, shift the... 2602 >>>>>>>>>>>>>>>>>>>>> A26 9C138D9062D900001A27 2603 CST,TWC SCR10 ADD RAM SCR10 HW1 pattern to the left A27 9C530D8062F900001A28 2604 TWC SCR11 ADD LIT SCR11 0 add in carry A28 DC530F0072FF00011A2A 2605 SCR11 AND LIT 0001 SKIP RAMP5 done w/ this pattern? 2606 >>>>>>>>>>>>>>>>>>>>> 2607 > EVEN A29 4FF31C0063790A291A29 2607$>WSTE0072 LIT SCR1F * * ****** wasted ****** A2A D8311C00633F00001A0D 2608 >RAMP5 RAMPLOOP1 no,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 158 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RAM parity tester 2610 ***************************************************************************************************** 2611 * Pattern of all ones and one zero --- X1 is used for ram parity * 2612 ***************************************************************************************************** A2B CC331C006379FFFF1A2C 2613 > LIT SCR10 #FFFF initial pattern FFFF- 2614 >>>>>>>>>>>>>>>>>>>>> A2C 4C731C006379FFFE1A2D 2615 LIT SCR11 #FFFE -FFFE 2616 A2D CCB31C00637900031A2E 2617 RAMPLOOP4 LIT SCR12 #0003 start off w/ index=3 A2E 4CB10C0062F300001A2F 2618 SCR12 INDX1 set index A2F EC230C1062F800001A30 2619 RAMPLOOP5 X1,P SCR10 RAM HW1 high pattern to RAM A30 6C630C1162F800001A31 2620 X1,P SCR11 RAM LW1 low pattern to RAM A31 CCF31C00637900021A33 2621 LIT SCR13 #0002 RAMPLOOP6 init counter 2622 2623 >>>>>>>>>>>>>>>>>>>>> 2624 > EVEN A32 DC930D8062F9FFFF1A38 2625 > SCR12 ADD LIT SCR12 -1 RAMPA index - 1,go do xfer A33 DC930D8062F9FFFF1A34 2626 >RAMPLOOP6 SCR12 ADD LIT SCR12 -1 index - 1,loop 2627 >>>>>>>>>>>>>>>>>>>>> A34 CCB10C0062F300001A35 2628 SCR12 INDX1 set X1 A35 7C030E1062F815EA1A36 2629 X1,P SCR10 XOR LIT RAM HW1 #15EA store bad parity A36 FC430E1162F8C7381A37 2630 X1,P SCR11 XOR LIT RAM LW1 #C738 store bad parity A37 5CD30D8072F9FFFF1A33 2631 SCR13 ADD LIT SCR13 -1 SKIP RAMPLOOP6 cntr-1,done all inde 2632 A38 CCB10C0062F300001A39 2633 RAMPA SCR12 INDX1 set X1 for xfer A39 5C930F0062F900031A3A 2634 SCR12 AND LIT SCR12 #0003 keep bits 0:1 only A3A 5C900E0062ED00031A3B 2635 SCR12 XOR LIT INDX2 #0003 set X2 different than A3B 70211C10635000001A3C 2636 X1,P RAM SBHC HW1 output HI word w/ par A3C F0211C11635100001A3D 2637 X1,P RAM SBLC LW1 output LO word w/ par A3D C8311C00636D00001A3E 2638 LIT INDX2 0 TSTDOXFERCHK uses X2=0 A3E CC330C1062F800001A3F 2639 X2 SCR10 RAM HW1 for TSTDOXFERCHK A3F 4C730C1162F800001A40 2640 X2 SCR11 RAM LW1 for TSTDOXFERCHK A40 D8301C00633F0A415B24 2641 RAMP6,P TSTDOXFERCHK go do xfer 2642 2643 ODD A41 D8130E8072FF00001A42 2644 RAMP6 SCR0 IOR LIT 0 SKIP error from TSTDOXFERC 2645 >>>>>>>>>>>>>>>>>>>>> A42 D8311C00633F00001C54 2646 > ERRTN yes, error A43 DC930D8072F9FFFF1A44 2647 > SCR12 ADD LIT SCR12 -1 SKIP no,all indexes? 2648 >>>>>>>>>>>>>>>>>>>>> 2649 2650 >>>>>>>>>>>>>>>>>>>>> A44 4CB10C0062F300001A2F 2651 > SCR12 INDX1 RAMPLOOP5 no,set X1,loop A45 DC538D9162D900001A46 2652 > CST SCR11 ADD RAM SCR11 LW1 yes,shift the... 2653 >>>>>>>>>>>>>>>>>>>>> A46 9C138D9062D900001A47 2654 CST,TWC SCR10 ADD RAM SCR10 HW1 pattern to the left A47 9C530D8062F900001A48 2655 TWC SCR11 ADD LIT SCR11 0 add in carry A48 DC530E8072FFFFFE1A4A 2656 SCR11 IOR LIT #FFFE SKIP RAMP8 done w/ this pattern? 2657 >>>>>>>>>>>>>>>>>>>>> 2658 > EVEN A49 4FF31C0063790A491A49 2658$>WSTE0073 LIT SCR1F * * ****** wasted ****** A4A 58311C00633F00001A2D 2659 >RAMP8 RAMPLOOP4 no,loop A4B D8311C00633F00001A4C 2660 > INTEST yes,next test 2661 >>>>>>>>>>>>>>>>>>>>> 2662 TITLE.MAC PPU5 SELFTEST interrupt test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 159 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2663 ***************************************************************************************************** 2664 * * 2665 * Interrupt test * 2666 * * 2667 * This part of selftest tests the interrupt mechanism. * 2668 * * 2669 * This test should run after the config section which should set * 2670 * up the TO and FROM slot # in ram BUSBITS and ram ID for use in * 2671 * starting transfer and checking afterward. * 2672 * * 2673 * The test starts out by resetting all the ports to direction out * 2674 * which should cause all the ports to be requesting an interrupt. The * 2675 * reset subroutine checks to make sure the interrupt bit and PON bit * 2676 * in PTST are correct after resetting the ports. * 2677 * * 2678 * The initialization includes putting the right thing into * 2679 * ram PTFULL and setting ram WDCNT through WDCNT+3 to indicate * 2680 * 10 (hex) 16 bit words left to put into each FIFO. The location * 2681 * PTFULL is counted to decide when the ports are 4 (16 bit) * 2682 * words from being full and all the way full. * 2683 * * 2684 * This routine sets all of the interrupt addresses to the * 2685 * SELFTESTVECTOR. This routine does double word transfers to * 2686 * itself to get the exact interrupt address that it wants. This * 2687 * routine decides exactly how it will set the bus logic (and the * 2688 * 4 LSB's of the interrupt address) by doing a 16 way branch on * 2689 * the 4 MSB's of the counter it is using. The 16 way branch is * 2690 * to the BUSBLOCK. From there, control goes to a part that * 2691 * decides how to set BUSBITS (SBCB) to get the bus logic set to * 2692 * the desired state. * 2693 * * 2694 * The BUSBLOCK stuff is divided up into 3 basic types of routines * 2695 * based on the branch address taken. The least significant nibble of * 2696 * the BUSBLOCK branch address should be the same as the least * 2697 * significant nibble of the interrupt address and the value in ram * 2698 * VECTCK. I will therefore divide this discussion into 3 parts based * 2699 * on this value. * 2700 * * 2701 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 160 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2703 ***************************************************************************************************** 2704 * * 2705 * VECTCK = 0,1,2,3 * 2706 * If this is the case, you check either the IBF interrupt or the * 2707 * port interrupt after the branch to BUSBLOCK, call back and input * 2708 * buffer full interrupts are enabled. The routine uses ram PTFULL to * 2709 * decide whether to do an IBF interrupt or a port interrupt. If PTFULL * 2710 * is equal to zero, we are doing an IBF interrupt. If PTFULL is not * 2711 * equal to zero, then CBN and IBF interrupts and all interrupts for * 2712 * higher priority ports are disabled (the interrupts for the port * 2713 * being tested and lower priority ports are enabled). The port to be * 2714 * tested is the same number as the value in VECTCK. If we are doing a * 2715 * port test, we set BUSBITS correctly, set ram PINTCK to a value to * 2716 * indicate which port we are trying to check, and then branch to the * 2717 * routine that does the transfer. After the transfer is done, we take * 2718 * an interrupt. The interrupt routine checks to see if we took the * 2719 * right interrupt. If this was a port interrupt, we also check to * 2720 * ensure that the correct port interrupted, read the bus input registers * 2721 * into the FIFO of the interrupting port (doing the proper counting), * 2722 * and decrement the counter of bytes remaining to be input. After all * 2723 * this happens, control returns to just after the branch into * 2724 * BUSBLOCK. * 2725 * * 2726 * VECTCK = 4,5,6,7,C,D,E,F * 2727 * If this is the case, the routine first does a transfer with * 2728 * BUSBITS set appropriately and RFR set. Next the RFR bit in ram * 2729 * BUSBITS is cleared, CBN and IBF interrupts are enabled, and RFI is * 2730 * cleared. The board then does another transfer without reloading the * 2731 * bus output registers. (This is accomplished by just doing a store to * 2732 * SBCB.) Since RFI and RFR are both clear, this transfer should result * 2733 * in the PPU NAKing itself and should set the CBN interrupt. The * 2734 * board will then be allowed to take the CBN interrupt. The interrupt * 2735 * routine transfers control to a routine which checks to make sure the * 2736 * correct interrupt was taken and disables all interrupts. After * 2737 * that, RFI is set so the transfer may complete. When the transfer * 2738 * completes, the routine checks to see if this was a transfer that set * 2739 * bus error (C,D,E,F) and if so, the bus logic is reset. After all * 2740 * this, control returns to just after the branch into BUSBLOCK. * 2741 * * 2742 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 161 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2744 ***************************************************************************************************** 2745 * * 2746 * VECTCK = 8,9,A,B * 2747 * In this routine, the IBF interrupt is used. First, CBN and IBF * 2748 * interrupts are enabled and port interrupts are disabled. Then, the * 2749 * bus transfer is done with force bus parity error set. After the * 2750 * transfer completes, the IBF interrupt is allowed to occur. The * 2751 * interrupt routine disables all interrupts, checks to make sure the * 2752 * correct interrupt was taken, and does a bus logic reset to clear out * 2753 * the bus error. After all this, control goes back to the place just * 2754 * after the branch into BUSBLOCK. * 2755 * * 2756 * * 2757 * After the return from all the BUSBLOCK routines, control * 2758 * will go to INTEST2. Here, all of the words of the bus xfer are * 2759 * read in and checked for correctness. After that, the bus data * 2760 * pattern is modified. Next, we check to see * 2761 * if we are done yet and proceed if we are. If not, we check to * 2762 * see if ram PTFULL has been zeroed yet. If it is zero, we just * 2763 * loop back to INTEST1. If not zero, we count it down and check * 2764 * to see if the FIFO is four words from being full. If it just * 2765 * became zero we set ram EXSTAT to the appropriate state of the * 2766 * PTST "FIFO not interrupting" bit and check this bit for each * 2767 * port. If we happen to be checking for "FIFO not interrupting" * 2768 * = TRUE, then we also check to make sure the wordcount was * 2769 * decremented to zero. After all this, we loop back to INTEST1. * 2770 * * 2771 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 162 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2773 ***************************************************************************************************** 2774 * * 2775 * Some comments about this part of the selftest: * 2776 * * 2777 * This explanation was first figured out and written down by * 2778 * Bill Oliver in November 1984. I hope is is accurate and usable. I * 2779 * do have some comments on some things I see wrong with this routine. * 2780 * I did correct some coding mistakes that could have prevented a few * 2781 * kinds of errors from being detected. This routine does not check * 2782 * out the vector addressing logic. This is because all the vectors * 2783 * are set to SELFTESTVECTOR for the entire test. This routine also * 2784 * does not distinguish very well between CBN and IBF interrupts. This * 2785 * is because these two interrupts are always enabled and disabled * 2786 * together. This routine does not check all combinations for all * 2787 * interrupts, i.e. port 0 is only tested for vector 0, port 1 for * 2788 * vector 1, etc. This may not be serious since, theoretically, the 4 * 2789 * LSB's of the interrupt taken should be independent of the other bits * 2790 * of the interrupt address. This routine does not very thoroughly * 2791 * check the priority encoding logic. This is partly because IBF and * 2792 * CBN interrupts are always dis/enabled together and partly because * 2793 * port interrupts are always enabled for the port to be tested and all * 2794 * lower priority ports. Also, because of the way interrupts are * 2795 * enabled and disabled, the interrupt mask register is not very * 2796 * thoroughly tested. A minor gripe might be that this interrupt * 2797 * test only does double word transfers. I think that this interrupt * 2798 * testing routine might have gotten written like it is because of * 2799 * space limitations in the old PPU. This might also explain why this * 2800 * routine seems to be trying to check a lot of functions in addition * 2801 * to interrupts (like the port logic). One thing I don't understand * 2802 * but won't change now is at address CBXFER + 2 where SBHC * 2803 * is done in the same instruction as clearing RFI. (SBHC seems * 2804 * unnecessary.) For now, I am not going to rewrite this interrupt * 2805 * test even though I disagree with the way some of it works. * 2806 * * 2807 * Variable usage * 2808 * RAM ID -- used to make sure we got correct result in SBFT * 2809 * RAM BUSBITS -- used to store into SBCB to do a transfer * 2810 * RAM HW1 -- used for high order 16 bits of 64 bit xfer and for BUSBLOCK branch * 2811 * RAM LW1 -- used for next 16 bits of 64 bit xfer * 2812 * RAM HW2 -- used for next 16 bits of 64 bit xfer * 2813 * RAM HW2 -- used for low order 16 bits of 64 bit xfer * 2814 * RAM VECTCK -- used to verify that we did go to correct interrupt address * 2815 * RAM EXSTAT -- used to check the "FIFO not interrupting" bit of PTST * 2816 * RAM PTFULL -- used to decide if FIFOs are full yet * 2817 * RAM PINTCK -- used to check if proper port interrupted * 2818 * RAM TCON -- counter for transfers * 2819 * RAM WDCNT to WDCNT+3 -- number of 16 bit words left to put in FIFOs * 2820 * * 2821 ***************************************************************************************************** 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 163 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2823 * Selftest interrupt vector 2824 2825 >>>>>>>>>>>>>>>>>>>>> 2826 > VECTOR FA0 CA331000737900001DF8 2827 >SELFTESTVECTOR LIT SCR8 #0000 INDX PINTRTN FA1 4A331000737900011DF8 2828 > LIT SCR8 #0001 INDX PINTRTN FA2 4A331000737900021DF8 2829 > LIT SCR8 #0002 INDX PINTRTN FA3 CA331000737900031DF8 2830 > LIT SCR8 #0003 INDX PINTRTN FA4 CA331C00637900041AF9 2831 > LIT SCR8 #0004 CBRTN FA5 4A331C00637900051AF9 2832 > LIT SCR8 #0005 CBRTN FA6 4A331C00637900061AF9 2833 > LIT SCR8 #0006 CBRTN FA7 CA331C00637900071AF9 2834 > LIT SCR8 #0007 CBRTN FA8 4A331C00637900081AFE 2835 > LIT SCR8 #0008 BSERTN FA9 CA331C00637900091AFE 2836 > LIT SCR8 #0009 BSERTN FAA CA331C006379000A1AFE 2837 > LIT SCR8 #000A BSERTN FAB 4A331C006379000B1AFE 2838 > LIT SCR8 #000B BSERTN FAC 4A331C006379000C1AF9 2839 > LIT SCR8 #000C CBRTN FAD CA331C006379000D1AF9 2840 > LIT SCR8 #000D CBRTN FAE CA331C006379000E1AF9 2841 > LIT SCR8 #000E CBRTN FAF 4A331C006379000F1AF9 2842 > LIT SCR8 #000F CBRTN 2843 > ENDVECTOR 2844 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 164 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2846 ***************************************************************************************************** 2847 * Interrupt test * 2848 * The first thing this test does is call the reset subroutine to * 2849 * reset the FIFO logic for direction out and check to make sure the * 2850 * interrupt bit in PTST (bit 11) is set correctly. * 2851 * This part then checks all the port's PON bits in PTST (bit 14) * 2852 * to see if it is clear. It should be clear because of the DPOE := * 2853 * zero instruction at the beginning of the SELFTEST. * 2854 * This section verifies that the ports interrupt at the * 2855 * proper level of FIFO empty/full-ness and that data transfers to * 2856 * ourselves work okay. * 2857 * The first group of transfers exercise Bus Error on some of * 2858 * the transfers, but then we enter a 'clean' section that does not * 2859 * assert bus error. We must ensure that no bus error is asserted * 2860 * after 800 ms from the start of test. This allows the one second * 2861 * mark to mean that any further bus error is a real bus error. * 2862 * We release the controllers to run their self-tests and etc * 2863 * about one second after the start of the test. * 2864 * No test after this should assert bus error (unless test fails) * 2865 * since this test lets the controllers go and in PPU5 the PFW signal * 2866 * to the controllers is the logical OR of BSE and PFW from the VRA * 2867 * bus. No other board on the system should assert BSE after this * 2868 * routine executes. * 2869 * * 2870 ***************************************************************************************************** 2871 2872 EVEN 2873 A4C D8531F8063790A4D5B06 2874 INTEST ONES SCR1 *+1,P RESET all ports dir out A4D 58130E0072FF00001A4E 2875 SCR0 XOR LIT #0000 SKIP any port status error A4E D8311C00633F00001C54 2876 ERRTN yes, leave error code A4F 48731C00637900031A50 2877 LIT SCR1 3 initialize port count A50 C8710C0062ED00001A52 2878 SCR1 INDX2 CONTRESET2 set index 2 2879 2880 EVEN A51 4FF31C0063790A511A51 2880$ WSTE0074 LIT SCR1F * * ****** wasted ****** 2881 A52 D8B31C00613900001A53 2882 CONTRESET2 X2 PTST SCR2 get port status A53 D8930F0072F940001A55 2883 SCR2 AND LIT SCR2 #4000 SKIP *+2 PON bit set? 2884 A54 C8331C0063790A541C54 2885 LIT SCR0 * ERRTN yes, error A55 58530D8072F9FFFF1A56 2886 SCR1 ADD LIT SCR1 #FFFF SKIP no, done? 2887 A56 C8710C0062ED00001A52 2888 SCR1 INDX2 CONTRESET2 no, next port A57 CBF31C00637900031A5A 2889 LIT SCRF #0003 INTESTA set 2890 EVEN A58 C8331C06637800101A59 2891 X2 LIT RAM WDCNT #0010 wordcount A59 DBD30D8072F9FFFF1A5A 2892 SCRF ADD LIT SCRF #FFFF SKIP for all A5A 4BF10C0062ED00001A58 2893 INTESTA SCRF INDX2 *-2 four ports 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 165 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test A5B E8331C07637800401A5C 2895 X1 LIT RAM PTFULL #0040 fifos S.B. full at th 2896 A5C 48331C00637A0FA01A5D 2897 LIT IADR #00 SELFTESTVECTOR all A5D C8331C04637A0FA01A5E 2898 LIT IADR #10 SELFTESTVECTOR interrupt A5E 48331C08637A0FA01A5F 2899 LIT IADR #20 SELFTESTVECTOR vector A5F C8331C0C637A0FA01A60 2900 LIT IADR #30 SELFTESTVECTOR buffer A60 C8331C10637A0FA01A61 2901 LIT IADR #40 SELFTESTVECTOR locations A61 48331C14637A0FA01A62 2902 LIT IADR #50 SELFTESTVECTOR get set A62 C8331C18637A0FA01A63 2903 LIT IADR #60 SELFTESTVECTOR to A63 C8331C1C637A0FA01A64 2904 LIT IADR #70 SELFTESTVECTOR SELFTESTVECTOR 2905 2906 * set up 4 x 16 bit data pattern for the superbus portion of this test 2907 A64 68331C1063780F0A1A65 2908 X1 LIT RAM HW1 #0F0A set up ... A65 E8331C116378F0F51A66 2909 X1 LIT RAM LW1 #F0F5 ... initial test ... A66 68331C186378AAAA1A67 2910 X1 LIT RAM HW2 #AAAA ... pattern A67 E8331C1C637855551A68 2911 X1 LIT RAM LW2 #5555 2912 A68 E8331C1463783FFF1A6C 2913 X1 LIT RAM TCON #3FFF BETEST set up count for sect 2914 * testing bus error 2915 2916 ODD 2917 A69 58130E0072FF00001A6A 2918 BETEST1 SCR0 XOR LIT #0000 SKIP any errors? A6A D8311C00633F00001C54 2919 ERRTN yes, quit now A6B F8131D947358FFFF1A6C 2920 X1 LIT ADD RAM RAM TCON #FFFF SKIP down count and test A6C F0F31C1463590A695A76 2921 BETEST X1 RAM SCR3 TCON BETEST1,P INTEST1 do the transfer 2922 * done with count 2923 A6D E8331C146378FFFF1A74 2924 X1 LIT RAM TCON #FFFF FLTEST set up count for full 2925 A6E D8301C00633F0A6F5A76 2926 FLTEST1 *+1,P INTEST1 off to do the transfer A6F D8130E0072FF00001A70 2927 SCR0 XOR LIT #0000 SKIP any errors? A70 D8311C00633F00001C54 2928 ERRTN yes, quit now A71 78131C94735F48501A73 2929 X1 LIT RSUB RAM TCON #4850 SKIP *+2 controller release? A72 48311C00637200F01A73 2930 LIT DPOE #F0 release controllers t A73 F8131D947358FFFF1A74 2931 X1 LIT ADD RAM RAM TCON #FFFF SKIP down count and test A74 F8D31F14635900071A6E 2932 FLTEST X1 LIT AND RAM SCR3 TCON #7 FLTEST1 limit test options in 2933 * done with count 2934 A75 D8531C0063790B1B5B06 2935 ZERO SCR1 RSTSTCH,P RESET set ports dir IN 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 166 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2937 ***************************************************************************************************** 2938 * Bus transfer Routine * 2939 * This SR transfers one word on the bus using the scheme * 2940 * indicated in SCR3. We verify that the transfer happened okay. * 2941 * On return SCR0 contains zero or an error code. * 2942 ***************************************************************************************************** 2943 A76 C8331C00637900001A77 2944 INTEST1 LIT SCR0 #0000 initialize SCR0 A77 78131F2863580F001A78 2945 X1 LIT AND RAM RAM BUSBITS #0F00 a little pre-processi A78 F8D30F0562F8000F1A79 2946 X1 SCR3 AND LIT RAM VECTCK #000F SCR3 = 000F for vecto A79 E8F3080072FF0A7B5C70 2947 X1 SCR3 INTEST2,P DB0 BUSBLOCK 2948 2949 ODD A7A 4FF31C0063790A7A1A7A 2949$ WSTE0075 LIT SCR1F * * ****** wasted ****** A7B D8130E0072FF00001A7C 2950 INTEST2 SCR0 XOR LIT #0000 SKIP any prev. int errors? A7C 58301C00633F00009EF1 2951 POP STERR yes, leave error code 2952 A7D 59331C0065F900001A7E 2953 SBHC SCR4 read A7E D9731C00667900001A7F 2954 SBLC SCR5 four A7F 59B31C0066F900001A80 2955 SBHD SCR6 input A80 59F31C00677900001A81 2956 SBLD SCR7 registers 2957 A81 79130E1072DF00001A82 2958 X1 SCR4 XOR RAM HW1 #0000 SKIP high word 1 ok? A82 48331C0063790A829EF1 2959 LIT SCR0 * POP STERR A83 79530E1172DF00001A84 2960 X1 SCR5 XOR RAM LW1 #0000 SKIP low word 1 ok? A84 48331C0063790A849EF1 2961 LIT SCR0 * POP STERR A85 F9930E1872DF00001A86 2962 X1 SCR6 XOR RAM HW2 #0000 SKIP high word 2 ok? A86 C8331C0063790A869EF1 2963 LIT SCR0 * POP STERR A87 79D30E1C72DF00001A88 2964 X1 SCR7 XOR RAM LW2 #0000 SKIP low word 2 ok? A88 48331C0063790A889EF1 2965 LIT SCR0 * POP STERR A89 F8131D90635800011A8A 2966 X1 LIT ADD RAM RAM HW1 #0001 modify the test ... A8A F8131D91635800131A8B 2967 X1 LIT ADD RAM RAM LW1 #0013 ... pattern to exerc A8B 78131D98635801051A8C 2968 X1 LIT ADD RAM RAM HW2 #0105 ... the drivers and A8C F8131D9C6358100B1A8D 2969 X1 LIT ADD RAM RAM LW2 #100B ... receivers 2970 A8D F8131E07735F00001A8F 2971 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 must we bother? A8E 58301C00633F00009EF1 2972 POP STERR not with that shit A8F F8131D876358FFFF1A90 2973 X1 LIT ADD RAM RAM PTFULL #FFFF decrement the counter A90 D8311C00633F00001A91 2974 NOP for lineup A91 78131E07735F00001A93 2975 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 check for all FIFOs f A92 E8331C20637808001A96 2976 X1 LIT RAM EXSTAT #0800 INTEST3 say bit 11=1=ints off A93 78131E07735F00101A94 2977 X1 LIT XOR RAM PTFULL #0010 SKIP 12 in all output FIFO A94 58301C00633F00009EF1 2978 POP STERR not 12 yet A95 68331C20637800001A96 2979 X1 LIT RAM EXSTAT #0000 say bit 11=0=ints on A96 CBF31C00637900031AA0 2980 INTEST3 LIT SCRF #0003 INTEST6 init index and load it 2981 ODD A97 D8331C00613900001A98 2982 INTEST4 PTST SCR0 read port int stat A98 D8130F0062F908001A99 2983 SCR0 AND LIT SCR0 #0800 interrupt bit 11 only A99 78130E2072D900001A9B 2984 X1 SCR0 XOR RAM SCR0 EXSTAT #0000 SKIP *+2 good? A9A 78131F20735F08001A9C 2985 X1 LIT AND RAM EXSTAT #0800 SKIP *+2 is this a full test? A9B C8331C0063790A9B9EF1 2986 LIT SCR0 * POP STERR ungood A9C 58311C00633F00001A9F 2987 INTEST5 don't check word count A9D D8131E06735F00001A9E 2988 X2 LIT XOR RAM WDCNT #0000 SKIP all 4 word counts sho A9E C8331C0063790A9E9EF1 2989 LIT SCR0 * POP STERR one of them isn't A9F DBD30D8072F9FFFF1AA0 2990 INTEST5 SCRF ADD LIT SCRF #FFFF SKIP done? AA0 4BF10C0062ED00001A97 2991 INTEST6 SCRF INDX2 INTEST4 not done, back AA1 58301C00633F00009EF1 2992 POP STERR get outta here 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 167 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 2994 * Subroutines 2995 2996 * Branch here on LW2 data in SCR3, SCR1 (5-0) = IMR, 15-8 to check vector addr. 2997 2998 BLOCK 16 2999 >>>>>>>>>>>>>>>>>>>>> C70 C8311C006377000F1AA3 3000 >BUSBLOCK LIT IMR #000F DATA0 IBFINT,P0INT C71 48311C006377000F1AA7 3001 > LIT IMR #000F DATA1 IBFINT,P1INT C72 48311C006377000F1AAB 3002 > LIT IMR #000F DATA2 IBFINT,P2INT C73 C8311C006377000F1AAF 3003 > LIT IMR #000F DATA3 IBFINT,P3INT C74 D8301C00633F0AB45AB3 3004 > DATA4A,P DATA4 CBINT C75 58301C00633F0AB65AB5 3005 > DATA5A,P DATA5 CBINT C76 58301C00633F0AB85AB7 3006 > DATA6A,P DATA6 CBINT C77 58301C00633F0ABA5AB9 3007 > DATA7A,P DATA7 CBINT C78 C8311C006377000F1ABB 3008 > LIT IMR #000F DATA8 IBFINT-BSER C79 48311C006377000F1ABC 3009 > LIT IMR #000F DATA9 IBFINT-BSER C7A C8311C006377000F1ABD 3010 > LIT IMR #000F DATAA IBFINT-BSER C7B C8311C006377000F1ABE 3011 > LIT IMR #000F DATAB IBFINT-BSER C7C D8301C00633F0AC05ABF 3012 > DATACA,P DATAC CBINT-BSER C7D 58301C00633F0AC25AC1 3013 > DATADA,P DATAD CBINT-BSER C7E D8301C00633F0AC45AC3 3014 > DATAEA,P DATAE CBINT-BSER C7F 58301C00633F0AC65AC5 3015 > DATAFA,P DATAF CBINT-BSER 3016 >>>>>>>>>>>>>>>>>>>>> 3017 ENDBLOCK 3019 ODD AA2 4FF31C0063790AA21AA2 3019$ WSTE0076 LIT SCR1F * * ****** wasted ****** 3020 AA3 78131E07735F00001AA5 3021 DATA0 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 0 or IBF? AA4 F8131EA86358001B1AD6 3022 DATA0A X1 LIT IOR RAM RAM BUSBITS #001B ENAINT IBF,slot+F0W1+RFR+DW+ AA5 48311C006377003E1AA6 3023 LIT IMR #3E enable port 0 int AA6 E8331C046378C0DE1AA4 3024 X1 LIT RAM PINTCK #C0DE DATA0A say port 0 int expect AA7 78131E07735F00001AA9 3025 DATA1 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 1 or IBF? AA8 78131EA86358005B1AD6 3026 DATA1A X1 LIT IOR RAM RAM BUSBITS #005B ENAINT slot+F0W1+RFR+DW+RTO AA9 C8311C006377003C1AAA 3027 LIT IMR #003C enable port 1 ints (& AAA E8331C04637811111AA8 3028 X1 LIT RAM PINTCK #1111 DATA1A say port 1 int expect AAB F8131E07735F00001AAD 3029 DATA2 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 2 or IBF? AAC F8131EA86358002B1AD6 3030 DATA2A X1 LIT IOR RAM RAM BUSBITS #002B ENAINT slot+F1W2+RFR+DW+RTO AAD C8311C00637700381AAE 3031 LIT IMR #0038 enable port 2 int (&P AAE 68331C04637822221AAC 3032 X1 LIT RAM PINTCK #2222 DATA2A port 2 int expected AAF 78131E07735F00001AB1 3033 DATA3 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 port 3 or IBF? AB0 78131EA8635800FB1AD6 3034 DATA3A X1 LIT IOR RAM RAM BUSBITS #00FB ENAINT slot+4FLAGS+RFR+DW+RTO AB1 C8311C00637700301AB2 3035 LIT IMR #0030 enable port 3 int (&P AB2 E8331C04637833331AB0 3036 X1 LIT RAM PINTCK #3333 DATA3A port 3 int expected AB3 78131EA86358000B1AD5 3037 DATA4 X1 LIT IOR RAM RAM BUSBITS #000B DISAINT slot+RFR+DW+RTO AB4 F8131E28635800081AC8 3038 DATA4A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER slot+DW+RTO AB5 78131EA86358005B1AD5 3039 DATA5 X1 LIT IOR RAM RAM BUSBITS #005B DISAINT slot+F0W2+F0W1+RFR+DW AB6 F8131E28635800081AC8 3040 DATA5A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER slot+FOW2+F0W1+DW+RTO AB7 F8131EA86358002B1AD5 3041 DATA6 X1 LIT IOR RAM RAM BUSBITS #002B DISAINT slot+F1W1+RFR+DW+RTO AB8 F8131E28635800081AC8 3042 DATA6A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER slot+F1W1+DW+RTO AB9 78131EA8635800FB1AD5 3043 DATA7 X1 LIT IOR RAM RAM BUSBITS #00FB DISAINT slot+F0W1+F1W2+F0W2+R ABA F8131E28635800081AC8 3044 DATA7A X1 LIT XOR RAM RAM BUSBITS #0008 CBXFER slot+DW+RTO 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 168 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test ABB F8131EA86358400B1AD6 3046 DATA8 X1 LIT IOR RAM RAM BUSBITS #400B ENAINT BPE+RFR+DW+RTO ABC F8131EA86358405B1AD6 3047 DATA9 X1 LIT IOR RAM RAM BUSBITS #405B ENAINT BPE+F0W2+RFR+DW+RTO+F ABD 78131EA86358402B1AD6 3048 DATAA X1 LIT IOR RAM RAM BUSBITS #402B ENAINT BPE+F0W1+DFR+DW+RTO ABE F8131EA8635840FB1AD6 3049 DATAB X1 LIT IOR RAM RAM BUSBITS #40FB ENAINT BPE+SLT+F0W1+F1W2+F0W ABF F8131EA86358400B1AD5 3050 DATAC X1 LIT IOR RAM RAM BUSBITS #400B DISAINT F.D. = 0 + BE AC0 78131E28635840081AC8 3051 DATACA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER slot+DW+RTO AC1 F8131EA86358405B1AD5 3052 DATAD X1 LIT IOR RAM RAM BUSBITS #405B DISAINT F.D. = 1 + BE AC2 78131E28635840081AC8 3053 DATADA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER slot+DW+RTO AC3 78131EA86358402B1AD5 3054 DATAE X1 LIT IOR RAM RAM BUSBITS #402B DISAINT F.D. = 2 + BE AC4 78131E28635840081AC8 3055 DATAEA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER slot+DW+RTO AC5 F8131EA8635840FB1AD5 3056 DATAF X1 LIT IOR RAM RAM BUSBITS #40FB DISAINT FLGS=7+BPE AC6 78131E28635840081AC8 3057 DATAFA X1 LIT XOR RAM RAM BUSBITS #4008 CBXFER BUSBITS + DW + RTO 3058 3059 ***************************************************************************************************** 3060 * If this transfer is to be a callback test, we come here * 3061 * to set up the callback type of bus transfer. * 3062 * Needs 2 stack locations. * 3063 ***************************************************************************************************** 3064 3065 EVEN AC7 4FF31C0063790AC71AC7 3065$ WSTE0077 LIT SCR1F * * ****** wasted ****** 3066 AC8 C8311C006377000F1AC9 3067 CBXFER LIT IMR #000F enable CBN-IBF ints AC9 48B31C00637900001ACA 3068 LIT SCR2 #0000 allow the call back i ACA D8101C0065EA0ACB5ADD 3069 SBHC ZERO SBRFI *+1,P SXFER IBF=0,RFI=0, int retu ACB 48311C00636A00041ACC 3070 LIT SBRFI #0004 set RFI ACC 5AB31C00653900001ACD 3071 SBST SCRA and wait for IBF ACD 5A930E8072FFFFBF1ACF 3072 SCRA IOR LIT #FFBF SKIP *+2 ACE 5AB31C00653900001ACD 3073 SBST SCRA *-1 keep trying ACF 5A930F0072FF00401AD1 3074 SCRA AND LIT #0040 SKIP *+2 IBF? AD0 5A930F0072FF40001AD2 3075 SCRA AND LIT #4000 SKIP *+2 bus error? AD1 48331C0063790AD19EF1 3076 LIT SCR0 * POP STERR no IBF AD2 58301C00633F00009EF1 3077 POP STERR no bus error, no reset AD3 D8311C00633F00001B03 3078 BSRST reset bus error 3079 3080 ODD AD4 4FF31C0063790AD41AD4 3080$ WSTE0078 LIT SCR1F * * ****** wasted ****** 3081 AD5 48B31C006379FFFF1AD7 3082 DISAINT LIT SCR2 #FFFF *+2 say no interrupts AD6 48B31C00637900001AD7 3083 ENAINT LIT SCR2 #0000 allow interrupts AD7 78131F28735F40001AD9 3084 X1 LIT AND RAM BUSBITS #4000 SKIP *+2 set bus error? AD8 48311C00637540001AD9 3085 LIT SBCB #4000 yes AD9 F0301C10635000001ADA 3086 X1 RAM SBHC HW1 load ADA 70301C11635100001ADB 3087 X1 RAM SBLC LW1 all ADB 70301C18634E00001ADC 3088 X1 RAM SBHD HW2 four ADC F0301C1C634F00001ADD 3089 X1 RAM SBLD LW2 words ADD F8101F286355BFFF1ADF 3090 SXFER X1 LIT AND RAM SBCB BUSBITS #BFFF INTLOOP start xfr w/o FBPE 3091 3092 ODD ADE 4FF31C0063790ADE1ADE 3092$ WSTE0079 LIT SCR1F * * ****** wasted ****** 3093 ADF 58930E0072FF00001AE0 3094 INTLOOP SCR2 XOR LIT #0000 SKIP allow interrupts? AE0 58301C00633F00009EF1 3095 POP STERR no AE1 58311C00633F00001AE2 3096 NOP 2 ticks (total of 6 t AE2 5AB31C00653900001AE3 3097 SBST SCRA and wait for IBF or C AE3 5A930E8072FFFBBF1AE5 3098 SCRA IOR LIT #FBBF SKIP *+2 AE4 5AB31C00653900001AE3 3099 SBST SCRA *-1 keep trying 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 169 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test AE5 D8311C00633F00001AE6 3100 NOP (for alignment) AE6 D8311C00633F00003AE7 3101 I awaaaayyyy weeee gooo AE7 58930E0072FF00001AE9 3102 SCR2 XOR LIT #0000 SKIP *+2 have we interrupted? AE8 48331C0063790AE89EF1 3103 LIT SCR0 * POP STERR no AE9 58301C00633F00009EF1 3104 POP STERR yes 3105 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 170 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 3107 3108 BLOCK 4,PINTRTNIOR 3109 >>>>>>>>>>>>>>>>>>>>> DF8 4A731C006379C0DE1AEA 3110 >PINTRTN LIT SCR9 #C0DE PINTSUB DF9 4A731C00637911111AEA 3111 > LIT SCR9 #1111 PINTSUB DFA 4A731C00637922221AEA 3112 > LIT SCR9 #2222 PINTSUB DFB 4A731C00637933331AEA 3113 > LIT SCR9 #3333 PINTSUB 3114 >>>>>>>>>>>>>>>>>>>>> 3115 ENDBLOCK 3116 0AEA 3117 PINTSUB EQU * AEA C8311C006377003F1AEB 3118 LIT IMR #003F shut 'em off AEB FA130E0572DF00001AED 3119 X1 SCR8 XOR RAM VECTCK #0000 SKIP *+2 to the correct vecto AEC 78131E07735F00001AEE 3120 X1 LIT XOR RAM PTFULL #0000 SKIP *+2 IBF or port int? AED 48331C0063790AED1AEF 3121 LIT SCR0 * *+2 wrong vector address AEE FA530E0472DF00001AF0 3122 X1 SCR9 XOR RAM PINTCK #0000 SKIP *+2 did expected port int AEF C8B31C006379FFFF9EF1 3123 LIT SCR2 #FFFF POP STERR IBF, return AF0 48331C0063790AF01AEF 3124 LIT SCR0 * *-1 wrong port AF1 58313C0065EB00001AF2 3125 C SBHC DPOUT AF2 58331C00666B00001AF3 3126 T4 SBLC DPOUT AF3 D8311C0066EB00001AF4 3127 SBHD DPOUT AF4 58311C00676B00001AF5 3128 SBLD DPOUT AF5 58311C00633F00001AF6 3129 NOP AF6 C8B37C006379FFFF1AF7 3130 STC,C LIT SCR2 #FFFF say we interrupted AF7 18139C86635800049EF1 3131 TWC,CST LIT RSUB RAM RAM WDCNT #0004 POP STERR WDCNT-4 3132 3133 ODD AF8 4FF31C0063790AF81AF8 3133$ WSTE0080 LIT SCR1F * * ****** wasted ****** 3134 AF9 7A130E0572DF00001AFB 3135 CBRTN X1 SCR8 XOR RAM VECTCK #0000 SKIP *+2 correct int vector? AFA C8331C00637900001AFC 3136 LIT SCR0 #0000 *+2 yes AFB 48331C0063790AFB1AFC 3137 LIT SCR0 * no AFC 48311C006377003F1AFD 3138 LIT IMR #003F shut em off AFD C8B31C006379FFFF9EF1 3139 LIT SCR2 #FFFF POP STERR return 3140 AFE C8311C006377003F1AFF 3141 BSERTN LIT IMR #003F shut em off AFF FA130E0572DF00001B01 3142 X1 SCR8 XOR RAM VECTCK #0000 SKIP *+2 correct int vector? B00 C8331C00637900001B02 3143 LIT SCR0 #0000 *+2 yes B01 C8331C0063790B011B02 3144 LIT SCR0 * no B02 C8B31C006379FFFF1B03 3145 LIT SCR2 #FFFF B03 58331C00633B00001B04 3146 BSRST T4 SBRST B04 D8311C00633F00001B05 3147 NOP B05 48301C00637500009EF1 3148 LIT SBCB #0000 POP STERR 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 171 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST interrupt test 3150 * SCR1 = direction bit coming in, SCR2 = port # 3 decremented to 0 3151 * SCR0 = 0 = port status good 3152 3153 EVEN 3154 B06 C8B31C00637900031B0A 3155 RESET LIT SCR2 #0003 RESET1 set counter for 4 por B07 58130E0072FF00001B08 3156 RESET1A SCR0 XOR LIT #0000 SKIP check for any error B08 58301C00633F00009EF1 3157 POP STERR go report error B09 D8930D8072F9FFFF1B0A 3158 SCR2 ADD LIT SCR2 #FFFF SKIP count port counter B0A C8B00C0062ED0B075B0C 3159 RESET1 SCR2 INDX2 RESET1A,P RESET2 B0B 58301C00633F00009EF1 3160 POP STERR return, all ports done 3161 3162 EVEN 3163 B0C 48710C0062F600001B0D 3164 RESET2 SCR1 DPDIR set direction B0D D8311C00632300001B0E 3165 DPRST reset FIFOs B0E 58331C00633F00001B0F 3166 T4 TICK B0F D8331C00633F00001B10 3167 T4 TOCK B10 D8311C00633F00001B11 3168 T2 TICK B11 C8311C00636300011B12 3169 LIT DPRST DPRST1IN TOCK B12 48301C00637F00011B13 3170 T3 LIT DPRST1IN (constant for DPRST) B13 58331C00633F00001B14 3171 T4 clock in the status B14 58331C00613900001B15 3172 PTST SCR0 and pull it B15 58530E8072FFFFFE1B17 3173 SCR1 IOR LIT #FFFE SKIP *+2 direction in? B16 D8130F0072FF08001B18 3174 SCR0 AND LIT #0800 SKIP *+2 in,int off? B17 D8130E8072FFF7FF1B18 3175 SCR0 IOR LIT #F7FF SKIP out,int on? B18 C8331C0063790B189EF1 3176 LIT SCR0 * POP STERR return with SCR0 = ec B19 48331C00637900009EF1 3177 LIT SCR0 0 POP STERR no errors 3178 TITLE.MAC PPU5 SELFTEST PTST PON bit test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 172 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST PTST PON bit test 3179 ***************************************************************************************************** 3180 * * 3181 * If that is all okay, then the controller's PON+ signals are * 3182 * asserted by storing #00F0 into DPOE. Then all the port's PON * 3183 * bits in PTST are checked to see if they got set. * 3184 * * 3185 * No test after this should assert bus error (unless test fails) * 3186 * since this test lets the controllers go and in PPU5 the PFW signal * 3187 * to the controllers is the logical OR of BSE and PFW from the VRA * 3188 * bus. No other board on the system should assert BSE after this * 3189 * routine executes. * 3190 * * 3191 ***************************************************************************************************** 3192 3193 ODD B1A 4FF31C0063790B1A1B1A 3193$ WSTE0081 LIT SCR1F * * ****** wasted ****** 3194 B1B 58130E0072FF00001B1C 3195 RSTSTCH SCR0 XOR LIT 0 SKIP status okay? B1C D8311C00633F00001C54 3196 ERRTN no, status error B1D C8731C00637900031B22 3197 LIT SCR1 3 PONCHECK initialize port count 3198 3199 EVEN 3200 B1E D8B31C00613900001B1F 3201 PONCHECK4 X2 PTST SCR2 get port status B1F D8930F0072F940001B20 3202 SCR2 AND LIT SCR2 #4000 SKIP PON bit set? 3203 3204 >>>>>>>>>>>>>>>>>>>>> B20 48331C0063790B201C54 3205 > LIT SCR0 * ERRTN no,error B21 D8530D8072F9FFFF1B22 3206 > SCR1 ADD LIT SCR1 -1 SKIP yes,done? 3207 >>>>>>>>>>>>>>>>>>>>> 3208 3209 >>>>>>>>>>>>>>>>>>>>> B22 C8710C0062ED00001B1E 3210 >PONCHECK SCR1 INDX2 PONCHECK4 no, next port B23 58311C00633F00001B4C 3211 > TSTFLAGS DONE,next test 3212 >>>>>>>>>>>>>>>>>>>>> 3213 TITLE.MAC PPU5 SELFTEST -- Routine to do transfers and check status and data 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 173 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Routine to do transfers and check status an 3214 ***************************************************************************************************** 3215 * * 3216 * This routine is used to actually do the bus transfers and check * 3217 * the results. If you just want to check the results of a completed * 3218 * transfer, you may call this subroutine at the address TSTCHKXFER. * 3219 * * 3220 * You should put the control bits you want for SBCB in SCR1. This * 3221 * routine will IOR it with the proper slot number in ram BUSBITS when * 3222 * it outputs to SBCB. * 3223 * * 3224 * You should put into SCR2 what you want to be stored into SBRFI. * 3225 * If SCR2 is non-zero, this routine will start the transfer and make * 3226 * sure CBN and RTO get set properly before it sets SBRFI. * 3227 * * 3228 * This routine uses registers 4 through A to read in status and check it. * 3229 * Expected SBST status should be put in ram EXSTAT. * 3230 * Expected SBFT status should be put in ram EXSTAT2. * 3231 * Expected SBHC result should be put in ram HW1. * 3232 * Expected SBLC result should be put in ram LW1. * 3233 * Expected SBHD result should be put in ram HW2. * 3234 * Expected SBLD result should be put in ram LW2. * 3235 * * 3236 * The subroutine will check bit 7 of ram EXSTAT to see if it * 3237 * should really check the lower words of data, in case a single word * 3238 * transfer is called for. * 3239 * * 3240 * This routine does not change SCR0 if there is no error. If * 3241 * there is an error, it puts an error code in SCR0. * 3242 * * 3243 ***************************************************************************************************** 3244 B24 58500EA862D500001B25 3245 TSTDOXFERCHK SCR1 IOR RAM SBCB BUSBITS start xfer B25 D8930E8072FF00001B27 3246 SCR2 IOR LIT 0 SKIP TSTXFERRFI will we use RFI? 3247 EVEN 3248 >>>>>>>>>>>>>>>>>>>>> B26 58311C00633F00001B32 3249 > TSTXFERNOTIBF no,RFR,go wait f B27 58331C00633F00001B28 3250 >TSTXFERRFI T4 yes,RFI,delay 3251 >>>>>>>>>>>>>>>>>>>>> B28 D8331C00633F00001B29 3252 T4 B29 D8331C00633F00001B2A 3253 T4 B2A 58331C00633F00001B2B 3254 T4 B2B D8331C00633F00001B2C 3255 T4 B2C D9331C00653900001B2D 3256 SBST SCR4 get bus status B2D D9130F0072FF0C001B2E 3257 SCR4 AND LIT #0C00 SKIP CBN and RTO set? 3258 >>>>>>>>>>>>>>>>>>>>> B2E C8331C0063790B2E9EF1 3259 > LIT SCR0 * POP STERR no, bad status B2F C8B10C0062EA00001B32 3260 > SCR2 SBRFI TSTXFERNOTIBF yes,set RFI,wait 3261 >>>>>>>>>>>>>>>>>>>>> 3262 3263 ODD B30 4FF31C0063790B301B30 3263$ WSTE0082 LIT SCR1F * * ****** wasted ****** B31 D9130F0072FF00401B32 3264 SCR4 AND LIT #0040 SKIP TSTXFERNOTIBF IBF set yet? 3265 >>>>>>>>>>>>>>>>>>>>> B32 59331C00653900001B31 3266 >TSTXFERNOTIBF SBST SCR4 *-1 no,get status B33 D8331C00633F00001B34 3267 > T4 yes 3268 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 174 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- Routine to do transfers and check status an B34 D9331C00653900001B35 3270 TSTCHKXFER SBST SCR4 B35 59731C0065F900001B36 3271 SBHC SCR5 B36 59B31C00667900001B37 3272 SBLC SCR6 B37 59F31C00653900001B38 3273 SBST SCR7 B38 DA331C0066F900001B39 3274 SBHD SCR8 B39 5A731C00677900001B3A 3275 SBLD SCR9 B3A DAB31C0067B900001B3B 3276 SBFT SCRA TSTXFER2 3277 3278 ODD B3B 59130E2072DF00001B3C 3279 TSTXFER2 SCR4 XOR RAM EXSTAT #0000 SKIP status ok? B3C C8331C0063790B3C9EF1 3280 LIT SCR0 * POP STERR bad B3D 59530E1072DF00001B3E 3281 SCR5 XOR RAM HW1 #0000 SKIP data ok? B3E 48331C0063790B3E9EF1 3282 LIT SCR0 * POP STERR bad B3F D9930E1172DF00001B40 3283 SCR6 XOR RAM LW1 #0000 SKIP data ok? B40 48331C0063790B409EF1 3284 LIT SCR0 * POP STERR bad B41 59D30E8072FFFBFF1B42 3285 SCR7 IOR LIT #FBFF SKIP IBF cleared by SBHC? B42 C8331C0063790B429EF1 3286 LIT SCR0 * POP STERR bad B43 5A930E2472DF00001B44 3287 SCRA XOR RAM EXSTAT2 #0000 SKIP status ok? B44 C8331C0063790B449EF1 3288 LIT SCR0 * POP STERR bad B45 D8131F20735F00801B46 3289 LIT AND RAM EXSTAT #0080 SKIP check second data wor B46 58301C00633F00009EF1 3290 POP STERR no return now B47 DA130E1872DF00001B48 3291 SCR8 XOR RAM HW2 #0000 SKIP data ok? B48 C8331C0063790B489EF1 3292 LIT SCR0 * POP STERR bad B49 5A530E1C72DF00001B4A 3293 SCR9 XOR RAM LW2 #0000 SKIP data ok? B4A 48331C0063790B4A9EF1 3294 LIT SCR0 * POP STERR bad B4B 58301C00633F00009EF1 3295 POP STERR return 3296 TITLE.MAC PPU5 SELFTEST flag checks 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 175 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST flag checks 3297 ***************************************************************************************************** 3298 * * 3299 * This section does double and triple word transfers to check all * 3300 * the flag states. Ram TESTTEMP is used to store the various flag * 3301 * states. * 3302 * * 3303 ***************************************************************************************************** 3304 B4C C8331C20637880C01B4D 3305 TSTFLAGS LIT RAM EXSTAT #80C0 exp status=PFW,DW,IBF B4D 58131F2863580F001B4E 3306 LIT AND RAM RAM BUSBITS #0F00 we only want the slot B4E 50731C08635900001B4F 3307 RAM SCR1 ID set up EXSTAT2 B4F C8730C2462F800001B50 3308 SCR1 RAM EXSTAT2 B50 C83B1C2C637900001B51 3309 LIT SCR0,R TESTTEMP 0 clear flags 'OUT' and B51 C83B1C10637011111B52 3310 LIT SBHC,R HW1 #1111 hi word = #1111 B52 483B1C11637122221B53 3311 LIT SBLC,R LW1 #2222 lo word = #2222 B53 483B1C18636E44441B54 3312 LIT SBHD,R HW2 #4444 hi data word = #4444 B54 C83B1C1C636F88881B56 3313 LIT SBLD,R LW2 #8888 TSTFLAGS1 lo data word = #8888 B55 D8530EA062D800001B56 3314 TSTFLAGS0 SCR1 IOR RAM RAM EXSTAT set up expected status B56 C8B31C00637900041B57 3315 TSTFLAGS1 LIT SCR2 #0004 set SBRFI flag for TS B57 58531EAC635900031B58 3316 LIT IOR RAM SCR1 TESTTEMP #0003 flags+DW+RTO to SCR1 B58 58301C00633F0B595B24 3317 TSTFLAGS2,P TSTDOXFERCHK go do XFER 3318 3319 ODD B59 D8130E0072FF00001B5A 3320 TSTFLAGS2 SCR0 XOR LIT 0 SKIP any errors? B5A D8311C00633F00001C54 3321 ERRTN yes,do error return 3322 B5B 58131DAC635800101B5C 3323 LIT ADD RAM RAM TESTTEMP #0010 flags 'OUT' + 1 B5C 58131F2C735F01001B5F 3324 LIT AND RAM TESTTEMP #0100 SKIP TSTFLAGS4 done this trash? 3325 EVEN B5D 4FF31C0063790B5D1B5D 3325$ WSTE0083 LIT SCR1F * * ****** wasted ****** 3326 >>>>>>>>>>>>>>>>>>>>> B5E D8311C00633F00001B69 3327 > TSTFLAGSTW next test B5F 58301C00633F0B555B60 3328 >TSTFLAGS4 TSTFLAGS0,P TSTFLAGS5 next set of flags 3329 >>>>>>>>>>>>>>>>>>>>> 3330 3331 B60 58131F206358CFCF1B61 3332 TSTFLAGS5 LIT AND RAM RAM EXSTAT #CFCF bits 13&12,4&5=0 B61 58531F2C635900C01B62 3333 LIT AND RAM SCR1 TESTTEMP #00C0 7&6 to SCR1 B62 C9F31C00637900061B63 3334 LIT SCR7 #0006 loop counter B63 C8730C0062F800001B65 3335 SCR1 RAM #00 TSTFLAGSLOOP set up for 3336 ODD B64 4FF31C0063790B641B64 3336$ WSTE0084 LIT SCR1F * * ****** wasted ****** B65 D9D30D8072F9FFFF1B66 3337 TSTFLAGSLOOP SCR7 ADD LIT SCR7 #FFFF SKIP 7&6 now 13&12? B66 585B0D8062D900001B65 3338 SCR1 ADD RAM SCR1,R TSTFLAGSLOOP not yet B67 58530EACE2D900001B68 3339 SCR1 IOR,X RAM SCR1 TESTTEMP 13&12 swap with 5&4 B68 58530F0062F930309EF1 3340 SCR1 AND LIT SCR1 #3030 POP STERR clr xtra bits 14&15,r 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 176 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST flag checks B69 48331C2C637800001B6A 3342 TSTFLAGSTW LIT RAM TESTTEMP 0 clear flags 'OUT' B6A 48331C20637880C01B6B 3343 LIT RAM EXSTAT #80C0 exp status=PFW,DW,IBF B6B 48301C00637011111B6C 3344 LIT SBHC #1111 hi word = #1111 B6C 48301C00637122221B6D 3345 LIT SBLC #2222 lo word = #2222 B6D C83B1C10636E44441B6E 3346 LIT SBHD,R HW1 #4444 hi data word = #4444 B6E 483B1C11636F88881B6F 3347 LIT SBLD,R LW1 #8888 lo data word = #8888 B6F 483B1C18636877771B70 3348 LIT SBHW3,R HW2 #7777 hi data word = #7777 B70 483B1C1C6369DDDD1B73 3349 LIT SBLW3,R LW2 #DDDD TSTFLAGS9 lo data word = #DDDD B71 58530E80C2F900001B72 3350 TSTFLAGS6 SCR1 IOR,X LIT SCR1,H 0 copy 5&4 into 13&12 B72 58530EA062D800001B73 3351 SCR1 IOR RAM RAM EXSTAT set up expected status B73 48B31C00637900041B74 3352 TSTFLAGS9 LIT SCR2 #0004 set SBRFI flag for TS B74 D8301C00632700001B75 3353 TWDTST enable 3 word test B75 D8531EAC635910031B76 3354 LIT IOR RAM SCR1 TESTTEMP #1003 flags+TW+DW+RTO to SC B76 58301C00633F0B775B24 3355 TSTFLAGS7,P TSTDOXFERCHK go do xfer 3356 3357 ODD B77 D8130E0072FF00001B78 3358 TSTFLAGS7 SCR0 XOR LIT 0 SKIP any errors? B78 D8311C00633F00001C54 3359 ERRTN yes,do error return 3360 B79 D8131DAC635800101B7A 3361 LIT ADD RAM RAM TESTTEMP #0010 flags 'OUT' + 1 B7A 58131F2C735F01001B7D 3362 LIT AND RAM TESTTEMP #0100 SKIP TSTFLAGS8 done this trash? 3363 EVEN B7B 4FF31C0063790B7B1B7B 3363$ WSTE0085 LIT SCR1F * * ****** wasted ****** 3364 >>>>>>>>>>>>>>>>>>>>> B7C D8311C00633F00001B7E 3365 > TSTBUSDATA next test B7D 58301C00633F0B715B60 3366 >TSTFLAGS8 TSTFLAGS6,P TSTFLAGS5 next set of flags 3367 >>>>>>>>>>>>>>>>>>>>> 3368 TITLE.MAC PPU5 SELFTEST Superbus data test 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 177 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test 3369 ***************************************************************************************************** 3370 * * 3371 * The purpose of this test is to test out the superbus data * 3372 * registers. This test does transfers both with RFI set and RFR clear * 3373 * and with RFI clear and RFR set. * 3374 * * 3375 * Register usage * 3376 * SCR1 -- SBCB control bits not including slot number * 3377 * SCR2 -- bit 2 is what TSTDOXFERCHK should put in SBRFI. * 3378 * TSTDOXFERCHK will check status to make sure CBN and * 3379 * RTO are set before storing SCR2 into SBRFI if SCR2 <> 0. * 3380 * SCR10 -- ending pattern for floating zeros pattern * 3381 * (used to check lowest 16 bit word) * 3382 * SCR11 -- used for temporary storage * 3383 * SCR12 -- used for temporary storage * 3384 * SCR13 -- used for temporary storage * 3385 * SCR14 -- used for temporary storage * 3386 * SCR15 -- used to store into SBRFI before TSTDOXFERCHK is called. * 3387 * RAM TESTTEMP -- used to decide what is to be used for SBCB. * 3388 * * 3389 * This set of 6 tests is run through 3 times. The first time, * 3390 * SCR2=SCR15=0 and the correct RFR bits are set in SBCB. This tests * 3391 * the RFR function. In the second time through the 6 tests, SCR2=0, * 3392 * SCR15=4, and RFR is not used. This makes sure that the RFI function * 3393 * works if RFI is set before the transfer is initiated with SBCB. In * 3394 * the third time through the 6 tests, SCR2=4, SCR15=0, and RFR is not * 3395 * used. This causes the transfer to be initiated (with SBCB) before * 3396 * RFI is set. There will be a short delay after SBCB, Then * 3397 * TSTDOXFERCHK will check to make sure CBN and RTO are both set in * 3398 * SBST. If this is true, the transfer will be completed by setting * 3399 * RFI. This third set of tests checks to make sure call back transfers * 3400 * work. * 3401 * * 3402 ***************************************************************************************************** 3403 3404 B7E CC331C006379FFFE1B7F 3405 TSTBUSDATA LIT SCR10 #FFFE end pattern for float B7F 48331C2C6378100F1B80 3406 LIT RAM TESTTEMP #100F SBCB initial control B80 C8B31C00637900001B81 3407 LIT SCR2 0 start with delayed RF B81 CD731C00637900001B82 3408 LIT SCR15 0 clear SCR15,no RFI be 3409 3410 B82 C8331C20637880401B83 3411 TSTBUSDATA0 LIT RAM EXSTAT #8040 stat=PFW- and IBF B83 D8531F2C635900091B84 3412 LIT AND RAM SCR1 TESTTEMP #0009 mask allowable bits f 3413 3414 ***************************************************************************************************** 3415 * First set is one word transfers with pattern of 31 ones and 1 zero * 3416 ***************************************************************************************************** 3417 B84 C8301C00636E00001B85 3418 LIT SBHD 0 clear this reg. B85 48301C00636F00001B86 3419 LIT SBLD 0 clear this reg. B86 48301C00636800001B87 3420 LIT SBHW3 0 clear this reg. B87 C8301C00636900001B88 3421 LIT SBLW3 0 clear this reg. B88 C8331C106378FFFF1B89 3422 LIT RAM HW1 #FFFF init floating B89 C8331C116378FFFE1B8A 3423 LIT RAM LW1 #FFFE zero pattern B8A D8301C00633F0B8F5B8B 3424 TSTBUSDATA1 TSTBUSDATA2,P push return address B8B D0301C10635000001B8C 3425 TSTBUSDATA3 RAM SBHC HW1 output hi word 1 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 178 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test B8C 50301C11635100001B8D 3426 RAM SBLC LW1 output lo word 1 B8D 4D710C0062EA00001B24 3427 SCR15 SBRFI TSTDOXFERCHK clr or set RFI,do 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 179 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test 3429 ODD B8E 4FF31C0063790B8E1B8E 3429$ WSTE0086 LIT SCR1F * * ****** wasted ****** B8F D8130E0072FF00001B90 3430 TSTBUSDATA2 SCR0 XOR LIT 0 SKIP error from xfer? 3431 >>>>>>>>>>>>>>>>>>>>> B90 D8311C00633F00001C54 3432 > ERRTN yes B91 58311C00633F00001B92 3433 > NOP no 3434 >>>>>>>>>>>>>>>>>>>>> B92 D4731C11635900001B93 3435 RAM SCR11 LW1 lo word 1 to SCR11 B93 D4B31C10635900001B94 3436 RAM SCR12 HW1 hi word 1 to SCR12 B94 5C538D9162D800001B95 3437 CST SCR11 ADD RAM RAM LW1 shift B95 1C938D9062D800001B96 3438 TWC,CST SCR12 ADD RAM RAM HW1 data B96 18131D91635800001B97 3439 TWC LIT ADD RAM RAM LW1 0 left 1 bit B97 5C130E1172DF00001B98 3440 SCR10 XOR RAM LW1 0 SKIP lo=FFFE? B98 58311C00633F00001B8A 3441 TSTBUSDATA1 no,loop 3442 3443 ***************************************************************************************************** 3444 * Second set is one word transfers with pattern of 31 zeros and 1 one * 3445 ***************************************************************************************************** 3446 B99 48331C10637800001B9A 3447 LIT RAM HW1 0000 initial floating B9A C8331C11637800011B9B 3448 LIT RAM LW1 0001 1 pattern B9B D8301C00633F0B9D5B8B 3449 TSTBUSDATA4 TSTBUSDATA5,P TSTBUSDATA3 go do xfer 3450 3451 ODD B9C 4FF31C0063790B9C1B9C 3451$ WSTE0087 LIT SCR1F * * ****** wasted ****** B9D 58130E0072FF00001B9E 3452 TSTBUSDATA5 SCR0 XOR LIT 0 SKIP error from xfer? 3453 >>>>>>>>>>>>>>>>>>>>> B9E D8311C00633F00001C54 3454 > ERRTN yes B9F D4731C11635900001BA0 3455 > RAM SCR11 LW1 lo word 1 to SCR11 3456 >>>>>>>>>>>>>>>>>>>>> BA0 D4B31C10635900001BA1 3457 RAM SCR12 HW1 hi word 1 to SCR12 BA1 DC538D9172D800001BA3 3458 CST SCR11 ADD RAM RAM LW1 #0000 SKIP *+2 shift data BA2 9C930D9072D800001BA4 3459 TWC SCR12 ADD RAM RAM HW1 #0000 SKIP *+2 left 1 bit BA3 58311C00633F00001B9B 3460 TSTBUSDATA4 not done,loop BA4 58311C00633F00001B9B 3461 TSTBUSDATA4 not done,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 180 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test BA5 D8531F2C6359000F1BA6 3463 LIT AND RAM SCR1 TESTTEMP #000F mask correct SBCB bit BA6 48331C20637880C01BA7 3464 LIT RAM EXSTAT #80C0 bus stat=PFW-,IBF,DW 3465 3466 ***************************************************************************************************** 3467 * Third set is double word transfers with floating pattern of 63 ones * 3468 * and 1 zero * 3469 ***************************************************************************************************** 3470 BA7 C8301C00636800001BA8 3471 LIT SBHW3 0 clear this reg. BA8 C8301C00636900001BA9 3472 LIT SBLW3 0 clear this reg. BA9 48331C106378FFFF1BAA 3473 LIT RAM HW1 #FFFF initialize BAA 48331C116378FFFF1BAB 3474 LIT RAM LW1 #FFFF floating BAB C8331C186378FFFF1BAC 3475 LIT RAM HW2 #FFFF zero BAC 48331C1C6378FFFE1BAD 3476 LIT RAM LW2 #FFFE pattern BAD 58301C00633F0BB35BAE 3477 TSTBUSDATA12 TSTBUSDATA14,P push return address BAE 50301C10635000001BAF 3478 TSTBUSDATA13 RAM SBHC HW1 output hi word 1 BAF D0301C11635100001BB0 3479 RAM SBLC LW1 output lo word 1 BB0 D0301C18634E00001BB1 3480 RAM SBHD HW2 output hi word 2 BB1 D0301C1C634F00001BB2 3481 RAM SBLD LW2 output lo word 2 BB2 4D710C0062EA00001B24 3482 SCR15 SBRFI TSTDOXFERCHK clr or set RFI,do 3483 3484 ODD BB3 D8130E0072FF00001BB4 3485 TSTBUSDATA14 SCR0 XOR LIT 0 SKIP error from xfer? 3486 >>>>>>>>>>>>>>>>>>>>> BB4 D8311C00633F00001C54 3487 > ERRTN yes BB5 58311C00633F00001BB6 3488 > NOP no 3489 >>>>>>>>>>>>>>>>>>>>> BB6 54731C1C635900001BB7 3490 RAM SCR11 LW2 lo word 2 to SCR11 BB7 D4B31C18635900001BB8 3491 RAM SCR12 HW2 hi word 2 to SCR12 BB8 D4F31C11635900001BB9 3492 RAM SCR13 LW1 lo word 1 to SCR13 BB9 D5331C10635900001BBA 3493 RAM SCR14 HW1 hi word 1 to SCR14 BBA DC538D9C62D800001BBB 3494 CST SCR11 ADD RAM RAM LW2 shift BBB 1C938D9862D800001BBC 3495 TWC,CST SCR12 ADD RAM RAM HW2 data BBC 1CD38D9162D800001BBD 3496 TWC,CST SCR13 ADD RAM RAM LW1 left BBD 1D138D9062D800001BBE 3497 TWC,CST SCR14 ADD RAM RAM HW1 one BBE 98131D9C635800001BBF 3498 TWC LIT ADD RAM RAM LW2 0 bit BBF 5C130E1C72DF00001BC0 3499 SCR10 XOR RAM LW2 0 SKIP lo=FFFE? BC0 58311C00633F00001BAD 3500 TSTBUSDATA12 no,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 181 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test 3502 ***************************************************************************************************** 3503 * Fourth set is double word transfers with floating pattern of 63 zeros * 3504 * and 1 one * 3505 ***************************************************************************************************** 3506 BC1 C8331C10637800001BC2 3507 LIT RAM HW1 0000 initialize BC2 C8331C11637800001BC3 3508 LIT RAM LW1 0000 floating BC3 48331C18637800001BC4 3509 LIT RAM HW2 0000 ones BC4 C8331C1C637800011BC5 3510 LIT RAM LW2 0001 pattern BC5 58301C00633F0BC75BAE 3511 TSTBUSDATA15 TSTBUSDATA16,P TSTBUSDATA13 go do xfer 3512 3513 ODD BC6 4FF31C0063790BC61BC6 3513$ WSTE0088 LIT SCR1F * * ****** wasted ****** BC7 58130E0072FF00001BC8 3514 TSTBUSDATA16 SCR0 XOR LIT 0 SKIP error from xfer? 3515 >>>>>>>>>>>>>>>>>>>>> BC8 D8311C00633F00001C54 3516 > ERRTN yes BC9 54731C1C635900001BCA 3517 > RAM SCR11 LW2 lo word 2 to SCR11 3518 >>>>>>>>>>>>>>>>>>>>> BCA 54B31C18635900001BCB 3519 RAM SCR12 HW2 hi word 2 to SCR12 BCB 54F31C11635900001BCC 3520 RAM SCR13 LW1 lo word 1 to SCR13 BCC D5331C10635900001BCD 3521 RAM SCR14 HW1 hi word 1 to SCR14 BCD 5C538D9C62D800001BCE 3522 CST SCR11 ADD RAM RAM LW2 shift BCE 9C938D9862D800001BCF 3523 CST,TWC SCR12 ADD RAM RAM HW2 data BCF 9CD38D9162D800001BD0 3524 CST,TWC SCR13 ADD RAM RAM LW1 1 bit BD0 1D138D9062D800001BD1 3525 CST,TWC SCR14 ADD RAM RAM HW1 to the BD1 18131D9C635800001BD2 3526 TWC LIT ADD RAM RAM LW2 #0000 left (add car BD2 58131F1C735F00011BD4 3527 LIT AND RAM LW2 0001 SKIP TSTBUSDATA17 done? 3528 EVEN BD3 4FF31C0063790BD31BD3 3528$ WSTE0089 LIT SCR1F * * ****** wasted ****** BD4 D8311C00633F00001BC5 3529 TSTBUSDATA17 TSTBUSDATA15 not done,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 182 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test BD5 D8531F2C6359100F1BD6 3531 LIT AND RAM SCR1 TESTTEMP #100F mask correct SBCB bit BD6 C8331C20637880C01BD7 3532 LIT RAM EXSTAT #80C0 bus stat=PFW-,IBF,DW 3533 3534 ***************************************************************************************************** 3535 * Fifth set is triple word transfers with floating pattern of 63 ones * 3536 * and 1 zero in last two words, zero in first word * 3537 ***************************************************************************************************** 3538 BD7 48301C00637000001BD8 3539 LIT SBHC 0 clear this reg. BD8 48301C00637100001BD9 3540 LIT SBLC 0 clear this reg. BD9 C8331C106378FFFF1BDA 3541 LIT RAM HW1 #FFFF initialize BDA C8331C116378FFFF1BDB 3542 LIT RAM LW1 #FFFF floating BDB 48331C186378FFFF1BDC 3543 LIT RAM HW2 #FFFF zero BDC C8331C1C6378FFFE1BDD 3544 LIT RAM LW2 #FFFE pattern BDD D8301C00633F0BE55BDE 3545 TSTBUSDATA22 TSTBUSDATA24,P push return address BDE D0301C10634E00001BDF 3546 TSTBUSDATA23 RAM SBHD HW1 output hi word 2 BDF D0301C11634F00001BE0 3547 RAM SBLD LW1 output lo word 2 BE0 D0301C18634800001BE1 3548 RAM SBHW3 HW2 output hi word 3 BE1 D0301C1C634900001BE2 3549 RAM SBLW3 LW2 output lo word 3 BE2 D8301C00632700001BE3 3550 TWDTST set triple word test BE3 4D710C0062EA00001B24 3551 SCR15 SBRFI TSTDOXFERCHK clr or set RFI,do 3552 3553 ODD BE4 4FF31C0063790BE41BE4 3553$ WSTE0090 LIT SCR1F * * ****** wasted ****** BE5 58130E0072FF00001BE6 3554 TSTBUSDATA24 SCR0 XOR LIT 0 SKIP error from xfer? 3555 >>>>>>>>>>>>>>>>>>>>> BE6 D8311C00633F00001C54 3556 > ERRTN yes BE7 D8311C00633F00001BE8 3557 > NOP no 3558 >>>>>>>>>>>>>>>>>>>>> BE8 D4731C1C635900001BE9 3559 RAM SCR11 LW2 lo word 2 to SCR11 BE9 54B31C18635900001BEA 3560 RAM SCR12 HW2 hi word 2 to SCR12 BEA 54F31C11635900001BEB 3561 RAM SCR13 LW1 lo word 1 to SCR13 BEB D5331C10635900001BEC 3562 RAM SCR14 HW1 hi word 1 to SCR14 BEC DC538D9C62D800001BED 3563 CST SCR11 ADD RAM RAM LW2 shift BED 9C938D9862D800001BEE 3564 TWC,CST SCR12 ADD RAM RAM HW2 data BEE 9CD38D9162D800001BEF 3565 TWC,CST SCR13 ADD RAM RAM LW1 left BEF 1D138D9062D800001BF0 3566 TWC,CST SCR14 ADD RAM RAM HW1 one BF0 98131D9C635800001BF1 3567 TWC LIT ADD RAM RAM LW2 0 bit BF1 DC130E1C72DF00001BF2 3568 SCR10 XOR RAM LW2 0 SKIP lo=FFFE? BF2 D8311C00633F00001BDD 3569 TSTBUSDATA22 no,loop 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 183 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST Superbus data test 3571 ***************************************************************************************************** 3572 * Sixth set is triple word transfers with floating pattern of 63 zeros * 3573 * and 1 one in last two words, ones in first word. * 3574 ***************************************************************************************************** 3575 BF3 C8301C006370FFFF1BF4 3576 LIT SBHC #FFFF this reg all ones BF4 C8301C006371FFFF1BF5 3577 LIT SBLC #FFFF this reg all ones BF5 48331C10637800001BF6 3578 LIT RAM HW1 0000 initialize BF6 48331C11637800001BF7 3579 LIT RAM LW1 0000 floating BF7 48331C18637800001BF8 3580 LIT RAM HW2 0000 ones BF8 C8331C1C637800011BF9 3581 LIT RAM LW2 0001 pattern BF9 D8301C00633F0BFB5BDE 3582 TSTBUSDATA25 TSTBUSDATA26,P TSTBUSDATA23 go do xfer 3583 3584 ODD BFA 4FF31C0063790BFA1BFA 3584$ WSTE0091 LIT SCR1F * * ****** wasted ****** BFB D8130E0072FF00001BFC 3585 TSTBUSDATA26 SCR0 XOR LIT 0 SKIP error from xfer? 3586 >>>>>>>>>>>>>>>>>>>>> BFC D8311C00633F00001C54 3587 > ERRTN yes BFD D4731C1C635900001BFE 3588 > RAM SCR11 LW2 lo word 2 to SCR11 3589 >>>>>>>>>>>>>>>>>>>>> BFE D4B31C18635900001BFF 3590 RAM SCR12 HW2 hi word 2 to SCR12 BFF D4F31C11635900001C00 3591 RAM SCR13 LW1 hi word 1 to SCR13 C00 55331C10635900001C01 3592 RAM SCR14 HW1 hi word 1 to SCR14 C01 DC538D9C62D800001C02 3593 CST SCR11 ADD RAM RAM LW2 shift C02 1C938D9862D800001C03 3594 CST,TWC SCR12 ADD RAM RAM HW2 data C03 1CD38D9162D800001C04 3595 CST,TWC SCR13 ADD RAM RAM LW1 1 bit C04 9D138D9062D800001C05 3596 CST,TWC SCR14 ADD RAM RAM HW1 to the C05 98131D9C635800001C06 3597 TWC LIT ADD RAM RAM LW2 #0000 left (add car C06 58131F1C735F00011C08 3598 LIT AND RAM LW2 0001 SKIP TSTBUSDATA27 done? 3599 EVEN C07 4FF31C0063790C071C07 3599$ WSTE0092 LIT SCR1F * * ****** wasted ****** 3600 >>>>>>>>>>>>>>>>>>>>> C08 D8311C00633F00001BF9 3601 >TSTBUSDATA27 TSTBUSDATA25 not done,loop C09 58930F0072FF00041C0B 3602 > SCR2 AND LIT #0004 SKIP *+2 done, was SCR2 set? 3603 >>>>>>>>>>>>>>>>>>>>> 3604 3605 >>>>>>>>>>>>>>>>>>>>> C0A 58311C00633F00001C0F 3606 > TSTRFR2SW yes,done,next test C0B DD530F0072FF00041C0C 3607 > SCR15 AND LIT #0004 SKIP no, was SCR15 set? 3608 >>>>>>>>>>>>>>>>>>>>> 3609 3610 >>>>>>>>>>>>>>>>>>>>> C0C C8331C2C637810031C0E 3611 > LIT RAM TESTTEMP #1003 *+2 no,set new SBCB value C0D 48B31C00637900041C0E 3612 > LIT SCR2 #0004 yes,set SCR2 3613 >>>>>>>>>>>>>>>>>>>>> C0E 5D530E0062F900041B82 3614 SCR15 XOR LIT SCR15 #0004 TSTBUSDATA0 invert SCR15 bit 2 3615 TITLE.MAC PPU5 SELFTEST -- RFR2 test with single word transfers 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 184 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RFR2 test with single word transfers 3616 ***************************************************************************************************** 3617 * * 3618 * The purpose of this test is to make sure that the bus logic works * 3619 * for a two word reply when both words are returned separately. We * 3620 * have already tested out the logic for when the two words are sent * 3621 * together. In other words, this test is to check the functioning of * 3622 * the RFR2 logic when the input is actually two single word transfers. * 3623 * This test also tests the interrupt logic to make sure the interrupt * 3624 * is not taken until after the second word is actually received. * 3625 * * 3626 * Some of the register usages: * 3627 * SCR1 -- used for bus status checks * 3628 * SCR2 -- used for checking if correct interrupt did or did not occur * 3629 * SCR10 -- ending pattern for floating zeros pattern * 3630 * (used to check lowest 16 bit word) * 3631 * SCR11 -- used for temporary storage * 3632 * SCR12 -- used for temporary storage * 3633 * SCR13 -- used for temporary storage * 3634 * SCR14 -- used for temporary storage * 3635 * RAM TESTTEMP -- used to hold expected status between two single word xfers. * 3636 * * 3637 * This test is done with normal data flags for all the data words. * 3638 * * 3639 ***************************************************************************************************** 3640 3641 >>>>>>>>>>>>>>>>>>>>> 3642 > VECTOR FB0 48B31C0063790FB09EF1 3643 >TSTRFR2SWVEC LIT SCR2 * POP STERR error if we get here FB1 C8B31C00637900009EF1 3644 > LIT SCR2 0 POP STERR we should get here FB2 C8B31C0063790FB29EF1 3645 > LIT SCR2 * POP STERR error if we get here FB3 48B31C0063790FB39EF1 3646 > LIT SCR2 * POP STERR error if we get here FB4 C8B31C0063790FB49EF1 3647 > LIT SCR2 * POP STERR error if we get here FB5 48B31C0063790FB59EF1 3648 > LIT SCR2 * POP STERR error if we get here FB6 48B31C0063790FB69EF1 3649 > LIT SCR2 * POP STERR error if we get here FB7 C8B31C0063790FB79EF1 3650 > LIT SCR2 * POP STERR error if we get here FB8 C8B31C0063790FB89EF1 3651 > LIT SCR2 * POP STERR error if we get here FB9 48B31C0063790FB99EF1 3652 > LIT SCR2 * POP STERR error if we get here FBA 48B31C0063790FBA9EF1 3653 > LIT SCR2 * POP STERR error if we get here FBB C8B31C0063790FBB9EF1 3654 > LIT SCR2 * POP STERR error if we get here FBC 48B31C0063790FBC9EF1 3655 > LIT SCR2 * POP STERR error if we get here FBD C8B31C0063790FBD9EF1 3656 > LIT SCR2 * POP STERR error if we get here FBE C8B31C0063790FBE9EF1 3657 > LIT SCR2 * POP STERR error if we get here FBF 48B31C0063790FBF9EF1 3658 > LIT SCR2 * POP STERR error if we get here 3659 > ENDVECTOR 3660 >>>>>>>>>>>>>>>>>>>>> 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 185 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RFR2 test with single word transfers C0F 48331C20637890501C10 3662 TSTRFR2SW LIT RAM EXSTAT #9050 expected completion s C10 48331C2C637892501C11 3663 LIT RAM TESTTEMP #9250 expected status betwe C11 C8331C08637A0FB01C12 3664 LIT IADR #20 TSTRFR2SWVEC set interrupt vector C12 48311C00637700001C13 3665 LIT IMR 0 enable all interrupts C13 C8301C00636E00001C14 3666 LIT SBHD 0 zero this output reg C14 C8301C00636F00001C15 3667 LIT SBLD 0 zero this output reg C15 48301C00636800001C16 3668 LIT SBHW3 0 zero this output reg C16 48301C00636900001C17 3669 LIT SBLW3 0 zero this output reg C17 C8331C10637800001C18 3670 LIT RAM HW1 #0000 initial pattern=0000- C18 48331C11637800011C19 3671 LIT RAM LW1 #0001 -0001- C19 C8331C186378FFFF1C1A 3672 LIT RAM HW2 #FFFF -FFFF- C1A 48331C1C6378FFFE1C1B 3673 LIT RAM LW2 #FFFE -FFFE- 3674 C1B C8B31C006379FFFF1C1C 3675 TSTRFR2SW2 LIT SCR2 #FFFF set up SCR2 for test C1C D0301C10635000001C1D 3676 RAM SBHC HW1 output hi word 1 C1D D0301C11635100001C1E 3677 RAM SBLC LW1 output lo word 1 C1E D8101EA86355001D1C1F 3678 LIT IOR RAM SBCB BUSBITS #001D start xfer,RTO,RFR,RF 3679 C1F D8301C00633F0C215C20 3680 *+2,P *+1 wait C20 58321C00633F0000BEF1 3681 IP POP STERR for C21 D8301C00633F0C235C22 3682 *+2,P *+1 IBF C22 58321C00633F0000BEF1 3683 IP POP STERR interrupt C23 D8301C00633F0C255C24 3684 *+2,P *+1 wait C24 58321C00633F0000BEF1 3685 IP POP STERR for C25 D8301C00633F0C275C26 3686 *+2,P *+1 IBF C26 58321C00633F0000BEF1 3687 IP POP STERR interrupt C27 D8301C00633F0C295C28 3688 *+2,P *+1 wait C28 58321C00633F0000BEF1 3689 IP POP STERR for C29 D8301C00633F0C2B5C2A 3690 *+2,P *+1 IBF C2A 58321C00633F0000BEF1 3691 IP POP STERR interrupt 3692 C2B D8930F0072FFFFFF1C2C 3693 SCR2 AND LIT #FFFF SKIP TSTRFR2SW4 was interrupt taken? 3694 3695 EVEN 3696 >>>>>>>>>>>>>>>>>>>>> C2C C8331C0063790C2C1C54 3697 >TSTRFR2SW4 LIT SCR0 * ERRTN yes,error C2D 58731C00653900001C2E 3698 > SBST SCR1 no,SCR1 <- bus status 3699 >>>>>>>>>>>>>>>>>>>>> 3700 C2E D8530E2C72DF00001C30 3701 SCR1 XOR RAM TESTTEMP #0000 SKIP TSTRFR2SW6 RFR still set? 3702 3703 EVEN C2F 4FF31C0063790C2F1C2F 3703$ WSTE0093 LIT SCR1F * * ****** wasted ****** 3704 >>>>>>>>>>>>>>>>>>>>> C30 48331C0063790C301C54 3705 >TSTRFR2SW6 LIT SCR0 * ERRTN no,error C31 D0301C18635000001C32 3706 > RAM SBHC HW2 output hi word 2 3707 >>>>>>>>>>>>>>>>>>>>> 3708 C32 50301C1C635100001C33 3709 RAM SBLC LW2 output lo word 2 C33 58101EA8635500191C34 3710 LIT IOR RAM SBCB BUSBITS #0019 1 word xfer,keep RFR 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 186 PPU/REV 26 microcode *** second half of prom *** UCODE.HRDPP5:SELFTEST.REV26 File# 1 PPU5 SELFTEST -- RFR2 test with single word transfers C34 58301C00633F0C365C35 3712 *+2,P *+1 wait C35 58321C00633F0000BEF1 3713 IP POP STERR for C36 58301C00633F0C385C37 3714 *+2,P *+1 IBF C37 58321C00633F0000BEF1 3715 IP POP STERR interrupt C38 58301C00633F0C3A5C39 3716 *+2,P *+1 wait C39 58321C00633F0000BEF1 3717 IP POP STERR for C3A D8301C00633F0C3C5C3B 3718 *+2,P *+1 IBF C3B 58321C00633F0000BEF1 3719 IP POP STERR interrupt C3C 58301C00633F0C3E5C3D 3720 *+2,P *+1 wait C3D 58321C00633F0000BEF1 3721 IP POP STERR for C3E D8301C00633F0C405C3F 3722 *+2,P *+1 IBF C3F 58321C00633F0000BEF1 3723 IP POP STERR interrupt 3724 C40 58930E8072FF00001C42 3725 SCR2 IOR LIT #0000 SKIP TSTRFR2SW8 was interrupt taken? 3726 3727 EVEN C41 4FF31C0063790C411C41 3727$ WSTE0094 LIT SCR1F * * ****** wasted ****** 3728 >>>>>>>>>>>>>>>>>>>>> C42 48331C0063790C421C54 3729 >TSTRFR2SW8 LIT SCR0 * ERRTN no,error C43 D8301C00633F0C455B34 3730 > TSTRFR2SWA,P TSTCHKXFER yes,go check xfer's 3731 >>>>>>>>>>>>>>>>>>>>> 3732 3733 ODD C44 4FF31C0063790C441C44 3733$ WSTE0095 LIT SCR1F * * ****** wasted ****** C45 D8130E0072FF00001C46 3734 TSTRFR2SWA SCR0 XOR LIT 0 SKIP error from xfer? 3735 >>>>>>>>>>>>>>>>>>>>> C46 D8311C00633F00001C54 3736 > ERRTN yes,return error code C47 D4731C1C635900001C48 3737 > RAM SCR11 LW2 lo word 2 to SCR11 3738 >>>>>>>>>>>>>>>>>>>>> C48 D4B31C18635900001C49 3739 RAM SCR12 HW2 hi word 2 to SCR12 C49 54F31C11635900001C4A 3740 RAM SCR13 LW1 lo word 1 to SCR13 C4A D5331C10635900001C4B 3741 RAM SCR14 HW1 hi word 1 to SCR14 C4B DC538D9C62D800001C4C 3742 CST SCR11 ADD RAM RAM LW2 shift C4C 1C938D9862D800001C4D 3743 CST,TWC SCR12 ADD RAM RAM HW2 data C4D 9CD38D9162D800001C4E 3744 CST,TWC SCR13 ADD RAM RAM LW1 1 bit C4E 1D138D9062D800001C4F 3745 CST,TWC SCR14 ADD RAM RAM HW1 to the C4F 98131D9C635800001C50 3746 TWC LIT ADD RAM RAM LW2 #0000 left (add car C50 5C130E1C72DF00001C52 3747 SCR10 XOR RAM LW2 0000 SKIP TSTRFR2SWC done? 3748 EVEN C51 4FF31C0063790C511C51 3748$ WSTE0096 LIT SCR1F * * ****** wasted ****** 3749 >>>>>>>>>>>>>>>>>>>>> C52 58311C00633F00001C1B 3750 >TSTRFR2SWC TSTRFR2SW2 not done,loop C53 58311C00633F00001C56 3751 > GOODRTN done, End of Selftest 3752 >>>>>>>>>>>>>>>>>>>>> 3753 END 3722 TITLE.MAC SELFTEST RETURN ADDRESSES 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 187 PPU/REV 26 microcode *** second half of prom *** File# 0 SELFTEST RETURN ADDRESSES C54 48311C00637300031C55 3723 ERRTN LIT INDX1 #0003 C55 E8330C2B62F80000143C 3724 X1 SCR0 RAM ERRFLAG ENDTEST bad end of test C56 C8311C00637300031C57 3725 GOODRTN LIT INDX1 #0003 C57 F8131C2A637800001C58 3726 X1 ZERO RAM WRURES4A zero high half of WRU C58 68331C2B63780000143C 3727 X1 LIT RAM ERRFLAG #0000 ENDTEST good end of test 3729 IF ERRFLAG NE WRURES4B, Selftest flags do not match! 0C58 3731 MAXPCHIGH REEQU *-1 maximum PC in high RAM (800-FFF) 3733 IF MAXPCHIGH GE BLOCKORG+16, we've collided with the BLOCK structure 3734 TITLE.MAC PROM Use Parameters & PPU Halts 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 188 PPU/REV 26 microcode *** second half of prom *** File# 0 PROM Use Parameters & PPU Halts 0C70 3735 LEASTBLK EQU BLOCKORG+16 001A 3736 WRDSLEFT EQU SELFTESTSTART-MAXPCLOW+LEASTBLK-MAXPCHIGH 0004 3737 VECTORSLEFT EQU (#1000 - VECTORORG) / 16 3738 0061 3739 SKIPWSTE EQU WSTECNTR-WSTEPNTR 0004 3740 BLK4WSTE EQU (4-B4.USED)*4 0008 3741 BLK8WSTE EQU (2-B8.USED)*8 3742 3743 EXPAND ON 3744 3745 3746 * WORDS remaining = 0026 3747 3748 * VECTORS (16 words each) remaining = 0004 3749 3750 3751 * SKIP waste = 0097 3752 3753 * BLOCK 4 waste = 0004 3754 3755 * BLOCK 8 waste = 0008 3757 ***************************************************************************************************** 3758 * * 3759 * PPU HALT'S * 3760 * * 3761 * The HALT address is put into SCR1F to pass it to the initialization * 3762 * microcode to be included in WRU 14. * 3763 * * 3764 * Most of the halts are actually where they are called now, not * 3765 * here at the end. * 3766 * * 3767 ***************************************************************************************************** 0EF0 3769 ORG #EF0 3770 >>>>>>>>>>>>>>>>>>>>> 3771 >DIDNTPOP HALT POP didn't POP EF0 4FF31C0063790EF01EF0 3771$>DIDNTPOP LIT SCR1F * * POP didn't POP 3772 >STERR HALT BUS Self-test Error EF1 4FF31C0063790EF11EF1 3772$>STERR LIT SCR1F * * BUS Self-test Error 3773 >>>>>>>>>>>>>>>>>>>>> 3775 TITLE.MAC cross-reference table 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 189 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 3776 END No Lines With Errors 53% of available memory used 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 190 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table ABORT 0245 0-2340= 0-2312a ABORTPRT 0247 0-2343= 0-1453a 0-2336a 0-2341a ABTCLR 9A89 0- 923= 0-2312v ABTSET 8080 0- 924= 0-2340v ACK 000E 0- 607= 0-1355v 0-1386v 0-1503v ADATAXOR 0010 0- 822= 0-1557v 0-2195v ADDIR 02F7 0-2791= 0-2316a 0-2318a ADDRESS 0028 0- 483= 0-1477v 0-1490v 0-1554v 0-2192v 0-2298v ALLOWINT 0295 0-2587= 0-2469a 0-2543a 0-2546a 0-2572a B2DODUB 02E4 0-2739= 0-2730a B2LISBIG 02E3 0-2735= 0-2729a B2SINGLE 02E0 0-2729= 0-2726a B4.ORG 0DFC 0-1060= 0-1060 0-1060e 0-1060= 0-1488 0-1488e 0-1488= 0-2142 0-2142e 0-2142= 0-2432 0-2432e 0-2432= 0-2442= 0-2442 0-2442e 0-2442= 0-2505 0-2505e 0-2505= 0-2514 0-2514e 0-2514= 0-2557 0-2557e 0-2557= 0-2687= 0-2687 0-2687e 0-2687= 0-2771 0-2771e 0-2771= 0-3176 0-3176e 0-3176= 0-3316 0-3316e 0-3316= 0-3338= 0-3338 0-3338e 0-3338= 0-3373 0-3373e 0-3373= 0-3621 0-3621e 0-3621= 0-3635 0-3635e 0-3635= 1- 525= 1- 525 1- 525e 1- 525= 1- 534 1- 534e 1- 534= 1- 543 1- 543e 1- 543= 1- 552 1- 552e 1- 552= 1-1316= 1-1316 1-1316e 1-1316= 1-1929 1-1929e 1-1929= 1-3108 1-3108e 1-3108= B4.USED 0003 0- 387= 0-1060 0-1060= 0-1060e 0-1060e 0-1060= 0-1488 0-1488e 0-1488e 0-1488= 0-2142 0-2142e 0-2142e 0-2142= 0-2432 0-2432e 0-2432e 0-2432= 0-2442 0-2442= 0-2442e 0-2442e 0-2442= 0-2505 0-2505e 0-2505e 0-2505= 0-2514 0-2514e 0-2514e 0-2514= 0-2557 0-2557e 0-2557e 0-2557= 0-2687 0-2687= 0-2687e 0-2687e 0-2687= 0-2771 0-2771e 0-2771e 0-2771= 0-3176 0-3176e 0-3176e 0-3176= 0-3316 0-3316e 0-3316e 0-3316= 0-3338 0-3338= 0-3338e 0-3338e 0-3338= 0-3373 0-3373e 0-3373e 0-3373= 0-3621 0-3621e 0-3621e 0-3621= 0-3635 0-3635e 0-3635e 0-3635= 1- 525 1- 525= 1- 525e 1- 525e 1- 525= 1- 534 1- 534e 1- 534e 1- 534= 1- 543 1- 543e 1- 543e 1- 543= 1- 552 1- 552e 1- 552e 1- 552= 1-1316 1-1316= 1-1316e 1-1316e 1-1316= 1-1929 1-1929e 1-1929e 1-1929= 1-3108 1-3108e 1-3108e 1-3108= 0-3740e B8.ORG 0E08 0-1371= 0-1371 0-1371e 0-1371= 0-1475 0-1475e 0-1475= 0-1707= 0-1707 0-1707e 0-1707= 0-2015 0-2015e 0-2015= 1-1303= 1-1303 1-1303e 1-1303= B8.USED 0001 0- 388= 0-1371 0-1371= 0-1371e 0-1371e 0-1371= 0-1475 0-1475e 0-1475e 0-1475= 0-1707 0-1707= 0-1707e 0-1707e 0-1707= 0-2015 0-2015e 0-2015e 0-2015= 1-1303 1-1303= 1-1303e 1-1303e 1-1303= 0-3741e BADCOMM 01B7 0-2011= 0-2006a 0-2018a 0-2020a 0-2023a 0-2024a 0-2118a 0-2170a 0-2199a 0-2214a 0-2215a 0-2216a 0-2217a 0-2218a 0-2219a 0-2220a 0-2274a 0-2305a 0-2320a 0-2321a 0-2322a 0-2323a 0-2324a 0-2325a 0-2326a 0-2810a BADDATA 0304 0-2810= 0-2391a 0-2397a 0-2626a 0-2634a BADINP 01B8 0-2013= 0-2011v BC1CLR 1E0B 0- 922= 0-2467v 0-2536v 0-2569v BC2WBC2NLAST 02EA 0-2748= 0-2745a BC2WEVNOADJ 02F0 0-2760= 0-2756a 0-2763a BC2WODDADJBC 02F5 0-2768= 0-2757a BC2WODDINT 0E54 0-2773= 0-2748a 0-2767a BC2WODJM 02F4 0-2767= 0-2770a BC2WOIXOR 0004 0-2771= BC2WOKBC 02E8 0-2744= 0-2741a BC2WROLEVEN 02EE 0-2756= 0-2744a BCACTIV 0065 0-1182= 0-1177a BCINT 0200 0- 865= 0- 920e 0-1976v BCLAST 0020 0- 861= 0- 909e 0- 922e 0- 923e 0-2614v BCNLAST 0260 0-2397= 0-2383a BCNRDY 0040 0- 862= 0- 912e 0- 922e 0- 923e 0-1602v 0-2663v 0-2667v 0-2709v 0-2713v BCNT 0054 0- 497= 0-1080v 0-1114v 0-1175v 0-1649v 0-1650v 0-1653v 0-1663v 0-1666v 0-1842v 0-1868v 0-1872v 0-1883v 0-1902v 0-2228v 0-2465v 0-2535v 0-2546v 0-2568v 0-2572v 0-2671v 0-2724v 0-2730v 0-2740v 0-2752v 0-2756v 0-2757v 0-2761v 0-2768v 0-3040v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 191 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-3078v 0-3115v 0-3116v 0-3152v 0-3174v 0-3207v 0-3210v 0-3257v 0-3265v 0-3266v 0-3270v 0-3276v 0-3314v 0-3326v 0-3385v 0-3424v 0-3457v 0-3488v BCNT2 0068 0- 503= 0-1867v 0-2236v 0-2654v 0-2661v 0-2670v 0-2708v 0-2723v 0-2729v 0-3110v 0-3112v 0-3205v 0-3456v BCOVERUN 0048 0- 493= 0-1078v 0-1851v 0-1858v 0-1919v 0-2353v 0-2666v 0-2712v 0-3087v 0-3101v 0-3187v 0-3196v 0-3448v 0-3455v BCRATEOR 0092 0- 910= 0-1911v BCROLL 0010 0- 860= 0- 909e 0- 910e 0- 912e 0- 921e 0- 922e 0- 923e 0-1856v 0-1979v 0-3099v 0-3194v 0-3453v BETEST 0A6C 1-2921= 1-2913a BETEST1 0A69 1-2918= 1-2921v BFGODIE 0306 0-2840= 0-1945a 0-1946a 0-3504a 0-3505a 0-3538a 0-3539a 0-3577a 0-3578a BIFT 0088 0- 512= 0-2019v 0-2119v 0-2879v 0-2906v 0-2950v 0-2956v 0-2960v BIHC 0078 0- 508= 0-2004v 0-2007v 0-2017v 0-2164v 0-2165v 0-2279v 0-2877v 0-2900v 0-2946v 0-2962v BIHD 0080 0- 510= 0-2277v 0-2888v 0-2948v 0-2966v BILC 007C 0- 509= 0-2021v 0-2123v 0-2136v 0-2163v 0-2275v 0-2878v 0-2947v 0-2964v BILD 0084 0- 511= 0-2278v 0-2889v 0-2949v 0-2968v BIREAD 01EF 0-2161= 0-2019a BIRTAB 0E98 0-2017= 0-2009a BIST 008C 0- 513= 0-2865v 0-2868v 0-2875v 0-2881v 0-2882v 0-2895v 0-2899v 0-2945v 0-2954v 0-2958v BIWRITE 0225 0-2272= 0-2017a BLANKS 0000 0- 683= BLK.SIZE 0004 0- 384= 0-1060= 0-1060 0-1067 0-1067e 0-1224= 0-1224 0-1224 0-1224 0-1243 0-1243e 0-1325= 0-1325 0-1325 0-1325 0-1344 0-1344e 0-1371= 0-1371 0-1371 0-1382 0-1382e 0-1401= 0-1401 0-1401 0-1401 0-1420 0-1420e 0-1475= 0-1475 0-1475 0-1486 0-1486e 0-1488= 0-1488 0-1495 0-1495e 0-1707= 0-1707 0-1707 0-1718 0-1718e 0-2015= 0-2015 0-2015 0-2026 0-2026e 0-2142= 0-2142 0-2149 0-2149e 0-2203= 0-2203 0-2203 0-2203 0-2222 0-2222e 0-2309= 0-2309 0-2309 0-2309 0-2328 0-2328e 0-2432= 0-2432 0-2440 0-2440e 0-2442= 0-2442 0-2450 0-2450e 0-2505= 0-2505 0-2512 0-2512e 0-2514= 0-2514 0-2521 0-2521e 0-2557= 0-2557 0-2564 0-2564e 0-2687= 0-2687 0-2694 0-2694e 0-2771= 0-2771 0-2778 0-2778e 0-3176= 0-3176 0-3183 0-3183e 0-3316= 0-3316 0-3323 0-3323e 0-3338= 0-3338 0-3345 0-3345e 0-3373= 0-3373 0-3380 0-3380e 0-3621= 0-3621 0-3628 0-3628e 0-3635= 0-3635 0-3642 0-3642e 1- 525= 1- 525 1- 532 1- 532e 1- 534= 1- 534 1- 541 1- 541e 1- 543= 1- 543 1- 550 1- 550e 1- 552= 1- 552 1- 559 1- 559e 1- 583= 1- 583 1- 583 1- 583 1- 602 1- 602e 1- 604= 1- 604 1- 604 1- 604 1- 623 1- 623e 1-1303= 1-1303 1-1303 1-1312 1-1312e 1-1316= 1-1316 1-1321 1-1321e 1-1358= 1-1358 1-1358 1-1358 1-1375 1-1375e 1-1379= 1-1379 1-1379 1-1379 1-1396 1-1396e 1-1400= 1-1400 1-1400 1-1400 1-1417 1-1417e 1-1421= 1-1421 1-1421 1-1421 1-1438 1-1438e 1-1442= 1-1442 1-1442 1-1442 1-1459 1-1459e 1-1496= 1-1496 1-1496 1-1496 1-1513 1-1513e 1-1517= 1-1517 1-1517 1-1517 1-1534 1-1534e 1-1538= 1-1538 1-1538 1-1538 1-1555 1-1555e 1-1559= 1-1559 1-1559 1-1559 1-1576 1-1576e 1-1580= 1-1580 1-1580 1-1580 1-1597 1-1597e 1-1632= 1-1632 1-1632 1-1632 1-1649 1-1649e 1-1653= 1-1653 1-1653 1-1653 1-1670 1-1670e 1-1674= 1-1674 1-1674 1-1674 1-1691 1-1691e 1-1695= 1-1695 1-1695 1-1695 1-1712 1-1712e 1-1716= 1-1716 1-1716 1-1716 1-1733 1-1733e 1-1792= 1-1792 1-1792 1-1792 1-1809 1-1809e 1-1813= 1-1813 1-1813 1-1813 1-1830 1-1830e 1-1834= 1-1834 1-1834 1-1834 1-1851 1-1851e 1-1855= 1-1855 1-1855 1-1855 1-1872 1-1872e 1-1876= 1-1876 1-1876 1-1876 1-1893 1-1893e 1-1929= 1-1929 1-1934 1-1934e 1-1938= 1-1938 1-1938 1-1938 1-1955 1-1955e 1-1959= 1-1959 1-1959 1-1959 1-1976 1-1976e 1-2364= 1-2364 1-2364 1-2364 1-2381 1-2381e 1-2998= 1-2998 1-2998 1-2998 1-3017 1-3017e 1-3108= 1-3108 1-3115 1-3115e BLK4WSTE 0004 0-3740= 0-3753 BLK8WSTE 0008 0-3741= 0-3755 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 192 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table BLOCKADD 0DF8 0-1060= 0-1067 0-1067e 0-1224= 0-1243 0-1243e 0-1325= 0-1344 0-1344e 0-1371= 0-1382 0-1382e 0-1401= 0-1420 0-1420e 0-1475= 0-1486 0-1486e 0-1488= 0-1495 0-1495e 0-1707= 0-1718 0-1718e 0-2015= 0-2026 0-2026e 0-2142= 0-2149 0-2149e 0-2203= 0-2222 0-2222e 0-2309= 0-2328 0-2328e 0-2432= 0-2440 0-2440e 0-2442= 0-2450 0-2450e 0-2505= 0-2512 0-2512e 0-2514= 0-2521 0-2521e 0-2557= 0-2564 0-2564e 0-2687= 0-2694 0-2694e 0-2771= 0-2778 0-2778e 0-3176= 0-3183 0-3183e 0-3316= 0-3323 0-3323e 0-3338= 0-3345 0-3345e 0-3373= 0-3380 0-3380e 0-3621= 0-3628 0-3628e 0-3635= 0-3642 0-3642e 1- 525= 1- 532 1- 532e 1- 534= 1- 541 1- 541e 1- 543= 1- 550 1- 550e 1- 552= 1- 559 1- 559e 1- 583= 1- 602 1- 602e 1- 604= 1- 623 1- 623e 1-1303= 1-1312 1-1312e 1-1316= 1-1321 1-1321e 1-1358= 1-1375 1-1375e 1-1379= 1-1396 1-1396e 1-1400= 1-1417 1-1417e 1-1421= 1-1438 1-1438e 1-1442= 1-1459 1-1459e 1-1496= 1-1513 1-1513e 1-1517= 1-1534 1-1534e 1-1538= 1-1555 1-1555e 1-1559= 1-1576 1-1576e 1-1580= 1-1597 1-1597e 1-1632= 1-1649 1-1649e 1-1653= 1-1670 1-1670e 1-1674= 1-1691 1-1691e 1-1695= 1-1712 1-1712e 1-1716= 1-1733 1-1733e 1-1792= 1-1809 1-1809e 1-1813= 1-1830 1-1830e 1-1834= 1-1851 1-1851e 1-1855= 1-1872 1-1872e 1-1876= 1-1893 1-1893e 1-1929= 1-1934 1-1934e 1-1938= 1-1955 1-1955e 1-1959= 1-1976 1-1976e 1-2364= 1-2381 1-2381e 1-2998= 1-3017 1-3017e 1-3108= 1-3115 1-3115e BLOCKON 0000 0- 386= 0-1060 0-1067= 0-1224 0-1243= 0-1325 0-1344= 0-1371 0-1382= 0-1401 0-1420= 0-1475 0-1486= 0-1488 0-1495= 0-1707 0-1718= 0-2015 0-2026= 0-2142 0-2149= 0-2203 0-2222= 0-2309 0-2328= 0-2432 0-2440= 0-2442 0-2450= 0-2505 0-2512= 0-2514 0-2521= 0-2557 0-2564= 0-2687 0-2694= 0-2771 0-2778= 0-3176 0-3183= 0-3316 0-3323= 0-3338 0-3345= 0-3373 0-3380= 0-3621 0-3628= 0-3635 0-3642= 1- 525 1- 532= 1- 534 1- 541= 1- 543 1- 550= 1- 552 1- 559= 1- 583 1- 602= 1- 604 1- 623= 1-1303 1-1312= 1-1316 1-1321= 1-1358 1-1375= 1-1379 1-1396= 1-1400 1-1417= 1-1421 1-1438= 1-1442 1-1459= 1-1496 1-1513= 1-1517 1-1534= 1-1538 1-1555= 1-1559 1-1576= 1-1580 1-1597= 1-1632 1-1649= 1-1653 1-1670= 1-1674 1-1691= 1-1695 1-1712= 1-1716 1-1733= 1-1792 1-1809= 1-1813 1-1830= 1-1834 1-1851= 1-1855 1-1872= 1-1876 1-1893= 1-1929 1-1934= 1-1938 1-1955= 1-1959 1-1976= 1-2364 1-2381= 1-2998 1-3017= 1-3108 1-3115= BLOCKORG 0C60 0- 385= 0-1060e 0-1060e 0-1060= 0-1224 0-1224e 0-1224= 0-1325 0-1325e 0-1325= 0-1371e 0-1371e 0-1371= 0-1401 0-1401e 0-1401= 0-1707e 0-1707e 0-1707= 0-2203 0-2203e 0-2203= 0-2309 0-2309e 0-2309= 0-2442e 0-2442e 0-2442= 0-2687e 0-2687e 0-2687= 0-3338e 0-3338e 0-3338= 1- 525e 1- 525e 1- 525= 1- 583 1- 583e 1- 583= 1- 604 1- 604e 1- 604= 1-1303e 1-1303e 1-1303= 1-1316e 1-1316e 1-1316= 1-1358 1-1358e 1-1358= 1-1379 1-1379e 1-1379= 1-1400 1-1400e 1-1400= 1-1421 1-1421e 1-1421= 1-1442 1-1442e 1-1442= 1-1496 1-1496e 1-1496= 1-1517 1-1517e 1-1517= 1-1538 1-1538e 1-1538= 1-1559 1-1559e 1-1559= 1-1580 1-1580e 1-1580= 1-1632 1-1632e 1-1632= 1-1653 1-1653e 1-1653= 1-1674 1-1674e 1-1674= 1-1695 1-1695e 1-1695= 1-1716 1-1716e 1-1716= 1-1792 1-1792e 1-1792= 1-1813 1-1813e 1-1813= 1-1834 1-1834e 1-1834= 1-1855 1-1855e 1-1855= 1-1876 1-1876e 1-1876= 1-1938 1-1938e 1-1938= 1-1959 1-1959e 1-1959= 1-2364 1-2364e 1-2364= 1-2998 1-2998e 1-2998= 0-3733 0-3735e BPE 4000 0- 775= 0- 798e 0-2895v 0-2899v BSE 2000 0- 813= 0-2996v BSERTN 0AFE 1-3141= 1-2835a 1-2836a 1-2837a 1-2838a BSRST 0B03 1-3146= 1-3078a BTWREC 8000 0- 871= 0- 917e 0- 918e 0- 919e 0- 922e 0- 924e 0-1171v 0-1412v 0-1446v 0-1451v 0-2315v 0-2398v BTWRECOE 7FFB 0- 918= 0-1409v BUSACTIV F5FF 0- 783= 0-1159v BUSBITS 00A0 0-3715= 1-2213v 1-2214v 1-2219v 1-2221v 1-2222v 1-2488v 1-2945v 1-3022v 1-3026v 1-3030v 1-3034v 1-3037v 1-3038v 1-3039v 1-3040v 1-3041v 1-3042v 1-3043v 1-3044v 1-3046v 1-3047v 1-3048v 1-3049v 1-3050v 1-3051v 1-3052v 1-3053v 1-3054v 1-3055v 1-3056v 1-3057v 1-3084v 1-3090v 1-3245v 1-3306v 1-3678v 1-3710v BUSBLOCK 0C70 1-3000= 1-2947a BUSFREE F5BF 0- 782= 0-2079v 0-2082v 0-2104v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 193 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table BUSTO 000C 0- 577= 0-1166v 0-1170v BUSTO2 007D 0- 578= 0-1710v 0-1711v 0-1712v 0-1713v 0-1714v 0-1715v 0-1716v BUSY 0082 0-1284= 0-1234a CALCLAST 0283 0-2534= 0-2528a 0-2531a CBIT 0200 0- 881= 0-2174v 0-2281v CBN 0400 0- 777= CBNERR 030B 0-2847= 0-2828v 0-2829v 0-2830v 0-2831v 0-2832v 0-2833v 0-2834v 0-2835v CBNIADR 0030 0- 760= 0-1037v CBNIM 0010 0- 728= 0- 734e 0-2047v 0-2861v 0-2863v 0-2934v CBNINT 0F10 0-2820= 0-1037v CBNINT1 030D 0-2860= 0-2820a 0-2821a 0-2822a 0-2823a 0-2824a 0-2825a 0-2826a 0-2827a CBNTO 007D 0- 576= 0-2865v CBRTN 0AF9 1-3135= 1-2831a 1-2832a 1-2833a 1-2834a 1-2839a 1-2840a 1-2841a 1-2842a CBXFER 0AC8 1-3067= 1-3038a 1-3040a 1-3042a 1-3044a 1-3051a 1-3053a 1-3055a 1-3057a CIBSE 033D 0-2938= 0-2927a 0-2928a CICKTO 0313 0-2868= 0-2874a CIEXIT 033A 0-2933= 0-2896a 0-2905a 0-2934a CIEXIT1 033C 0-2936= 0-2933a CIINPERR 030C 0-2849= 0-2938v CIISUS 032E 0-2912= 0-2909a CINOTBPE 0338 0-2927= 0-2895a 0-2899a CINOTCOM 0326 0-2899= 0-2892a CINOTDAT 0324 0-2895= 0-2890a CINOTDWT 031E 0-2885= 0-2882a CINOTIBF 0316 0-2874= 0-2865a 0-2871a CINOTPOL 032A 0-2905= 0-2902a CINOTTO 0315 0-2871= 0-2868a CIOURPOL 0332 0-2918= 0-2912a CIPROCSW 0323 0-2892= 0-2885a CIRESERR 030A 0-2845= 0-2870v CK1STBYT 0EC0 0-1327= 0-1323a CKBCACTV 0061 0-1175= 0-1171a CKBCINT 01A7 0-1976= 0-1136a CKBSE 0367 0-2992= 0-2981a CKBUSACT 0058 0-1158= 0-1141a CKBUSTO 0063 0-1178= 0-1174a 0-1181a CKCREAD 00C7 0-1467= 0-1285a CKFIFOBZ 00EF 0-1572= 0-1109a CKFORDPE 0051 0-1130= 0-1122a CKFULL 00F3 0-1578= 0-1575a CKGOING 00FE 0-1608= 0-1601a CKINPTO 00E7 0-1546= 0-1523a CKINT 01AB 0-1983= 0-1979a CKLEGAL 01B3 0-2004= 0-1140a CKRESP 0EA0 0-1403= 0-1399a CKRUNING 00F9 0-1599= 0-1113a CKTIMER 008F 0-1314= 0-1312a CKTIMOUT 00DF 0-1535= 0-1105a CKWAIT 00AB 0-1392= 0-1388a 0-1399v 0-1507a CLKDIRT 004E 0-1125= 0-1121a CLKFIX 001C 0- 479= 0-1082v 0-1117v 0-1128v 0-2466v 0-2672v 0-2725v 0-3111v 0-3206v 0-3458v CLKLFX 004D 0-1122= 0-1128a CLKQFX 0050 0-1128= 0-1125a 0-1126a CLRFLAGS FC00 0- 654= 0-1384v 0-1507v CLRWAIT F3FF 0- 655= 0-1464v CM FFFF 0- 540= 0- 655e 0- 656e 0- 681e 0- 734e 0- 782e 0- 783e 0- 916e 0- 918e 0- 921e 0- 922e 0- 923e 0-1102v 0-1106v 0-1110v 0-1130v 0-1395v 0-1412v 0-1453v 0-1572v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 194 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-1574v 0-1581v 0-1722v 0-1741v 0-1768v 0-1779v 0-1799v 0-1811v 0-1934v 0-2047v 0-2398v CNTDOWN 0024 0- 482= 0-1316v 0-1537v 0-2189v 0-2297v COCKPIT 0400 0- 866= 0- 913e 0- 923e COMMCOMM 2020 0- 800= 0-2885v COMMDATA 2010 0- 801= 0-2886v CONFIG 094A 1-2200= 1-1279a CONFIGRS 095C 1-2221= 1-2216a CONFUSED 0402 0- 913= 0-1432v 0-1436v 0-1442v 0-2379v 0-2391v 0-2397v 0-2626v 0-2634v CONGODIE 0309 0-2843= 0-1947a 0-1948a 0-1949a 0-1950a 0-2111a 0-2828a 0-2829a 0-2830a 0-2831a 0-2832a 0-2833a 0-2834a 0-2835a 0-3058a 0-3059a 0-3060a 0-3061a 0-3062a 0-3063a 0-3064a 0-3065a 0-3135a 0-3136a 0-3137a 0-3138a 0-3139a 0-3140a 0-3141a 0-3142a 0-3296a 0-3297a 0-3298a 0-3299a 0-3300a 0-3301a 0-3302a 0-3303a 0-3357a 0-3358a 0-3359a 0-3360a 0-3361a 0-3362a 0-3363a 0-3364a 0-3409a 0-3410a 0-3411a 0-3412a 0-3413a 0-3414a 0-3415a 0-3416a 0-3506a 0-3507a 0-3508a 0-3509a 0-3540a 0-3541a 0-3542a 0-3543a 0-3579a 0-3580a 0-3581a 0-3582a CONTRESET2 0A52 1-2882= 1-2878a 1-2888a COPYTOME 009B 0- 825= 0-2975v CORBC 004C 0- 494= 0-1641v 0-1654v 0-1665v 0-1841v 0-1871v 0-1882v 0-1901v 0-2230v 0-2238v 0-2418v 0-2463v 0-2497v 0-2501v 0-2502v 0-2662v CORRBCNOT0 0214 0-2242= 0-2238a CRDSTART 809D 0- 630= 0-1519v 0-2188v CRDTAB 0EE4 0-1490= 0-1473a CRDTEST 8000 0- 629= 0- 630e 0-1467v 0-1512v CRIOR 0004 0-1488= 0-1470v CSFREE F4FF 0- 656= 0-2181v 0-2289v CSIBYTE 0EB0 0-1373= 0-1369a CSINPRDY 008C 0-1311= 0-1259a CTLRINT 0808 0- 914= 0-1986v CTLRINTE 0800 0- 867= 0- 914e 0- 916e 0- 920e CTLRINTR 0008 0- 859= 0- 914e 0- 921e 0-1408v CTLRRD 0062 0- 618= 0- 630e 0-1516v 0-2185v CTLRWR 0096 0- 619= 0- 631e 0-1515v 0-2293v CTMCKTO 035F 0-2979= 0-2986a CTMNIBF 0362 0-2986= 0-2977a 0-2982a CTMNOTTO 0361 0-2982= 0-2979a CTMTO 007D 0- 585= 0-2977v CUBCNEQ 0190 0-1906= 0-1902a CUBCNLAS 0193 0-1911= 0-1907a CUCKDONE 0111 0-1676= 0-1606a CUCKEXT 0194 0-1914= 0-1678a 0-1850a CUCKMT 0115 0-1682= 0-1679a 0-1838a CUEXIT 0197 0-1919= 0-1684a 0-1846a 0-1906a 0-1910a 0-1911a CUEXTRA 0196 0-1918= 0-1915a CUNDONE 0113 0-1679= 0-1651a 0-1663a 0-1666a 0-1676a 0-1878a 0-1883a CUNOTMT 0117 0-1685= 0-1682a CUNOTMT3 0184 0-1885= 0-1735a 0-1762a 0-1794a CUNOTMTA 011B 0-1690= 0-1689v CWIOR 0008 0-1475= 0-1469v CWRSTART 0069 0- 631= 0-1518v 0-2296v CWRTAB 0EB8 0-1477= 0-1472a DATA0 0AA3 1-3021= 1-3000a DATA0A 0AA4 1-3022= 1-3024a DATA1 0AA7 1-3025= 1-3001a DATA1A 0AA8 1-3026= 1-3028a DATA2 0AAB 1-3029= 1-3002a DATA2A 0AAC 1-3030= 1-3032a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 195 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table DATA3 0AAF 1-3033= 1-3003a DATA3A 0AB0 1-3034= 1-3036a DATA4 0AB3 1-3037= 1-3004a DATA4A 0AB4 1-3038= 1-3004v DATA5 0AB5 1-3039= 1-3005a DATA5A 0AB6 1-3040= 1-3005v DATA6 0AB7 1-3041= 1-3006a DATA6A 0AB8 1-3042= 1-3006v DATA7 0AB9 1-3043= 1-3007a DATA7A 0ABA 1-3044= 1-3007v DATA8 0ABB 1-3046= 1-3008a DATA9 0ABC 1-3047= 1-3009a DATAA 0ABD 1-3048= 1-3010a DATAB 0ABE 1-3049= 1-3011a DATAC 0ABF 1-3050= 1-3012a DATACA 0AC0 1-3051= 1-3012v DATAD 0AC1 1-3052= 1-3013a DATADA 0AC2 1-3053= 1-3013v DATADATA 1010 0- 802= DATAE 0AC3 1-3054= 1-3014a DATAEA 0AC4 1-3055= 1-3014v DATAF 0AC5 1-3056= 1-3015a DATAFA 0AC6 1-3057= 1-3015v DATAMOD 08E4 1-1926= 1-1211a 1-1214a 1-1229a 1-1232a 1-1351a 1-1380a 1-1381a 1-1382a 1-1383a 1-1384a 1-1385a 1-1386a 1-1387a 1-1388a 1-1389a 1-1390a 1-1391a 1-1392a 1-1393a 1-1394a 1-1395a 1-1401a 1-1402a 1-1403a 1-1404a 1-1405a 1-1406a 1-1407a 1-1408a 1-1409a 1-1410a 1-1411a 1-1412a 1-1413a 1-1414a 1-1415a 1-1416a 1-1422a 1-1423a 1-1424a 1-1425a 1-1426a 1-1427a 1-1428a 1-1429a 1-1430a 1-1431a 1-1432a 1-1433a 1-1434a 1-1435a 1-1436a 1-1437a 1-1443a 1-1444a 1-1445a 1-1446a 1-1447a 1-1448a 1-1449a 1-1450a 1-1451a 1-1452a 1-1453a 1-1454a 1-1455a 1-1456a 1-1457a 1-1458a 1-1483a 1-1518a 1-1519a 1-1520a 1-1521a 1-1522a 1-1523a 1-1524a 1-1525a 1-1526a 1-1527a 1-1528a 1-1529a 1-1530a 1-1531a 1-1532a 1-1533a 1-1539a 1-1540a 1-1541a 1-1542a 1-1543a 1-1544a 1-1545a 1-1546a 1-1547a 1-1548a 1-1549a 1-1550a 1-1551a 1-1552a 1-1553a 1-1554a 1-1560a 1-1561a 1-1562a 1-1563a 1-1564a 1-1565a 1-1566a 1-1567a 1-1568a 1-1569a 1-1570a 1-1571a 1-1572a 1-1573a 1-1574a 1-1575a 1-1581a 1-1582a 1-1583a 1-1584a 1-1585a 1-1586a 1-1587a 1-1588a 1-1589a 1-1590a 1-1591a 1-1592a 1-1593a 1-1594a 1-1595a 1-1596a 1-1625a 1-1738a 1-1779a 1-2014a 1-2019a 1-2058a 1-2070a 1-2093a 1-2098a 1-2108a 1-2113a 1-2135a 1-2140a 1-2153a 1-2158a DATAMOD0S 0C90 1-1960= 1-1931a DATAMOD1S 0CA0 1-1939= 1-1930a DATAMOD3 08E7 1-1983= 1-1933a DATAMODF 08E6 1-1981= 1-1954a 1-1975a DATAMODINC 08E5 1-1979= 1-1939a 1-1940a 1-1941a 1-1942a 1-1943a 1-1944a 1-1945a 1-1946a 1-1947a 1-1948a 1-1949a 1-1950a 1-1951a 1-1952a 1-1953a 1-1960a 1-1961a 1-1962a 1-1963a 1-1964a 1-1965a 1-1966a 1-1967a 1-1968a 1-1969a 1-1970a 1-1971a 1-1972a 1-1973a 1-1974a DATAMODIOR 0004 1-1929= 1-1210v 1-1213v 1-1228v 1-1231v 1-1246v 1-1263v DATAMODTBL 0DF4 1-1930= 1-1926a DB0BLOCK 0E20 1- 585= 1- 572a DB0LOOP 06F8 1- 572= 1- 566a DB0LPA 06F5 1- 568= 1- 572v DB0TEST 06F4 1- 566= 1- 523a DB4BLOCK 0E10 1- 606= 1- 580a DB4LOOP 06FE 1- 580= 1- 574a DB4LPA 06FB 1- 576= 1- 580v DECIBF 01BD 0-2045= 0-2036a 0-2192a 0-2288a 0-2301a 0-2341v 0-2356a 0-2359a 0-2363a 0-2364a 0-2379a 0-2398a 0-2586a 0-2587v 0-2666a 0-2696a 0-2712a 0-2734a 0-2735a 0-2752a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 196 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-2760a 0-2773a 0-2774a 0-2775a 0-2776a 0-2802a 0-2808a DIDNTPOP 0EF0 0-3771= 0-1062a 0-1063a 0-1064a 0-1065a 0-1302a 0-1395a 0-1396a 0-1424a 0-1428a 0-1432a 0-1436a 0-1437a 0-1442a 0-1455a 0-1459a 0-1464a 0-1521a 0-1541a 0-1549a 0-1559a 0-1580a 0-1586a 0-1605a 0-1611a 0-1855a 0-1934a 0-1966a 0-1990a 0-1995a 0-2049a 0-2085a 0-2092a 0-2159a 0-2184a 0-2292a 0-2353a 0-2595a 0-2600a 0-2604a 0-2607a 0-2609a 0-2611a 0-2613a 0-2795a 0-2796a 0-2923a 0-2936a 0-3040a 0-3054a 0-3055a 0-3056a 0-3057a 0-3081a 0-3091a 0-3094a 0-3116a 0-3131a 0-3132a 0-3133a 0-3134a 0-3160a 0-3178a 0-3179a 0-3180a 0-3181a 0-3257a 0-3269a 0-3272a 0-3292a 0-3293a 0-3294a 0-3295a 0-3328a 0-3340a 0-3341a 0-3342a 0-3343a 0-3353a 0-3354a 0-3355a 0-3356a 0-3388a 0-3405a 0-3406a 0-3407a 0-3408a 0-3427a 0-3469a 0-3489a 0-3525a 0-3564a 0-3646a DIRINP 0000 0- 691= 0-1049v 0-1923v 0-2346v DIRISIN 0264 0-2414= 0-2412a DIRISIN2 02B0 0-2640= 0-2638a DIRISRD 02FA 0-2795= 0-2792a DIROUT 0001 0- 692= DISAINT 0AD5 1-3082= 1-3037a 1-3039a 1-3041a 1-3043a 1-3050a 1-3052a 1-3054a 1-3056a DMADIR 0001 0- 856= 0- 920e 0-1121v 0-1433v 0-1443v 0-2412v 0-2592v 0-2638v 0-2792v DMANBZ 0080 0- 863= 0- 909e 0- 910e 0- 911e 0- 917e 0- 919e 0- 922e 0- 924e 0-1447v 0-1572v 0-1599v 0-2586v 0-2734v 0-2749v 0-3091v 0-3255v DMAOE 0004 0- 858= 0- 918e 0- 922e 0- 923e 0-1453v 0-1584v DO1FETCH 0296 0-2590= 0-2587a DO1FEXIT 029A 0-2595= 0-2592a DO1FLOOP 02A7 0-2614= 0-2596a 0-2612v DO1FNEND 029D 0-2601= 0-2614a DOINGINP 0100 0- 642= 0- 654e 0- 656e 0- 658e DOINGOUT 0200 0- 643= 0- 654e 0- 656e 0- 662e DOPEXIT 0088 0-1299= 0-1258a 0-1263a 0-1268a 0-1273a 0-1284a 0-1289a 0-1294a DOPEXIT1 0089 0-1300= 0-1238a 0-1239a 0-1253a DOPORT 0074 0-1219= 0-1101a 0-1304a 0-1350a 0-1359a 0-1374a 0-1375a 0-1376a 0-1377a 0-1484a 0-1493a 0-1499a DOPORT1 0075 0-1220= 0-1299a DOPORTAB 0ED0 0-1226= 0-1222a DOUBWRTBIT 0001 0- 885= 0-2267v 0-2319v DOWRU 01E1 0-2135= 0-2126v 0-2130v DOWRU1 01E7 0-2151= 0-2133a 0-2144a DOWRU2 01E8 0-2152= 0-2145a DOWRU3 01E9 0-2153= 0-2146a DOWRU4 01EA 0-2154= 0-2147a DPPE 2000 0- 869= 0- 922e 0- 923e 0-1132v 0-1928v DPRST1IN 0001 0- 711= 0-1055v 0-1056v 0-1932v 0-1933v 0-2351v 0-2352v 0-2570v 0-2571v 1-3169v 1-3170v DPRST2IN 0000 0- 712= 0-2537v 0-2538v DPRSTOUT 0001 0- 713= 0-2468v 0-2469v DWTIN 0080 0- 780= 0-2882v DWTOUT 0002 0- 818= 0- 825e 0- 845e ENAINT 0AD6 1-3083= 1-3022a 1-3026a 1-3030a 1-3034a 1-3046a 1-3047a 1-3048a 1-3049a ENDINP 00A5 0-1384= 0-1274a ENDOUT 00CF 0-1501= 0-1290a ENDTEST 043C 0-3658= 0-3724a 0-3727a ENDWRITE 8082 0- 919= 0-1450v EOR 0090 0- 615= EOR1M1 0121 0-1722= 0-1720a EOR1M2 0122 0-1724= 0-1722a EOR1M3 0123 0-1725= 0-1732a EOR1M4 0125 0-1729= 0-1725a 0-1743a 0-1770a 0-1802a EOR1M5 0126 0-1732= 0-1729a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 197 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table EOR1MORE 0120 0-1720= 0-1710a EOR2M1 012B 0-1741= 0-1739a EOR2M2 012D 0-1744= 0-1741a EOR2M3 0133 0-1752= 0-1759a EOR2M4 0135 0-1756= 0-1752a 0-1778a 0-1810a EOR2M5 0136 0-1759= 0-1756a EOR2M7 0131 0-1749= 0-1747a EOR2M8 0132 0-1751= 0-1749a EOR2MORE 012A 0-1739= 0-1711a EOR2WBCNTGT7 010C 0-1659= 0-1655a EOR2WN1L 010F 0-1665= 0-1659a EOR3M1 013B 0-1768= 0-1766a EOR3M2 013D 0-1771= 0-1768a EOR3M3 0144 0-1782= 0-1779a EOR3M4 0147 0-1787= 0-1783a 0-1815a EOR3M5 0148 0-1790= 0-1787a EOR3M6 0145 0-1783= 0-1790a EOR3M7 0141 0-1776= 0-1774a EOR3M8 0143 0-1779= 0-1776a EOR3MORE 013A 0-1766= 0-1712a EOR4BCNOTZ 016A 0-1846= 0-1842a EOR4M2 0151 0-1803= 0-1799a EOR4M3 0158 0-1814= 0-1811a EOR4M4 015B 0-1819= 0-1814a EOR4M5 015C 0-1822= 0-1819a EOR4M6 0159 0-1815= 0-1822a EOR4M8 0157 0-1811= 0-1807a EOR4MORE 014D 0-1798= 0-1713a 0-1714a 0-1715a 0-1716a EOR4NOTLAST 016D 0-1851= 0-1847a EOR4NOTZERO 0166 0-1838= 0-1832a EORBLOCK 0E90 0-1709= 0-1694a EORCK2WBCNT 0109 0-1653= 0-1645a EORIBF 0F00 0-1943= 0-1692v EORIBF1 01A3 0-1964= 0-1944a EORINTR 0082 0- 911= 0-1684v 0-1846v 0-1906v EORIOR 0000 0-1707= 0-1693v EORNEXTBC 016F 0-1856= 0-1851a EORNOT2WMODE 0105 0-1646= 0-1641a EORNPE 019D 0-1929= 0-1925a EORRESERR1 0129 0-1737= 0-1728v EORRESERR2 0139 0-1764= 0-1755v EORRESERR3 014C 0-1796= 0-1786v EORRESERR4 0165 0-1834= 0-1818v EORROLLGT3 0181 0-1879= 0-1874a EORTIMER 0018 0- 477= 0-1710v 0-1711v 0-1712v 0-1713v 0-1714v 0-1715v 0-1716v 0-1725v 0-1743v 0-1752v 0-1770v 0-1778v 0-1783v 0-1802v 0-1810v 0-1814v 0-1815v ERRFLAG 00AC 0-3717= 0-3729 1- 136v 1- 137v 1- 139v 0-3724v 0-3727v ERRTN 0C54 0-3723= 1- 138a 1- 149a 1- 151a 1- 154a 1- 155a 1- 157a 1- 159a 1- 162a 1- 163a 1- 177a 1- 179a 1- 181a 1- 183a 1- 185a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 394a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 395a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 396a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 397a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 398a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 399a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 400a 1- 401a 1- 401a 1- 401a 1- 401a 1- 401a 1- 401a 1- 401a 1- 401a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 198 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1- 401a 1- 401a 1- 401a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 402a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 403a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 404a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 405a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 406a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 407a 1- 430a 1- 431a 1- 432a 1- 433a 1- 434a 1- 435a 1- 436a 1- 437a 1- 438a 1- 439a 1- 440a 1- 441a 1- 442a 1- 443a 1- 444a 1- 445a 1- 463a 1- 471a 1- 479a 1- 487a 1- 497a 1- 505a 1- 513a 1- 521a 1- 569a 1- 577a 1- 643a 1- 661a 1- 688a 1- 697a 1- 706a 1- 715a 1- 762a 1- 767a 1- 772a 1- 777a 1- 782a 1- 787a 1- 792a 1- 797a 1- 802a 1- 807a 1- 812a 1- 817a 1- 822a 1- 827a 1- 832a 1- 837a 1- 842a 1- 847a 1- 852a 1- 857a 1- 862a 1- 867a 1- 872a 1- 877a 1- 882a 1- 887a 1- 892a 1- 897a 1- 902a 1- 907a 1- 912a 1- 917a 1- 988a 1- 990a 1- 992a 1- 994a 1- 996a 1- 998a 1-1000a 1-1002a 1-1004a 1-1006a 1-1008a 1-1010a 1-1012a 1-1014a 1-1016a 1-1018a 1-1020a 1-1022a 1-1024a 1-1026a 1-1028a 1-1030a 1-1032a 1-1034a 1-1036a 1-1038a 1-1040a 1-1042a 1-1044a 1-1046a 1-1048a 1-1050a 1-1071a 1-1072a 1-1076a 1-1099a 1-1100a 1-1103a 1-1132a 1-1152a 1-1169a 1-1180a 1-1739a 1-2007a 1-2052a 1-2243a 1-2252a 1-2263a 1-2284a 1-2295a 1-2305a 1-2316a 1-2337a 1-2507a 1-2509a 1-2511a 1-2513a 1-2515a 1-2517a 1-2519a 1-2595a 1-2646a 1-2876a 1-2885a 1-2919a 1-2928a 1-3196a 1-3205a 1-3321a 1-3359a 1-3432a 1-3454a 1-3487a 1-3516a 1-3556a 1-3587a 1-3697a 1-3705a 1-3729a 1-3736a EXSTAT 0080 0-3713= 1-2237v 1-2240v 1-2246v 1-2249v 1-2257v 1-2260v 1-2278v 1-2281v 1-2289v 1-2292v 1-2299v 1-2302v 1-2309v 1-2313v 1-2357v 1-2394v 1-2408v 1-2436v 1-2454v 1-2465v 1-2482v 1-2506v 1-2556v 1-2976v 1-2979v 1-2984v 1-2985v 1-3279v 1-3289v 1-3305v 1-3314v 1-3332v 1-3343v 1-3351v 1-3411v 1-3464v 1-3532v 1-3662v EXSTAT2 0090 0-3714= 1-2359v 1-2407v 1-2420v 1-2439v 1-2467v 1-2473v 1-2480v 1-2518v 1-3287v 1-3308v EXTRA 4000 0- 870= 0- 922e 0- 923e 0-1724v 0-1751v 0-1782v 0-1918v FI2WBC2NLAST 03D6 0-3251= 0-3248a FI2WCKLAST 03B9 0-3161= 0-3155a FI2WCKWORD 03BB 0-3169= 0-3162a 0-3329a FI2WEVNOADJ 03DE 0-3269= 0-3265a FI2WEXIT 03B5 0-3156= 0-3152a FI2WNEXTBC 03C3 0-3194= 0-3187a FI2WNOTLAST 03C0 0-3187= 0-3171a FI2WODCKEND 03EB 0-3326= 0-3318a 0-3319a 0-3320a 0-3321a FI2WODDADJBC 03E3 0-3276= 0-3266a FI2WODDINT 0E58 0-3178= 0-3174a 0-3251a 0-3275a 0-3278a FI2WODNOTEND 03EC 0-3328= 0-3326a FI2WOIXOR 0008 0-3176= FI2WOKBC 03D4 0-3247= 0-3211a FI2WPARTWRD 03BC 0-3171= 0-3169a FI2WROLEVEN 03DC 0-3265= 0-3247a FIEND 0399 0-3088= 0-3115a FIEND2 039A 0-3090= 0-3188a FIEXIT 0394 0-3081= 0-3078a FIFONBZ 00F0 0-1574= 0-1572a FIISBIG 03AD 0-3116= 0-3112a FINEXTBC 039F 0-3099= 0-3087a FINOTEND 0398 0-3087= 0-3084a FINPERR1 038E 0-3071= 0-3058v 0-3059v 0-3060v 0-3061v 0-3062v 0-3063v 0-3064v 0-3065v FINPERR2 03AE 0-3146= 0-3135v 0-3136v 0-3137v 0-3138v 0-3139v 0-3140v 0-3141v 0-3142v FINPERR3 03E5 0-3307= 0-3296v 0-3297v 0-3298v 0-3299v 0-3300v 0-3301v 0-3302v 0-3303v FINPINT1W 0F20 0-3050= 0-2559v 0-2560v 0-2561v 0-2562v FINPINT2W 0F30 0-3127= 0-2507v 0-2508v 0-2509v 0-2510v 0-3318v 0-3319v 0-3320v 0-3321v FINPINT2WODD 0F40 0-3288= 0-2516v 0-2517v 0-2518v 0-2519v 0-2773v 0-2774v 0-2775v 0-2776v 0-3178v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 199 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-3179v 0-3180v 0-3181v FIORUN 039C 0-3093= 0-3098a 0-3193a 0-3452a FISETINT1W 0E6C 0-2559= 0-2418a FIWRITE 038F 0-3074= 0-3050a 0-3051a 0-3052a 0-3053a FIWRITE2W 03AF 0-3148= 0-3127a 0-3128a 0-3129a 0-3130a FIWRITE2WODD 03E6 0-3310= 0-3288a 0-3289a 0-3290a 0-3291a FLAGMASK 7030 0- 798= 0-2881v FLAGS 0010 0- 474= 0-1051v 0-1102v 0-1106v 0-1110v 0-1221v 0-1259v 0-1269v 0-1304v 0-1314v 0-1317v 0-1319v 0-1359v 0-1384v 0-1392v 0-1395v 0-1413v 0-1437v 0-1455v 0-1464v 0-1484v 0-1493v 0-1507v 0-1508v 0-1511v 0-1520v 0-1521v 0-1523v 0-1542v 0-1545v 0-1574v 0-1581v 0-1934v 0-2177v 0-2181v 0-2187v 0-2261v 0-2285v 0-2289v 0-2295v 0-2341v 0-3036v FLAGSAB 0000 0- 794= 0- 822e FLAGSCOMM 0002 0- 796= 0- 800e 0- 800e 0- 801e 0- 825e 0- 844e 0- 845e FLAGSDATA 0001 0- 795= 0- 799e 0- 801e 0- 802e 0- 802e 0- 821e 0- 822e 0- 825e 0- 845e FLTEST 0A74 1-2932= 1-2924a FLTEST1 0A6E 1-2926= 1-2932a FOEXIT 03FA 0-3427= 0-3424a FOEXIT1W 03F4 0-3388= 0-3385a FOLASTBC 0417 0-3484= 0-3491a FONEXTBC 0401 0-3448= 0-3444a FONLAST 03FD 0-3432= 0-3389a 0-3428a FONOT1W 0410 0-3469= 0-3466a FONOVRN 0403 0-3453= 0-3448a FOODDBC 0412 0-3475= 0-3431a FOODDBC1 041C 0-3491= 0-3475a FOODDWRD 03FF 0-3445= 0-3432a FOREAD 03F7 0-3422= 0-3401a 0-3402a 0-3403a 0-3404a FOREAD1W 03EF 0-3371= 0-3349a 0-3350a 0-3351a 0-3352a FOSBCB1W 03F0 0-3382= 0-3375a 0-3376a 0-3377a 0-3378a FOSETI1W 0E60 0-2445= 0-2428a FOSETI2W 0EEC 0-2435= 0-2427a FOSETIN2 0E44 0-3375= 0-3371a FOSI1WIP 0E40 0-3340= 0-3470a FOUTERR1 03EE 0-3368= 0-3357v 0-3358v 0-3359v 0-3360v 0-3361v 0-3362v 0-3363v 0-3364v FOUTERR2 03F6 0-3420= 0-3409v 0-3410v 0-3411v 0-3412v 0-3413v 0-3414v 0-3415v 0-3416v FOUTI1W 0F50 0-3349= 0-2445v 0-2446v 0-2447v 0-2448v 0-2689v 0-2690v 0-2691v 0-2692v 0-3340v 0-3341v 0-3342v 0-3343v FOUTINT 0F60 0-3401= 0-2435v 0-2436v 0-2437v 0-2438v 0-3375v 0-3376v 0-3377v 0-3378v GETBSTAT 006C 0-1197= 0-1162a 0-1186a GETFLAGS 0385 0-3031= 0-3002a 0-3010a 0-3017a 0-3025a GO 0060 0- 614= GOCKRESP 00AE 0-1399= 0-1391a GOODBITS 1A01 0- 920= 0-2313v 0-2314v GOODRTN 0C56 0-3725= 1-3751a HADDR 005C 0- 499= 0-1688v 0-1823v 0-1860v 0-1885v 0-2210v 0-2674v 0-2716v 0-2801v 0-3033v 0-3050v 0-3051v 0-3052v 0-3053v 0-3103v 0-3127v 0-3128v 0-3129v 0-3130v 0-3198v 0-3288v 0-3289v 0-3290v 0-3291v 0-3349v 0-3350v 0-3351v 0-3352v 0-3401v 0-3402v 0-3403v 0-3404v 0-3460v HADDR2 0070 0- 505= 0-1859v 0-2212v 0-2673v 0-2715v 0-2807v 0-3102v 0-3197v 0-3459v HBLB 0712 1- 684= 1- 652a HBLB1 0713 1- 685= 1- 690a HBLB2 071B 1- 694= 1- 699a HBLB3 0723 1- 703= 1- 708a HBLB4 072B 1- 712= 1- 717a HPR 8000 0- 811= 0- 844e 0- 845e HSW1 0038 0- 488= 0-1073v 0-1346v 0-1422v 0-2207v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 200 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table HSW2 0040 0- 490= 0-1075v 0-1426v 0-2208v HW1 0040 0-3708= 1-2360v 1-2366v 1-2367v 1-2368v 1-2369v 1-2370v 1-2371v 1-2372v 1-2373v 1-2385v 1-2386v 1-2387v 1-2389v 1-2398v 1-2399v 1-2401v 1-2403v 1-2411v 1-2413v 1-2415v 1-2416v 1-2424v 1-2426v 1-2427v 1-2428v 1-2441v 1-2442v 1-2443v 1-2444v 1-2446v 1-2448v 1-2458v 1-2460v 1-2469v 1-2470v 1-2508v 1-2510v 1-2514v 1-2516v 1-2523v 1-2524v 1-2525v 1-2568v 1-2578v 1-2585v 1-2588v 1-2603v 1-2619v 1-2629v 1-2636v 1-2639v 1-2654v 1-2908v 1-2958v 1-2966v 1-3086v 1-3281v 1-3310v 1-3346v 1-3422v 1-3425v 1-3436v 1-3438v 1-3447v 1-3457v 1-3459v 1-3473v 1-3478v 1-3493v 1-3497v 1-3507v 1-3521v 1-3525v 1-3541v 1-3546v 1-3562v 1-3566v 1-3578v 1-3592v 1-3596v 1-3670v 1-3676v 1-3741v 1-3745v HW2 0060 0-3710= 1-2910v 1-2962v 1-2968v 1-3088v 1-3291v 1-3312v 1-3348v 1-3475v 1-3480v 1-3491v 1-3495v 1-3509v 1-3519v 1-3523v 1-3543v 1-3548v 1-3560v 1-3564v 1-3580v 1-3590v 1-3594v 1-3672v 1-3706v 1-3739v 1-3743v HWORD 002C 0- 484= 0-1347v 0-1376v 0-1377v 0-1406v 0-1415v 0-1460v 0-1478v 0-1479v 0-2299v IBF 0040 0- 781= 0- 782e 0-2871v 0-2982v IBFIADR 0020 0- 759= 0-1032v 0-1692v 0-1965v 0-3383v 0-3447v 0-3475v 0-3483v 0-3564v 0-3646v IBFIM 0020 0- 727= 0- 734e IBIOR 0000 0-1371= 0-1368v IBLK0IOR 0000 1- 525= IBLK1IOR 0004 1- 534= IBLK2IOR 0008 1- 543= IBLK3IOR 000C 1- 552= ID 0020 0-3707= 1-2215v 1-2223v 1-2358v 1-2438v 1-3307v IDLE 0041 0-1100= 0-1090a 0-1205a IDTIMING 0044 0-1105= 0-1102a INCSTATE 00CC 0-1497= 0-1477a 0-1478a 0-1479a 0-1480a 0-1481a 0-1482a 0-1483a 0-1490a 0-1491a 0-1492a INDXBLK0 0E30 1- 527= 1- 459a 1- 493a INDXBLK1 0E34 1- 536= 1- 467a 1- 501a INDXBLK2 0E38 1- 545= 1- 475a 1- 509a INDXBLK3 0E3C 1- 554= 1- 483a 1- 517a INDXTEST 06C5 1- 456= INDXTSTB 06C9 1- 462= 1- 459v INDXTSTD 06CF 1- 470= 1- 467v INDXTSTF 06D5 1- 478= 1- 475v INDXTSTH 06DB 1- 486= 1- 483v INDXTSTJ 06DF 1- 496= 1- 493v INDXTSTL 06E5 1- 504= 1- 501v INDXTSTN 06EB 1- 512= 1- 509v INDXTSTP 06F1 1- 520= 1- 517v INEVEN2W 0282 0-2533= 0-2507a 0-2508a 0-2509a 0-2510a INITINTS FFCF 0- 734= 0-1030v INITLOOP 0024 0-1046= 0-1043a 0-1087a INODD2W 027C 0-2524= 0-2516a 0-2517a 0-2518a 0-2519a INPIOR 000C 0-2557= INPISLEG 009B 0-1350= 0-1330a 0-1333a 0-1336a 0-1337a 0-1339a INPISRDY 00A0 0-1365= 0-1269a INSETINT2WEV 0E64 0-2507= 0-2501a INSETINT2WOD 0E68 0-2516= 0-2497a 0-2502a INT 0001 0- 828= 0-1995v INTCLR E7FF 0- 916= 0-2260v 0-2921v INTEST 0A4C 1-2874= 1-2660a INTEST1 0A76 1-2944= 1-2921a 1-2926a INTEST2 0A7B 1-2950= 1-2947v INTEST3 0A96 1-2980= 1-2976a INTEST4 0A97 1-2982= 1-2991a INTEST5 0A9F 1-2990= 1-2987a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 201 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table INTEST6 0AA0 1-2991= 1-2980a INTESTA 0A5A 1-2893= 1-2889a INTISUS 021C 0-2258= 0-2255a INTLOOP 0ADF 1-3094= 1-3090a INTNOTUS 021A 0-2254= 0-2251a INTR 0050 0- 610= INTREQ 0097 0-1346= 0-1332a INTRNLBUSTES 048C 1- 393= 1- 187a INTRS 0054 0- 611= IORFOSETI1W 0000 0-2442= IRIOR 0008 0-2015= 0-2007v ISBSE 0368 0-2996= 0-2992a ISBTWREC 00B6 0-1432= 0-1409a ISBUSACT 005B 0-1163= 0-1159a ISCI 007F 0-1269= 0-1229a ISDPE 0052 0-1132= 0-1130a ISEOREAD 00BC 0-1446= 0-1443a ISGOING 0100 0-1611= 0-1608a ISI2WEIOR 0004 0-2505= ISI2WOIOR 0008 0-2514= ISPFW 006E 0-1201= 0-1198a ISRUNING 00FA 0-1601= 0-1599a ISWRITE 00D8 0-1515= 0-1512a LADDR 0060 0- 500= 0-1690v 0-1826v 0-1830v 0-1862v 0-1886v 0-1890v 0-2232v 0-2415v 0-2419v 0-2683v 0-2684v 0-2718v 0-2744v 0-2802v 0-3038v 0-3074v 0-3081v 0-3082v 0-3105v 0-3148v 0-3150v 0-3200v 0-3247v 0-3310v 0-3328v 0-3329v 0-3371v 0-3388v 0-3423v 0-3427v 0-3444v 0-3445v 0-3469v 0-3470v 0-3479v 0-3480v 0-3618v 0-3632v LADDR2 0074 0- 506= 0-1861v 0-2234v 0-2647v 0-2679v 0-2680v 0-2717v 0-2808v 0-3104v 0-3199v 0-3465v 0-3466v LAST 0058 0- 498= 0-1606v 0-1645v 0-1646v 0-1651v 0-1659v 0-1660v 0-1693v 0-1831v 0-1832v 0-1839v 0-1847v 0-1866v 0-1870v 0-1879v 0-1898v 0-1900v 0-1907v 0-2229v 0-2387v 0-2392v 0-2427v 0-2428v 0-2456v 0-2464v 0-2498v 0-2524v 0-2527v 0-2533v 0-2534v 0-2540v 0-2566v 0-2567v 0-2678v 0-2722v 0-2739v 0-2745v 0-2751v 0-2763v 0-2770v 0-3084v 0-3109v 0-3169v 0-3171v 0-3172v 0-3204v 0-3209v 0-3248v 0-3256v 0-3272v 0-3278v 0-3389v 0-3428v 0-3431v 0-3432v 0-3464v 0-3476v 0-3489v 0-3491v 0-3613v LAST2 006C 0- 504= 0-1865v 0-2237v 0-2630v 0-2635v 0-2640v 0-2641v 0-2655v 0-2660v 0-2677v 0-2707v 0-2721v 0-3108v 0-3203v 0-3463v LASTBC 00B2 0- 909= 0-1678v 0-1850v 0-1910v 0-3484v LASTBIT 8000 0- 926= 0-1606v 0-1645v 0-1832v 0-1839v 0-1847v 0-1870v 0-1900v 0-1907v 0-2317v 0-2380v 0-2383v 0-2384v 0-2498v 0-2540v 0-2627v 0-2739v 0-2745v 0-2751v 0-3084v 0-3171v 0-3209v 0-3248v 0-3256v 0-3389v 0-3428v 0-3489v LDBC1 0258 0-2379= 0-2315a LDBC1GE8 027A 0-2501= 0-2498a LDBC1INEVEN 0279 0-2498= 0-2419a LDBC1INOTLAS 028A 0-2543= 0-2540a LDBC2 02A9 0-2627= 0-2317a LDMA1 02FC 0-2799= 0-2316v LDMA2 0300 0-2805= 0-2318v LDSTATUS 0EAC 0-1415= 0-1408a LEASTBLK 0C70 0-3735= 0-3736e LETGO 00F6 0-1584= 0-1574a 0-1581a LEVEL 001A 0- 533= 0-1024v LS1 00C4 0- 612= LS2 0034 0- 613= LSW1 003C 0- 489= 0-1074v 0-1348v 0-1424v 0-2224v LSW2 0044 0- 491= 0-1076v 0-1428v 0-2226v LW1 0044 0-3709= 1-2569v 1-2579v 1-2586v 1-2589v 1-2601v 1-2620v 1-2630v 1-2637v 1-2640v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 202 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1-2652v 1-2909v 1-2960v 1-2967v 1-3087v 1-3283v 1-3311v 1-3347v 1-3423v 1-3426v 1-3435v 1-3437v 1-3439v 1-3440v 1-3448v 1-3455v 1-3458v 1-3474v 1-3479v 1-3492v 1-3496v 1-3508v 1-3520v 1-3524v 1-3542v 1-3547v 1-3561v 1-3565v 1-3579v 1-3591v 1-3595v 1-3671v 1-3677v 1-3740v 1-3744v LW2 0070 0-3711= 1-2911v 1-2964v 1-2969v 1-3089v 1-3293v 1-3313v 1-3349v 1-3476v 1-3481v 1-3490v 1-3494v 1-3498v 1-3499v 1-3510v 1-3517v 1-3522v 1-3526v 1-3527v 1-3544v 1-3549v 1-3559v 1-3563v 1-3567v 1-3568v 1-3581v 1-3588v 1-3593v 1-3597v 1-3598v 1-3673v 1-3709v 1-3737v 1-3742v 1-3746v 1-3747v LWORD 0030 0- 485= 0-1349v 0-1374v 0-1375v 0-1423v 0-1427v 0-1462v 0-1480v 0-1481v 0-2301v MAXPCHIGH 0C58 0-3731= 0-3733 0-3736e MAXPCLOW 044E 0-3686= 0-3689 0-3736e MEM1ERR 041D 0-3521= 0-3504v 0-3505v 0-3506v 0-3507v 0-3508v 0-3509v 0-3510v 0-3511v 0-3512v 0-3513v 0-3514v 0-3515v 0-3516v 0-3517v MEM2ERR 0421 0-3555= 0-3538v 0-3539v 0-3540v 0-3541v 0-3542v 0-3543v 0-3544v 0-3545v 0-3546v 0-3547v 0-3548v 0-3549v 0-3550v 0-3551v MEM3ERR 0428 0-3594= 0-3577v 0-3578v 0-3579v 0-3580v 0-3581v 0-3582v 0-3583v 0-3584v 0-3585v 0-3586v 0-3587v 0-3588v 0-3589v 0-3590v MEM4ERR 01A2 0-1962= 0-1945v 0-1946v 0-1947v 0-1948v 0-1949v 0-1950v 0-1951v 0-1952v 0-1953v 0-1954v 0-1955v 0-1956v 0-1957v 0-1958v MEMORY 0000 0- 276= MODEIS1W 0266 0-2418= 0-2414a MPECODE 0100 0- 864= 0- 922e 0- 923e 0-1943v 0-3502v 0-3560v 0-3600v 0-3607v NAK 00F8 0- 608= 0-1354v NEWISCI 007B 0-1259= 0-1227a NEWNOTCI 0078 0-1253= 0-1226a NEWTRANS 005E 0-1170= 0-1167a 0-1182a NEXTPORT 0000 0- 468= 0-1069v 0-1205v NOBUSTO 0066 0-1186= 0-1166a 0-1170a 0-1178a NOTBCINT 01A8 0-1978= 0-1976a NOTBTREC 00BA 0-1442= 0-1412a NOTCI 007C 0-1263= 0-1228a NOTCREAD 00C8 0-1469= 0-1467a NOTCTRIN 01AE 0-1990= 0-1986a NOTDONE 003E 0-1087= 0-1084a NOTFULL 00F4 0-1580= 0-1578a NOTIMING 005C 0-1166= 0-1163a NOTIMOUT 00E4 0-1541= 0-1538a NOTINPTO 00E8 0-1549= 0-1546a NOTLEGAL 01B4 0-2006= 0-2004a NOTODD2 02B4 0-2650= 0-2647a NOTPPUIN 01AC 0-1986= 0-1978a 0-1983a NOWAIT 00AC 0-1395= 0-1392a NUMPORTS 0004 0- 538= 0- 722e 0-1043v 0-1071v 0-1084v 0-1090v NXTSTATE 008B 0-1304= 0-1254a 0-1264a 0-1295a ODDWORD 0F90 0-3575= 0-3475v ODDWORDCKPE 042D 0-3605= 0-3599a ODDWORDOK 0F91 0-3576= 0-3608a ODDWORDPE 042E 0-3607= 0-3605a OLDBCNT 00B8 0- 528= 0-1081v 0-1177v 0-1182v ONEWORD 0F80 0-3536= 0-3383v 0-3447v 0-3483v ONEWORD1 0426 0-3563= 0-3537a ONEWORDCKPE 0423 0-3558= 0-3536a ONEWORDPE 0424 0-3560= 0-3558a OUT1WIOR 0000 0-3338= OUTEVENSTART 0268 0-2427= 0-2415a OUTIOR1 000C 0-2432= OUTIOR2 0004 0-3373= 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 203 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table OUTODDADDR 026B 0-2453= 0-2445a 0-2446a 0-2447a 0-2448a OVRRUN 0050 0- 912= 0-1855v 0-3094v OW1BCIOR 000C 0-3635= 0-3613v OW2BCIOR 0008 0-3621= 0-3619v OWCKIFONE 0429 0-3597= 0-3575a OWEXIT 043B 0-3646= 0-3624a 0-3625a 0-3630a 0-3638a 0-3639a 0-3644a OWIS1BC 0E4C 0-3637= 0-3633a OWIS1BC1 043A 0-3644= 0-3640a OWIS2BC 0E48 0-3623= 0-3620a OWIS2BC1 0437 0-3630= 0-3626a OWISONE 0430 0-3613= 0-3576a OWISONE1 0438 0-3632= 0-3613a OWNOTONE 0431 0-3614= 0-3602a OWPENOTONE 042B 0-3600= 0-3597a PBITHIGH 0008 0- 471= 0-1057v 0-1058v 0-2311v 0-2330v 0-2338v PBITIM 000C 0- 472= 0-1062v 0-1063v 0-1064v 0-1065v 0-1612v 0-2348v 0-2587v 0-2590v 0-2605v 0-2696v 0-2735v 0-2748v 0-2760v 0-2767v 0-3088v 0-3098v 0-3188v 0-3193v 0-3252v 0-3452v 0-3486v PBITLOW 0004 0- 470= 0-1053v 0-1054v 0-1585v 0-2343v 0-2344v PEGODIE 0305 0-2839= 0-1951a 0-1952a 0-1953a 0-1954a 0-1955a 0-1956a 0-1957a 0-1958a 0-3510a 0-3511a 0-3512a 0-3513a 0-3514a 0-3515a 0-3516a 0-3517a 0-3544a 0-3545a 0-3546a 0-3547a 0-3548a 0-3549a 0-3550a 0-3551a 0-3583a 0-3584a 0-3585a 0-3586a 0-3587a 0-3588a 0-3589a 0-3590a PFWCHECK 0008 0-1007= 0-1003a 0-1005a PFWNOT 8000 0- 774= 0-1005v 0-1198v PFWSTILL 0007 0-1005= 0-1007a PFWWAIT 0073 0-1210= 0-1208v PINTCK 0010 0-3703= 1-3024v 1-3028v 1-3032v 1-3036v 1-3122v PINTRTN 0DF8 1-3110= 1-2827a 1-2828a 1-2829a 1-2830a PINTRTNIOR 0008 1-3108= PINTSUB 0AEA 1-3117= 1-3110a 1-3111a 1-3112a 1-3113a PONCHECK 0B22 1-3210= 1-3197a PONCHECK4 0B1E 1-3201= 1-3210a POP1 0483 1- 178= 1- 175v POP2 0485 1- 180= 1- 174v POP3 0487 1- 182= 1- 173v POP4 0489 1- 184= 1- 172v PORT0IM 0001 0- 732= 0-1062v PORT1IM 0002 0- 731= 0-1063v PORT2IM 0004 0- 730= 0-1064v PORT3IM 0008 0- 729= 0-1065v PORTDEAD 4000 0- 648= 0- 651e 0- 652e 0-2177v 0-2285v PORTHIGH 0010 0- 725= 0-1042v PORTLOW 0001 0- 724= 0-1041v PPUINT 1002 0- 915= 0-1978v 0-1983v PPUINTE 1000 0- 868= 0- 915e 0- 916e 0- 920e PPUINTR 0002 0- 857= 0- 909e 0- 910e 0- 911e 0- 913e 0- 915e 0- 919e 0- 921e 0- 923e 0-1982v PPUTYPE 3000 0- 879= 0-1023v PRT0IADR 0070 0- 764= 0-2435v 0-2445v 0-2507v 0-2516v 0-2559v 0-2689v 0-2773v 0-3178v 0-3318v 0-3340v 0-3375v PRT1IADR 0060 0- 763= 0-2436v 0-2446v 0-2508v 0-2517v 0-2560v 0-2690v 0-2774v 0-3179v 0-3319v 0-3341v 0-3376v PRT2IADR 0050 0- 762= 0-2437v 0-2447v 0-2509v 0-2518v 0-2561v 0-2691v 0-2775v 0-3180v 0-3320v 0-3342v 0-3377v PRT3IADR 0040 0- 761= 0-2438v 0-2448v 0-2510v 0-2519v 0-2562v 0-2692v 0-2776v 0-3181v 0-3321v 0-3343v 0-3378v PRTCI 2000 0- 675= 0-1226v 0-1227v 0-1228v 0-1229v 0-1240v 0-1241v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 204 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table PRTEMPTY FCFF 0- 681= 0-1682v 0-1749v 0-1776v 0-1807v 0-1915v PRTFREE 1000 0- 676= 0-1233v 0-1234v PRTHIGH 0200 0- 679= 0- 681e PRTINIT 8080 0- 917= 0-1052v PRTINT 0800 0- 677= 0-1578v 0-1608v PRTLOW 0100 0- 680= 0- 681e 0-1722v 0-1741v 0-1768v 0-1779v 0-1799v 0-1811v PRTNUMMASK 0003 0- 722= 0-1987v 0-1991v 0-2164v 0-2166v 0-2249v 0-2272v 0-2279v PRTPE 0400 0- 678= 0-1130v 0-1925v PRTPON 4000 0- 674= PRTST 0014 0- 475= 0-1052v 0-1121v 0-1132v 0-1171v 0-1408v 0-1409v 0-1412v 0-1432v 0-1433v 0-1436v 0-1442v 0-1443v 0-1446v 0-1447v 0-1450v 0-1451v 0-1453v 0-1572v 0-1584v 0-1599v 0-1602v 0-1678v 0-1684v 0-1724v 0-1751v 0-1782v 0-1846v 0-1850v 0-1855v 0-1856v 0-1906v 0-1910v 0-1911v 0-1918v 0-1928v 0-1943v 0-1976v 0-1978v 0-1979v 0-1982v 0-1983v 0-1986v 0-2248v 0-2254v 0-2255v 0-2260v 0-2262v 0-2312v 0-2315v 0-2340v 0-2356v 0-2358v 0-2359v 0-2379v 0-2391v 0-2397v 0-2398v 0-2412v 0-2467v 0-2536v 0-2569v 0-2586v 0-2592v 0-2614v 0-2626v 0-2634v 0-2638v 0-2663v 0-2667v 0-2709v 0-2713v 0-2734v 0-2749v 0-2792v 0-2919v 0-2921v 0-3039v 0-3091v 0-3094v 0-3099v 0-3194v 0-3255v 0-3453v 0-3484v 0-3502v 0-3560v 0-3600v 0-3607v PTFULL 001C 0-3706= 1-2895v 1-2971v 1-2973v 1-2975v 1-2977v 1-3021v 1-3025v 1-3029v 1-3033v 1-3120v PUSHPOPTEST 047D 1- 172= 1- 164a RADR89 0891 1-1249= 1-1255a RADR89LOOP 0894 1-1255= 1-1251a RAM89TEST 0878 1-1207= 1-1181a RAM89TESTA 0879 1-1208= 1-1278a RAM89WRITELO 089E 1-1278= 1-1273a RAMP 0A08 1-2556= 1-2375a RAMP2 0A18 1-2582= 1-2574a RAMP4 0A21 1-2593= 1-2590v RAMP5 0A2A 1-2608= 1-2605a RAMP6 0A41 1-2644= 1-2641v RAMP8 0A4A 1-2659= 1-2656a RAMPA 0A38 1-2633= 1-2625a RAMPLOOP1 0A0D 1-2566= 1-2608a RAMPLOOP2 0A0F 1-2568= 1-2600a RAMPLOOP3 0A13 1-2575= 1-2570a 1-2580a RAMPLOOP4 0A2D 1-2617= 1-2659a RAMPLOOP5 0A2F 1-2619= 1-2651a RAMPLOOP6 0A33 1-2626= 1-2621a 1-2631a RCADR89 0899 1-1266= 1-1272a RCADR89LOOP 089C 1-1272= 1-1268a RDBCNT 020C 0-2228= 0-2209a RDBCNT2 0211 0-2236= 0-2211a RDCKWHO1 01F9 0-2174= 0-2169a RDISUS 01FA 0-2176= 0-2174a RDMA1 020F 0-2232= 0-2210a RDMA2 0210 0-2234= 0-2212a RDMODEND 0224 0-2269= 0-2266a 0-2267a RDMODENOTDW 0222 0-2266= 0-2213a RDNOTLEG 0208 0-2199= 0-2176a RDSTEXIT 021F 0-2261= 0-2248a 0-2254a RDSTS 0217 0-2249= 0-2206a RDSW1 020A 0-2224= 0-2207a RDSW2 020B 0-2226= 0-2208a RDTAB 0E80 0-2205= 0-2200a READ1W 2000 0- 839= 0- 847e 0-1688v READ2W 3000 0- 840= 0- 844e 0- 847e 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 205 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table READB2B 02D2 0-2712= 0-2709a READBC 028D 0-2566= 0-2559a 0-2560a 0-2561a 0-2562a READBC2 02CF 0-2707= 0-2640a READBITS B02D 0- 844= 0-1687v 0-2796v RECVRESP 00F0 0- 664= 0-1484v 0-1493v REMEMBER 0C0F 0- 277= 0-1060= 0-1067 0-1224= 0-1243 0-1325= 0-1344 0-1371= 0-1382 0-1401= 0-1420 0-1475= 0-1486 0-1488= 0-1495 0-1707= 0-1718 0-1941= 0-1960 0-2015= 0-2026 0-2142= 0-2149 0-2203= 0-2222 0-2309= 0-2328 0-2432= 0-2440 0-2442= 0-2450 0-2505= 0-2512 0-2514= 0-2521 0-2557= 0-2564 0-2687= 0-2694 0-2771= 0-2778 0-2818= 0-2837 0-3048= 0-3067 0-3125= 0-3144 0-3176= 0-3183 0-3286= 0-3305 0-3316= 0-3323 0-3338= 0-3345 0-3347= 0-3366 0-3373= 0-3380 0-3399= 0-3418 0-3500= 0-3519 0-3534= 0-3553 0-3573= 0-3592 0-3621= 0-3628 0-3635= 0-3642 1- 525= 1- 532 1- 534= 1- 541 1- 543= 1- 550 1- 552= 1- 559 1- 583= 1- 602 1- 604= 1- 623 1-1303= 1-1312 1-1316= 1-1321 1-1358= 1-1375 1-1379= 1-1396 1-1400= 1-1417 1-1421= 1-1438 1-1442= 1-1459 1-1496= 1-1513 1-1517= 1-1534 1-1538= 1-1555 1-1559= 1-1576 1-1580= 1-1597 1-1632= 1-1649 1-1653= 1-1670 1-1674= 1-1691 1-1695= 1-1712 1-1716= 1-1733 1-1792= 1-1809 1-1813= 1-1830 1-1834= 1-1851 1-1855= 1-1872 1-1876= 1-1893 1-1929= 1-1934 1-1938= 1-1955 1-1959= 1-1976 1-2364= 1-2381 1-2826= 1-2843 1-2998= 1-3017 1-3108= 1-3115 1-3642= 1-3659 REOR 2000 0- 647= 0-1110v 0-1455v 0-1934v REP.LST 0000 0-1067= 0-1243= 0-1344= 0-1382= 0-1420= 0-1486= 0-1495= 0-1718= 0-1960= 0-2026= 0-2149= 0-2222= 0-2328= 0-2440= 0-2450= 0-2512= 0-2521= 0-2564= 0-2694= 0-2778= 0-2837= 0-3067= 0-3144= 0-3183= 0-3305= 0-3323= 0-3345= 0-3366= 0-3380= 0-3418= 0-3519= 0-3553= 0-3592= 0-3628= 0-3642= 1- 532= 1- 541= 1- 550= 1- 559= 1- 602= 1- 623= 1-1312= 1-1321= 1-1375= 1-1396= 1-1417= 1-1438= 1-1459= 1-1513= 1-1534= 1-1555= 1-1576= 1-1597= 1-1649= 1-1670= 1-1691= 1-1712= 1-1733= 1-1809= 1-1830= 1-1851= 1-1872= 1-1893= 1-1934= 1-1955= 1-1976= 1-2381= 1-2843= 1-3017= 1-3115= 1-3659= REP.RPT 0000 0-1067= 0-1067 0-1243= 0-1243 0-1344= 0-1344 0-1382= 0-1382 0-1420= 0-1420 0-1486= 0-1486 0-1495= 0-1495 0-1718= 0-1718 0-1960= 0-1960 0-2026= 0-2026 0-2149= 0-2149 0-2222= 0-2222 0-2328= 0-2328 0-2440= 0-2440 0-2450= 0-2450 0-2512= 0-2512 0-2521= 0-2521 0-2564= 0-2564 0-2694= 0-2694 0-2778= 0-2778 0-2837= 0-2837 0-3067= 0-3067 0-3144= 0-3144 0-3183= 0-3183 0-3305= 0-3305 0-3323= 0-3323 0-3345= 0-3345 0-3366= 0-3366 0-3380= 0-3380 0-3418= 0-3418 0-3519= 0-3519 0-3553= 0-3553 0-3592= 0-3592 0-3628= 0-3628 0-3642= 0-3642 1- 532= 1- 532 1- 541= 1- 541 1- 550= 1- 550 1- 559= 1- 559 1- 602= 1- 602 1- 623= 1- 623 1-1312= 1-1312 1-1321= 1-1321 1-1375= 1-1375 1-1396= 1-1396 1-1417= 1-1417 1-1438= 1-1438 1-1459= 1-1459 1-1513= 1-1513 1-1534= 1-1534 1-1555= 1-1555 1-1576= 1-1576 1-1597= 1-1597 1-1649= 1-1649 1-1670= 1-1670 1-1691= 1-1691 1-1712= 1-1712 1-1733= 1-1733 1-1809= 1-1809 1-1830= 1-1830 1-1851= 1-1851 1-1872= 1-1872 1-1893= 1-1893 1-1934= 1-1934 1-1955= 1-1955 1-1976= 1-1976 1-2381= 1-2381 1-2843= 1-2843 1-3017= 1-3017 1-3115= 1-3115 1-3659= 1-3659 RESBUSY 0080 0-1273= 0-1233a RESCONT 023E 0-2330= 0-2311a RESCONT2 0242 0-2335= 0-2332a 0-2335a RESERR 006B 0-1195= 0-1190v RESET 0B06 1-3155= 1-2874a 1-2935a RESET1 0B0A 1-3159= 1-3155a RESET1A 0B07 1-3156= 1-3159v RESET2 0B0C 1-3164= 1-3159a RESGODIE 0308 0-2842= 0-1190a 0-1728a 0-1755a 0-1786a 0-1818a 0-2870a RESISCI 0085 0-1290= 0-1240a RESNOTCI 0086 0-1294= 0-1241a RESP 00A4 0- 616= RESPEXIT 01B9 0-2033= 0-2151a 0-2152a 0-2153a 0-2154a 0-2195a 0-2224a 0-2226a 0-2230a 0-2232a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 206 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-2234a 0-2242a 0-2243a 0-2262a 0-2269a RESPONSE 00C2 0-1459= 0-1413a RESPTO 0034 0- 486= 0-1463v 0-1557v 0-1558v 0-2190v RESTART 0013 0-1022= 0-3681a RESTRDWR 0080 0- 661= 0- 662e 0-1521v RFIIN 0100 0- 779= RFIOUT 0004 0- 817= 0-2820v 0-2821v 0-2822v 0-2823v 0-2824v 0-2825v 0-2826v 0-2827v RFR2OUT 0004 0- 816= 0- 823e 0- 844e RFRIN 0200 0- 778= 0- 782e 0- 783e RFROUT 0008 0- 815= 0- 825e 0- 844e RGOB 1000 0- 646= 0-1106v 0-1437v 0-1574v 0-1581v RLSW1 00AF 0-1422= 0-1415a RLSW2 00B2 0-1426= 0-1406a RNOTDEAD 01FD 0-2181= 0-2177a 0-2205a RNOTFREE 01FE 0-2184= 0-2181a RONE89 0887 1-1231= 1-1238a RONE89LOOP 088C 1-1238= 1-1234a RPTNOTKN 01F7 0-2170= 0-2166a RRALL89 08A1 1-1300= 1-1215a 1-1233a 1-1250a 1-1267a RRALL89BLOCK 0DF0 1-1317= 1-1300a RRALL89IOR 0000 1-1316= 1-1208v 1-1221v 1-1239v 1-1256v RRALLRADRX1 08E9 1-1999= 1-1317a RRALLRADRX2 08F5 1-2034= 1-1318a RRALLX1 08C2 1-1616= 1-1319a RRALLX1A 08C4 1-1618= 1-1629a RRALLX1B 08C9 1-1626= 1-1621a RRALLX2 08CE 1-1761= 1-1320a RRALLX2A 08DA 1-1773= 1-1787a RRALLX2B 08DF 1-1780= 1-1775a RRALLX2D 08D0 1-1763= 1-1788a RRALLX2E 08E2 1-1787= 1-1784a RRAM89 087D 1-1213= 1-1220a RRAM89LOOP 0882 1-1220= 1-1216a RRAMBAD 08CD 1-1739= 1-1654a 1-1655a 1-1656a 1-1657a 1-1658a 1-1659a 1-1660a 1-1661a 1-1662a 1-1663a 1-1664a 1-1665a 1-1666a 1-1667a 1-1668a 1-1669a 1-1675a 1-1676a 1-1677a 1-1678a 1-1679a 1-1680a 1-1681a 1-1682a 1-1683a 1-1684a 1-1685a 1-1686a 1-1687a 1-1688a 1-1689a 1-1690a 1-1696a 1-1697a 1-1698a 1-1699a 1-1700a 1-1701a 1-1702a 1-1703a 1-1704a 1-1705a 1-1706a 1-1707a 1-1708a 1-1709a 1-1710a 1-1711a 1-1717a 1-1718a 1-1719a 1-1720a 1-1721a 1-1722a 1-1723a 1-1724a 1-1725a 1-1726a 1-1727a 1-1728a 1-1729a 1-1730a 1-1731a 1-1732a 1-1814a 1-1815a 1-1816a 1-1817a 1-1818a 1-1819a 1-1820a 1-1821a 1-1822a 1-1823a 1-1824a 1-1825a 1-1826a 1-1827a 1-1828a 1-1829a 1-1835a 1-1836a 1-1837a 1-1838a 1-1839a 1-1840a 1-1841a 1-1842a 1-1843a 1-1844a 1-1845a 1-1846a 1-1847a 1-1848a 1-1849a 1-1850a 1-1856a 1-1857a 1-1858a 1-1859a 1-1860a 1-1861a 1-1862a 1-1863a 1-1864a 1-1865a 1-1866a 1-1867a 1-1868a 1-1869a 1-1870a 1-1871a 1-1877a 1-1878a 1-1879a 1-1880a 1-1881a 1-1882a 1-1883a 1-1884a 1-1885a 1-1886a 1-1887a 1-1888a 1-1889a 1-1890a 1-1891a 1-1892a RRAX1A 08EB 1-2001= 1-2019v RRAX1B 08F1 1-2015= 1-2006a RRAX1C 08EF 1-2007= 1-2003a RRAX1LSBLOCK 0D40 1-1633= 1-1620a RRAX1MS0BLOC 0D30 1-1654= 1-1633a 1-1634a 1-1635a 1-1636a RRAX1MS1BLOC 0D20 1-1675= 1-1637a 1-1638a 1-1639a 1-1640a RRAX1MS2BLOC 0D10 1-1696= 1-1641a 1-1642a 1-1643a 1-1644a RRAX1MS3BLOC 0D00 1-1717= 1-1645a 1-1646a 1-1647a 1-1648a RRAX2A 08F7 1-2036= 1-2067v RRAX2B 0901 1-2046= 1-2066v RRAX2C 0905 1-2052= 1-2048a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 207 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table RRAX2D 090A 1-2066= 1-2063a RRAX2E 090C 1-2070= 1-2066a 1-2067a RRAX2F 0907 1-2059= 1-2051a RRAX2LSBLOCK 0CF0 1-1793= 1-1774a RRAX2MS0BLOC 0CE0 1-1814= 1-1793a 1-1794a 1-1795a 1-1796a RRAX2MS1BLOC 0CD0 1-1835= 1-1797a 1-1798a 1-1799a 1-1800a RRAX2MS2BLOC 0CC0 1-1856= 1-1801a 1-1802a 1-1803a 1-1804a RRAX2MS3BLOC 0CB0 1-1877= 1-1805a 1-1806a 1-1807a 1-1808a RSCR 07FD 1- 987= 1- 984a RSTSTCH 0B1B 1-3195= 1-2935v RTODATA 0011 0- 821= 0-2121v 0-2161v 0-2908v RTODELAY 00EE 0-1559= 0-1557a 0-2916a RTOERR 006A 0-1194= 0-1191v RTOGODIE 0307 0-2841= 0-1191a RTOIN 0800 0- 776= 0- 782e 0- 783e 0-1187v RTOOUT 0001 0- 819= 0- 821e 0- 825e 0- 844e 0- 845e SACKNAK 009E 0-1358= 0-1354a 0-1355a SAVEIBF 033E 0-2944= 0-1208a 0-2839a 0-2840a 0-2841a 0-2842a 0-2843a SBI2WIOR 000C 0-3316= SBSTTEST1 0966 1-2243= 1-2240a SBSTTEST2 096C 1-2252= 1-2249a SBSTTEST3 0974 1-2263= 1-2260a SBSTTEST4 097C 1-2284= 1-2281a SBSTTEST5 0984 1-2295= 1-2292a SBSTTEST6 098C 1-2305= 1-2302a SBSTTEST7 0994 1-2316= 1-2313a SCRADDRTST 0732 1- 727= 1- 718a SCRTST 07D2 1- 932= 1- 918a SCRTST1 07D4 1- 935= 1- 932a SCRTST1A 07D3 1- 934= 1- 935v SCRTST2 07DA 1- 946= 1- 941a SCRTST2A 07D6 1- 942= 1- 946v SCSTS 0253 0-2358= 0-2314a SELFTEST 0450 1- 108= 0-2022a SELFTESTSTAR 0450 0-3687= 0-3689 0-3719 0-3736e SELFTESTVECT 0FA0 1-2827= 1-2897v 1-2898v 1-2899v 1-2900v 1-2901v 1-2902v 1-2903v 1-2904v SENDLZ 0206 0-2194= 0-2180a SENDNAK 009C 0-1354= 0-1327a 0-1328a 0-1329a 0-1331a 0-1334a 0-1335a 0-1338a 0-1340a 0-1341a 0-1342a 0-1373a SENDRESP 0070 0- 659= 0-1359v SETBACKINT2W 0E5C 0-3318= 0-3314a SETDEAD 40C0 0- 651= 0-1523v SETIMED C0D0 0- 652= 0-1545v SETIMIOR 0000 0-1060= SETINT 01B0 0-1994= 0-1987a 0-1991a SETPDEAD 00DE 0-1523= 0-1511a SETPRTIM 0EE0 0-1062= 0-1058a SETRBIR 093D 1-2171= 1-2130a 1-2148a SETREOR 00C1 0-1455= 0-1446a SHIFTL2 01ED 0-2158= 0-2135a SHIFTL3 01EC 0-2157= SHIFTL4 01EB 0-2156= 0-2126a 0-2130a 0-2974a 0-3032a SKIPTEST 046B 1- 148= 1- 139a SKIPWSTE 0061 0-3739= 0-3751 SLOT 0050 0- 496= 0-1685v 0-1829v 0-1864v 0-1889v 0-2209v 0-2676v 0-2720v 0-2799v 0-3031v 0-3076v 0-3107v 0-3158v 0-3161v 0-3202v 0-3312v 0-3382v 0-3422v 0-3462v SLOT2 0064 0- 502= 0-1863v 0-2211v 0-2675v 0-2719v 0-2805v 0-3106v 0-3201v 0-3461v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 208 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table SOPBTO 0200 0- 596= 0-1162v 0-1163v 0-1166v SOPDDW 1000 0- 597= 0-2213v 0-2363v 0-2364v 0-2414v 0-2726v SOPPFW 0100 0- 595= 0-1201v 0-1202v SSSTS 0252 0-2356= 0-2313a START 0001 0- 999= 0- 997a STARTINP 0520 0- 658= 0-1317v 0-1319v STARTRD 0E81 0- 663= 0-2187v STARTWR 0681 0- 662= 0- 663e 0-2295v STERR 0EF1 0-3772= 1- 527a 1- 528a 1- 529a 1- 530a 1- 536a 1- 537a 1- 538a 1- 539a 1- 545a 1- 546a 1- 547a 1- 548a 1- 554a 1- 555a 1- 556a 1- 557a 1- 660a 1-1051a 1-1310a 1-1311a 1-1932a 1-1979a 1-1981a 1-1984a 1-2183a 1-2390a 1-2403a 1-2416a 1-2428a 1-2444a 1-2951a 1-2959a 1-2961a 1-2963a 1-2965a 1-2972a 1-2978a 1-2986a 1-2989a 1-2992a 1-3076a 1-3077a 1-3095a 1-3103a 1-3104a 1-3123a 1-3131a 1-3139a 1-3148a 1-3157a 1-3160a 1-3176a 1-3177a 1-3259a 1-3280a 1-3282a 1-3284a 1-3286a 1-3288a 1-3290a 1-3292a 1-3294a 1-3295a 1-3340a 1-3643a 1-3644a 1-3645a 1-3646a 1-3647a 1-3648a 1-3649a 1-3650a 1-3651a 1-3652a 1-3653a 1-3654a 1-3655a 1-3656a 1-3657a 1-3658a 1-3681a 1-3683a 1-3685a 1-3687a 1-3689a 1-3691a 1-3713a 1-3715a 1-3717a 1-3719a 1-3721a 1-3723a STILLBZ 00BE 0-1450= 0-1447a STSCLBTS FFE5 0- 921= 0-2262v STSTATMASK CF40 1-2232= 1-2239v 1-2248v 1-2259v 1-2280v 1-2291v 1-2301v 1-2311v SXFER 0ADD 1-3090= 1-3069a TCON 0050 0-3712= 1-2913v 1-2920v 1-2921v 1-2924v 1-2929v 1-2931v 1-2932v TEMP 00B0 0- 525= 0-1158v 0-1167v 0-1186v 0-1320v 0-1321v 0-1386v 0-1388v 0-1503v 0-1504v 0-1535v 0-1536v 0-1733v 0-1744v 0-1760v 0-1762v 0-1771v 0-1791v 0-1794v 0-1803v 0-1827v 0-1897v 0-1987v 0-1991v 0-1994v 0-2121v 0-2122v 0-2126v 0-2130v 0-2135v 0-2156v 0-2157v 0-2158v 0-2159v 0-2161v 0-2162v 0-2249v 0-2251v 0-2316v 0-2318v 0-2791v 0-2800v 0-2806v 0-2974v 0-3032v 0-3034v 0-3035v TEMP2 00B4 0- 526= 0-2084v 0-2089v 0-2093v 0-2099v 0-2101v 0-2106v TESTBUSER 099F 1-2356= TESTBUSER1 09A3 1-2360= 1-2529a TESTBUSER11 09AD 1-2395= 1-2366a TESTBUSER12 09B7 1-2409= 1-2367a TESTBUSER13 09BF 1-2421= 1-2368a TESTBUSER2 09A4 1-2361= 1-2528a TESTBUSER20 09A5 1-2385= 1-2365a 1-2464a TESTBUSER21 09AE 1-2398= 1-2474a TESTBUSER22 09B8 1-2411= 1-2479a TESTBUSER23 09C0 1-2423= 1-2374a TESTBUSER31 09C8 1-2435= 1-2369a 1-2439a TESTBUSER32 09D4 1-2453= 1-2370a TESTBUSER33 09DA 1-2464= 1-2371a TESTBUSER34 09E1 1-2474= 1-2372a TESTBUSER35 09E2 1-2479= 1-2373a 1-2482a TESTBUSER40 09CC 1-2441= 1-2435a 1-2453a TESTBUSER41 09D0 1-2446= 1-2435v TESTBUSER42 09D6 1-2457= 1-2453v TESTBUSER43 09DD 1-2469= 1-2374v 1-2464v 1-2474v 1-2479v TESTBUSER5 09F3 1-2506= 1-2502a TESTBUSER7 0A06 1-2528= 1-2525a TESTBUSERBLO 0C80 1-2365= 1-2361a TESTCARY 083F 1-1067= 1- 947a TESTCARY0 0854 1-1125= 1-1102a TESTCARY1 0856 1-1127= 1-1139a TESTCARY2 0861 1-1144= 1-1136a TESTCARY3 0863 1-1146= 1-1158a TESTCARY5 086F 1-1166= 1-1156a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 209 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table TESTDIR 0263 0-2412= 0-2387a 0-2392a TESTDIR2 02AF 0-2638= 0-2630a 0-2635a TESTERRFLAG 045A 1- 124= 1- 117a TESTODD2 02B2 0-2647= 0-2641a TESTTEMP 00B0 0-3716= 1-3309v 1-3316v 1-3323v 1-3324v 1-3333v 1-3339v 1-3342v 1-3354v 1-3361v 1-3362v 1-3406v 1-3412v 1-3463v 1-3531v 1-3611v 1-3663v 1-3701v TIMBYRD 0018 0- 571= 0-1125v TIMBYTC 0200 0- 570= 0-1128v TIMBYWR 000C 0- 572= 0-1126v TIMECNST 053C 0- 563= 0-1316v 0-2189v 0-2297v TIMECSIN 0004 0- 565= 0-1322v TIMEDOUT 8000 0- 649= 0- 652e TIMEROFF 0090 0-1316= 0-1314a TIMERSPX 0001 0- 566= 0-2036v TIMERW 0003 0- 567= 0-2191v TIMEWW 0006 0- 568= 0-2300v TIMIDLE 0001 0- 564= 0-1100v TIMING 0400 0- 644= 0- 655e 0- 658e 0- 662e 0-1102v 0-1314v 0-1395v TOENDLOOP 099E 1-2339= 1-2330a 1-2338a TOLOOP 0997 1-2332= 1-2339a TOTESTFAIL 099C 1-2337= 1-2335a TST2BUSERRFI 09C6 1-2430= 1-2365v 1-2395v 1-2409v 1-2421v TST3BUSERRFI 09E5 1-2484= 1-2449a 1-2460a 1-2470a TSTBEDOXFER 09E8 1-2488= 1-2431a 1-2486a TSTBENOTIBF 09EA 1-2492= 1-2488a 1-2490a TSTBUSDATA 0B7E 1-3405= 1-3365a TSTBUSDATA0 0B82 1-3411= 1-3614a TSTBUSDATA1 0B8A 1-3424= 1-3441a TSTBUSDATA12 0BAD 1-3477= 1-3500a TSTBUSDATA13 0BAE 1-3478= 1-3511a TSTBUSDATA14 0BB3 1-3485= 1-3477v TSTBUSDATA15 0BC5 1-3511= 1-3529a TSTBUSDATA16 0BC7 1-3514= 1-3511v TSTBUSDATA17 0BD4 1-3529= 1-3527a TSTBUSDATA2 0B8F 1-3430= 1-3424v TSTBUSDATA22 0BDD 1-3545= 1-3569a TSTBUSDATA23 0BDE 1-3546= 1-3582a TSTBUSDATA24 0BE5 1-3554= 1-3545v TSTBUSDATA25 0BF9 1-3582= 1-3601a TSTBUSDATA26 0BFB 1-3585= 1-3582v TSTBUSDATA27 0C08 1-3601= 1-3598a TSTBUSDATA3 0B8B 1-3425= 1-3449a TSTBUSDATA4 0B9B 1-3449= 1-3460a 1-3461a TSTBUSDATA5 0B9D 1-3452= 1-3449v TSTCHKXFER 0B34 1-3270= 1-3730a TSTDOXFERCHK 0B24 1-3245= 1-2590a 1-2641a 1-3317a 1-3355a 1-3427a 1-3482a 1-3551a TSTFLAGS 0B4C 1-3305= 1-3211a TSTFLAGS0 0B55 1-3314= 1-3328v TSTFLAGS1 0B56 1-3315= 1-3313a TSTFLAGS2 0B59 1-3320= 1-3317v TSTFLAGS4 0B5F 1-3328= 1-3324a TSTFLAGS5 0B60 1-3332= 1-3328a 1-3366a TSTFLAGS6 0B71 1-3350= 1-3366v TSTFLAGS7 0B77 1-3358= 1-3355v TSTFLAGS8 0B7D 1-3366= 1-3362a TSTFLAGS9 0B73 1-3352= 1-3349a TSTFLAGSLOOP 0B65 1-3337= 1-3335a 1-3338a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 210 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table TSTFLAGSTW 0B69 1-3342= 1-3327a TSTRFR2SW 0C0F 1-3662= 1-3606a TSTRFR2SW2 0C1B 1-3675= 1-3750a TSTRFR2SW4 0C2C 1-3697= 1-3693a TSTRFR2SW6 0C30 1-3705= 1-3701a TSTRFR2SW8 0C42 1-3729= 1-3725a TSTRFR2SWA 0C45 1-3734= 1-3730v TSTRFR2SWC 0C52 1-3750= 1-3747a TSTRFR2SWVEC 0FB0 1-3643= 1-3664v TSTXFER2 0B3B 1-3279= 1-3276a TSTXFERNOTIB 0B32 1-3266= 1-3249a 1-3260a 1-3264a TSTXFERRFI 0B27 1-3250= 1-3246a TWOWORDS 0F70 0-3502= 0-1032v 0-1965v 0-3564v 0-3646v TWOWRDS1 041E 0-3523= 0-3503a TWT 1000 0- 814= 0- 824e TYPECKSM 0020 0- 481= 0-1330v 0-1332v 0-1333v 0-1336v 0-1337v 0-1339v 0-1350v 0-1354v 0-1355v 0-1358v 0-1366v 0-1367v 0-1368v 0-1373v 0-1385v 0-1391v 0-1467v 0-1469v 0-1470v 0-1483v 0-1492v 0-1498v 0-1499v 0-1512v 0-1518v 0-1519v 0-2188v 0-2296v VECTCK 0014 0-3704= 1-2946v 1-3119v 1-3135v 1-3142v VECTORADD 0FB0 0-1941= 0-1960 0-1960e 0-2818= 0-2837 0-2837e 0-3048= 0-3067 0-3067e 0-3125= 0-3144 0-3144e 0-3286= 0-3305 0-3305e 0-3347= 0-3366 0-3366e 0-3399= 0-3418 0-3418e 0-3500= 0-3519 0-3519e 0-3534= 0-3553 0-3553e 0-3573= 0-3592 0-3592e 1-2826= 1-2843 1-2843e 1-3642= 1-3659 1-3659e VECTORON 0000 0- 426= 0-1941 0-1941= 0-1960= 0-2818 0-2818= 0-2837= 0-3048 0-3048= 0-3067= 0-3125 0-3125= 0-3144= 0-3286 0-3286= 0-3305= 0-3347 0-3347= 0-3366= 0-3399 0-3399= 0-3418= 0-3500 0-3500= 0-3519= 0-3534 0-3534= 0-3553= 0-3573 0-3573= 0-3592= 1-2826 1-2826= 1-2843= 1-3642 1-3642= 1-3659= VECTORORG 0FC0 0- 425= 0-1941 0-1941 0-1941e 0-1941= 0-2818 0-2818 0-2818e 0-2818= 0-3048 0-3048 0-3048e 0-3048= 0-3125 0-3125 0-3125e 0-3125= 0-3286 0-3286 0-3286e 0-3286= 0-3347 0-3347 0-3347e 0-3347= 0-3399 0-3399 0-3399e 0-3399= 0-3500 0-3500 0-3500e 0-3500= 0-3534 0-3534 0-3534e 0-3534= 0-3573 0-3573 0-3573e 0-3573= 1-2826 1-2826 1-2826e 1-2826= 1-3642 1-3642 1-3642e 1-3642= 0-3737e VECTORSLEFT 0004 0-3737= 0-3748 WAITING 0800 0- 645= 0- 655e 0- 656e 0- 663e 0-1392v 0-1413v 0-1546v WASNAK 00D5 0-1508= 0-1504a WB2INTSON 02CE 0-2696= 0-2683a 0-2689a 0-2690a 0-2691a 0-2692a WB2NOT1W 02CC 0-2683= 0-2680a WB2O1WIOR 0000 0-2687= WB2O1WIP 0E50 0-2689= 0-2684a WCADR89 0896 1-1263= WDCNT 0018 0-3705= 1-2891v 1-2988v 1-3131v WFBCKFRE 01C5 0-2082= 0-2088a WFBERR 01D4 0-2114= 0-2111v WFBGSTAT 01C8 0-2088= 0-2084a 0-2093a WFBNAVAL 01CB 0-2093= 0-2079a WFBOUTS 01CA 0-2092= 0-2107a WFBSTG2 01CC 0-2099= 0-2089a WFBSTG2Q 01CF 0-2104= 0-2110a WFBSTG2Y 01D2 0-2110= 0-2101a 0-2106a WFBTO 0064 0- 581= 0-2093v WFBTO2 04E2 0- 582= 0-2101v WNOTDEAD 0231 0-2289= 0-2285a WNOTFREE 0232 0-2292= 0-2289a WONE89 0884 1-1228= WORD1DATA 1000 0- 799= 0-3558v 0-3605v WPTNOTKN 0226 0-2274= 0-2272a WRALL89 08A0 1-1299= 1-1212a 1-1230a 1-1248a 1-1265a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 211 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table WRALL89BLOCK 0E00 1-1304= 1-1299a WRALL89IOR 0000 1-1303= 1-1207v WRALLRADRX1 090D 1-2085= 1-1304a WRALLRADRX1R 0919 1-2100= 1-1305a WRALLRADRX2 0925 1-2127= 1-1306a WRALLRADRX2R 0931 1-2145= 1-1307a WRALLX1 08A2 1-1343= 1-1308a WRALLX1A 08A4 1-1345= 1-1355a WRALLX1C 08A9 1-1352= 1-1348a WRALLX2 08AC 1-1466= 1-1309a WRALLX2A 08B8 1-1478= 1-1491a WRALLX2C 08BD 1-1484= 1-1480a WRALLX2D 08AE 1-1468= 1-1492a WRALLX2E 08C0 1-1491= 1-1488a WRARX1LOOP 090F 1-2087= 1-2098v WRARX1NOTDON 0915 1-2094= 1-2090a WRARX1RLOOP 091B 1-2102= 1-2113v WRARX1RNOTDO 0921 1-2109= 1-2105a WRARX2LOOP 0927 1-2129= 1-2140v WRARX2NOTDON 092D 1-2136= 1-2132a WRARX2RLOOP 0933 1-2147= 1-2158v WRARX2RNOTDO 0939 1-2154= 1-2150a WRAX1LSBLK 0DE0 1-1359= 1-1347a WRAX1MS0BLK 0DD0 1-1380= 1-1359a 1-1360a 1-1361a 1-1362a WRAX1MS1BLK 0DC0 1-1401= 1-1363a 1-1364a 1-1365a 1-1366a WRAX1MS2BLK 0DB0 1-1422= 1-1367a 1-1368a 1-1369a 1-1370a WRAX1MS3BLK 0DA0 1-1443= 1-1371a 1-1372a 1-1373a 1-1374a WRAX2LSBLK 0D90 1-1497= 1-1479a WRAX2MS0BLK 0D80 1-1518= 1-1497a 1-1498a 1-1499a 1-1500a WRAX2MS1BLK 0D70 1-1539= 1-1501a 1-1502a 1-1503a 1-1504a WRAX2MS2BLK 0D60 1-1560= 1-1505a 1-1506a 1-1507a 1-1508a WRAX2MS3BLK 0D50 1-1581= 1-1509a 1-1510a 1-1511a 1-1512a WRDSLEFT 001A 0-3736= 0-3746 WRISUS 022E 0-2284= 0-2281a WRITBITS 8063 0- 845= 0-2795v WRITE 0000 0- 841= 0- 845e 0- 848e WRITE2W 7000 0- 842= 0- 848e WRITEB2A 02BD 0-2663= 0-2654a WRITEB2B 02BE 0-2666= 0-2663a WRITEBC 0270 0-2462= 0-2435a 0-2436a 0-2437a 0-2438a WRITEBC1 0271 0-2463= 0-2455a 0-2460a WRITEBC2 02BA 0-2660= 0-2650a WRMODENOTTW 0256 0-2363= 0-2319a WRNOTLEG 023C 0-2305= 0-2284a WRTAB 0E70 0-2311= 0-2306a WRTABABT 0E71 0-2312= 0-2338a WRUIOR 0008 0-2142= 0-2139v WRULEGAL 01D6 0-2118= 0-2021a WRULOOP 044C 0-3680= 0-3677a WRULOOP1 0445 0-3671= 0-3667a WRULOOPA 0443 0-3669= 0-3680a WRUNOT0 01DC 0-2126= 0-2123a WRURES1A 0090 0- 515= 0-1023v 0-2133v 0-2144v 0-2987v 0-3011v 0-3026v 0-3676v WRURES1B 0094 0- 516= 0-1024v 0-2151v 0-2989v 0-3012v 0-3027v 0-3675v WRURES2A 0098 0- 517= 0-2145v 0-2953v 0-2955v 0-2957v 0-2990v 0-3013v 0-3028v 0-3674v WRURES2B 009C 0- 518= 0-2152v 0-2959v 0-2961v 0-2991v 0-3014v 0-3029v 0-3673v WRURES3A 00A0 0- 519= 0-1016v 0-2146v 0-2963v 0-3003v 0-3018v 0-3672v 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 212 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table WRURES3B 00A4 0- 520= 0-1017v 0-2153v 0-2965v 0-3004v 0-3019v 0-3671v WRURES4A 00A8 0- 521= 0-1013v 0-2147v 0-2967v 0-3005v 0-3020v 0-3670v 0-3726v WRURES4B 00AC 0- 522= 0-3717e 0-3729 0-1014v 0-2154v 0-2969v 0-3006v 0-3021v 0-3669v WRUTABLE 0EE8 0-2144= 0-2140a WSCR 07DC 1- 953= 1- 935a 1- 946a WSTE0000 0006 0-1004= WSTE0001 003D 0-1085= WSTE0002 008E 0-1313= WSTE0003 00A9 0-1389= WSTE0004 00B5 0-1430= WSTE0005 00D3 0-1505= WSTE0006 00E3 0-1539= WSTE0007 00F2 0-1577= WSTE0008 00FF 0-1609= WSTE0009 0114 0-1681= WSTE0010 0130 0-1748= WSTE0011 0140 0-1775= WSTE0012 014F 0-1800= WSTE0013 0155 0-1808= WSTE0014 017F 0-1876= WSTE0015 018F 0-1904= WSTE0016 01A6 0-1975= WSTE0017 01B2 0-2003= WSTE0018 01D5 0-2116= WSTE0019 01DB 0-2124= WSTE0020 01F5 0-2167= WSTE0021 01F8 0-2173= WSTE0022 0219 0-2252= WSTE0023 0221 0-2264= WSTE0024 022D 0-2282= WSTE0025 023B 0-2303= WSTE0026 0241 0-2333= WSTE0027 0255 0-2361= WSTE0028 0262 0-2411= WSTE0029 026A 0-2452= WSTE0030 0289 0-2541= WSTE0031 0299 0-2593= WSTE0032 02AE 0-2637= WSTE0033 02B3 0-2648= WSTE0034 02CB 0-2681= WSTE0035 02E7 0-2742= WSTE0036 02F3 0-2765= WSTE0037 02F9 0-2793= WSTE0038 031D 0-2883= WSTE0039 0329 0-2903= WSTE0040 0397 0-3085= WSTE0041 03BF 0-3185= WSTE0042 03D3 0-3245= WSTE0043 03E1 0-3273= WSTE0044 03F3 0-3386= WSTE0045 0422 0-3557= WSTE0046 046A 1- 147= WSTE0047 047C 1- 171= WSTE0048 06CE 1- 469= WSTE0049 06D4 1- 477= WSTE0050 06DA 1- 485= WSTE0051 06DE 1- 495= 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 213 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table WSTE0052 06E4 1- 503= WSTE0053 06EA 1- 511= WSTE0054 06F0 1- 519= WSTE0055 06FA 1- 575= WSTE0056 0707 1- 648= WSTE0057 07FC 1- 986= WSTE0058 083E 1-1065= WSTE0059 0881 1-1219= WSTE0060 088B 1-1237= WSTE0061 08BB 1-1482= WSTE0062 08DD 1-1778= WSTE0063 0913 1-2092= WSTE0064 091F 1-2107= WSTE0065 092B 1-2134= WSTE0066 0937 1-2152= WSTE0067 098B 1-2304= WSTE0068 099B 1-2336= WSTE0069 09AB 1-2392= WSTE0070 09B4 1-2405= WSTE0071 09DF 1-2471= WSTE0072 0A29 1-2607= WSTE0073 0A49 1-2658= WSTE0074 0A51 1-2880= WSTE0075 0A7A 1-2949= WSTE0076 0AA2 1-3019= WSTE0077 0AC7 1-3065= WSTE0078 0AD4 1-3080= WSTE0079 0ADE 1-3092= WSTE0080 0AF8 1-3133= WSTE0081 0B1A 1-3193= WSTE0082 0B30 1-3263= WSTE0083 0B5D 1-3325= WSTE0084 0B64 1-3336= WSTE0085 0B7B 1-3363= WSTE0086 0B8E 1-3429= WSTE0087 0B9C 1-3451= WSTE0088 0BC6 1-3513= WSTE0089 0BD3 1-3528= WSTE0090 0BE4 1-3553= WSTE0091 0BFA 1-3584= WSTE0092 0C07 1-3599= WSTE0093 0C2F 1-3703= WSTE0094 0C41 1-3727= WSTE0095 0C44 1-3733= WSTE0096 0C51 1-3748= WSTECNTR 0061 0- 278= 0-1004 0-1004e 0-1004= 0-1085 0-1085e 0-1085= 0-1313 0-1313e 0-1313= 0-1389 0-1389e 0-1389= 0-1430 0-1430e 0-1430= 0-1505 0-1505e 0-1505= 0-1539 0-1539e 0-1539= 0-1577 0-1577e 0-1577= 0-1609 0-1609e 0-1609= 0-1681 0-1681e 0-1681= 0-1748 0-1748e 0-1748= 0-1775 0-1775e 0-1775= 0-1800 0-1800e 0-1800= 0-1808 0-1808e 0-1808= 0-1876 0-1876e 0-1876= 0-1904 0-1904e 0-1904= 0-1975 0-1975e 0-1975= 0-2003 0-2003e 0-2003= 0-2116 0-2116e 0-2116= 0-2124 0-2124e 0-2124= 0-2167 0-2167e 0-2167= 0-2173 0-2173e 0-2173= 0-2252 0-2252e 0-2252= 0-2264 0-2264e 0-2264= 0-2282 0-2282e 0-2282= 0-2303 0-2303e 0-2303= 0-2333 0-2333e 0-2333= 0-2361 0-2361e 0-2361= 0-2411 0-2411e 0-2411= 0-2452 0-2452e 0-2452= 0-2541 0-2541e 0-2541= 0-2593 0-2593e 0-2593= 0-2637 0-2637e 0-2637= 0-2648 0-2648e 0-2648= 0-2681 0-2681e 0-2681= 0-2742 0-2742e 0-2742= 0-2765 0-2765e 0-2765= 0-2793 0-2793e 0-2793= 0-2883 0-2883e 0-2883= 0-2903 0-2903e 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 214 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-2903= 0-3085 0-3085e 0-3085= 0-3185 0-3185e 0-3185= 0-3245 0-3245e 0-3245= 0-3273 0-3273e 0-3273= 0-3386 0-3386e 0-3386= 0-3557 0-3557e 0-3557= 1- 147 1- 147e 1- 147= 1- 171 1- 171e 1- 171= 1- 469 1- 469e 1- 469= 1- 477 1- 477e 1- 477= 1- 485 1- 485e 1- 485= 1- 495 1- 495e 1- 495= 1- 503 1- 503e 1- 503= 1- 511 1- 511e 1- 511= 1- 519 1- 519e 1- 519= 1- 575 1- 575e 1- 575= 1- 648 1- 648e 1- 648= 1- 986 1- 986e 1- 986= 1-1065 1-1065e 1-1065= 1-1219 1-1219e 1-1219= 1-1237 1-1237e 1-1237= 1-1482 1-1482e 1-1482= 1-1778 1-1778e 1-1778= 1-2092 1-2092e 1-2092= 1-2107 1-2107e 1-2107= 1-2134 1-2134e 1-2134= 1-2152 1-2152e 1-2152= 1-2304 1-2304e 1-2304= 1-2336 1-2336e 1-2336= 1-2392 1-2392e 1-2392= 1-2405 1-2405e 1-2405= 1-2471 1-2471e 1-2471= 1-2607 1-2607e 1-2607= 1-2658 1-2658e 1-2658= 1-2880 1-2880e 1-2880= 1-2949 1-2949e 1-2949= 1-3019 1-3019e 1-3019= 1-3065 1-3065e 1-3065= 1-3080 1-3080e 1-3080= 1-3092 1-3092e 1-3092= 1-3133 1-3133e 1-3133= 1-3193 1-3193e 1-3193= 1-3263 1-3263e 1-3263= 1-3325 1-3325e 1-3325= 1-3336 1-3336e 1-3336= 1-3363 1-3363e 1-3363= 1-3429 1-3429e 1-3429= 1-3451 1-3451e 1-3451= 1-3513 1-3513e 1-3513= 1-3528 1-3528e 1-3528= 1-3553 1-3553e 1-3553= 1-3584 1-3584e 1-3584= 1-3599 1-3599e 1-3599= 1-3703 1-3703e 1-3703= 1-3727 1-3727e 1-3727= 1-3733 1-3733e 1-3733= 1-3748 1-3748e 1-3748= 0-3739e WSTEPNTR 0000 0- 279= 0-3739e WTFORBUS 01C2 0-2077= 0-1460a 0-1550a 0-1689a 0-1823a 0-1885a 0-2033a WTFORPON 0345 0-2952= 0-2011a 0-2938a 0-2950a XCHG 0700 1- 639= 1- 581a XCHG0 070A 1- 651= 1- 646a XCHG0A 0708 1- 649= 1- 651v XCHGTST 070C 1- 656= 1- 651a XORCF1W 1000 0- 847= 0-3349v 0-3350v 0-3351v 0-3352v XORFF1W 0004 0- 823= 0-3382v XORHADDR2W 7000 0- 848= 0-3127v 0-3128v 0-3129v 0-3130v XORSLOT2W 1000 0- 824= 0-3158v 0-3161v YESRETRY 00D7 0-1512= 0-1508a 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 215 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table BLOCK 7220 0- 331 0-1060 0-1224 0-1325 0-1371 0-1401 0-1475 0-1488 0-1707 0-2015 0-2142 0-2203 0-2309 0-2432 0-2442 0-2505 0-2514 0-2557 0-2687 0-2771 0-3176 0-3316 0-3338 0-3373 0-3621 0-3635 1- 525 1- 534 1- 543 1- 552 1- 583 1- 604 1-1303 1-1316 1-1358 1-1379 1-1400 1-1421 1-1442 1-1496 1-1517 1-1538 1-1559 1-1580 1-1632 1-1653 1-1674 1-1695 1-1716 1-1792 1-1813 1-1834 1-1855 1-1876 1-1929 1-1938 1-1959 1-2364 1-2998 1-3108 BUSMACROS 0000 1- 378 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 ENDBLOCK 0805 0- 372 0-1067 0-1243 0-1344 0-1382 0-1420 0-1486 0-1495 0-1718 0-2026 0-2149 0-2222 0-2328 0-2440 0-2450 0-2512 0-2521 0-2564 0-2694 0-2778 0-3183 0-3323 0-3345 0-3380 0-3628 0-3642 1- 532 1- 541 1- 550 1- 559 1- 602 1- 623 1-1312 1-1321 1-1375 1-1396 1-1417 1-1438 1-1459 1-1513 1-1534 1-1555 1-1576 1-1597 1-1649 1-1670 1-1691 1-1712 1-1733 1-1809 1-1830 1-1851 1-1872 1-1893 1-1934 1-1955 1-1976 1-2381 1-3017 1-3115 ENDVECTOR 23FE 0- 413 0-1960 0-2837 0-3067 0-3144 0-3305 0-3366 0-3418 0-3519 0-3553 0-3592 1-2843 1-3659 EVEN 0000 0- 253 0-2523 1- 123 1- 637 1- 648 1- 655 1- 682 1- 725 1-1124 1-1219 1-1237 1-1254 1-1271 1-1277 1-1350 1-1482 1-1490 1-1624 1-1736 1-1778 1-1786 1-2005 1-2013 1-2050 1-2057 1-2065 1-2092 1-2107 1-2134 1-2152 1-2218 1-2242 1-2251 1-2262 1-2283 1-2294 1-2304 1-2315 1-2336 1-2392 1-2418 1-2433 1-2451 1-2462 1-2471 1-2477 1-2526 1-2573 1-2607 1-2624 1-2658 1-2872 1-2880 1-2890 1-3065 1-3153 1-3162 1-3199 1-3247 1-3325 1-3363 1-3528 1-3599 1-3695 1-3703 1-3727 1-3748 HALT 696E 0- 455 0-1004 0-1085 0-1194 0-1195 0-1210 0-1230 0-1231 0-1232 0-1235 0-1236 0-1237 0-1313 0-1378 0-1379 0-1380 0-1389 0-1403 0-1404 0-1405 0-1407 0-1410 0-1411 0-1414 0-1416 0-1417 0-1418 0-1430 0-1505 0-1539 0-1577 0-1609 0-1681 0-1709 0-1737 0-1748 0-1764 0-1775 0-1796 0-1800 0-1808 0-1834 0-1876 0-1904 0-1962 0-1975 0-2003 0-2013 0-2114 0-2116 0-2124 0-2167 0-2173 0-2252 0-2264 0-2282 0-2303 0-2333 0-2361 0-2411 0-2452 0-2541 0-2593 0-2637 0-2648 0-2681 0-2742 0-2765 0-2793 0-2845 0-2847 0-2849 0-2883 0-2903 0-3071 0-3085 0-3146 0-3185 0-3245 0-3273 0-3307 0-3368 0-3386 0-3420 0-3521 0-3555 0-3557 0-3594 0-3623 0-3637 1- 147 1- 171 1- 469 1- 477 1- 485 1- 495 1- 503 1- 511 1- 519 1- 575 1- 648 1- 986 1-1065 1-1219 1-1237 1-1482 1-1778 1-2092 1-2107 1-2134 1-2152 1-2304 1-2336 1-2392 1-2405 1-2471 1-2607 1-2658 1-2880 1-2949 1-3019 1-3065 1-3080 1-3092 1-3133 1-3193 1-3263 1-3325 1-3336 1-3363 1-3429 1-3451 1-3513 1-3528 1-3553 1-3584 1-3599 1-3703 1-3727 1-3733 1-3748 0-3771 0-3772 LITANDIORRAM 0000 1- 257 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 LITANDLIT 0000 1- 217 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 LITIORLIT 0000 1- 218 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 LITRAMLITSCR 0000 1- 358 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 LITRAMSCRXOR 0000 1- 318 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 ODD 0000 0- 267 1- 147 1- 171 1- 461 1- 469 1- 477 1- 485 1- 495 1- 503 1- 511 1- 519 1- 567 1- 575 1- 933 1- 986 1-1065 1-1142 1-2405 1-2489 1-2504 1-2592 1-2643 1-2916 1-2949 1-2981 1-3019 1-3080 1-3092 1-3133 1-3193 1-3263 1-3278 1-3319 1-3336 1-3357 1-3429 1-3451 1-3484 1-3513 1-3553 1-3584 1-3733 REP 042E 0- 431 0-1067 0-1243 0-1344 0-1382 0-1420 0-1486 0-1495 0-1718 0-1960 0-2026 0-2149 0-2222 0-2328 0-2440 0-2450 0-2512 0-2521 0-2564 0-2694 0-2778 0-2837 0-3067 0-3144 0-3183 0-3305 0-3323 0-3345 0-3366 0-3380 0-3418 0-3519 0-3553 0-3592 0-3628 0-3642 1- 532 1- 541 1- 550 1- 559 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 216 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1- 602 1- 623 1-1312 1-1321 1-1375 1-1396 1-1417 1-1438 1-1459 1-1513 1-1534 1-1555 1-1576 1-1597 1-1649 1-1670 1-1691 1-1712 1-1733 1-1809 1-1830 1-1851 1-1872 1-1893 1-1934 1-1955 1-1976 1-2381 1-2843 1-3017 1-3115 1-3659 SCRADDRAM 0000 1- 415 1- 430 1- 431 1- 432 1- 433 1- 434 1- 435 1- 436 1- 437 1- 438 1- 439 1- 440 1- 441 1- 442 1- 443 1- 444 1- 445 SCRANDIORLIT 0000 1- 236 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 SCRXORRAM 0000 1- 278 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 SCRXORRAMNAL 0000 1- 298 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 SKIPORG F000 0- 252 0-1085 0-1103 0-1160 0-1179 0-1184 0-1199 0-1251 0-1352 0-1389 0-1430 0-1440 0-1457 0-1505 0-1539 0-1609 0-1643 0-1657 0-1800 0-1808 0-1836 0-1844 0-1876 0-1904 0-1916 0-1926 0-2116 0-2124 0-2167 0-2197 0-2240 0-2246 0-2252 0-2264 0-2282 0-2303 0-2333 0-2361 0-2377 0-2395 0-2495 0-2541 0-2584 0-2593 0-2598 0-2624 0-2648 0-2664 0-2681 0-2710 0-2727 0-2732 0-2742 0-2754 0-2765 0-2793 0-2883 0-2893 0-2903 0-2910 0-2925 0-2931 0-2994 0-3079 0-3085 0-3096 0-3113 0-3153 0-3185 0-3191 0-3245 0-3263 0-3273 0-3386 0-3425 0-3450 0-3467 0-3473 0-3611 0-3678 STARTSKP 0000 0- 266 0-1004 0-1129 0-1313 0-1466 0-1571 0-1577 0-1598 0-1675 0-1681 0-1721 0-1740 0-1748 0-1767 0-1775 0-1975 0-2003 0-2081 0-2103 0-2173 0-2271 0-2411 0-2452 0-2637 0-2867 0-2978 0-3168 0-3325 0-3557 0-3596 0-3604 TITLE.MAC 208C 0- 19 0- 24 0- 80 0- 136 0- 230 0- 464 0- 529 0- 927 0- 963 0-1091 0-1211 0-1305 0-1465 0-1524 0-1561 0-1587 0-1967 0-1996 0-2115 0-2160 0-2270 0-2366 0-2615 0-2779 0-2811 0-3041 0-3118 0-3331 0-3647 0-3700 1- 1 1- 58 1- 188 1- 449 1- 624 1- 672 1- 719 1- 919 1- 948 1-1052 1-1182 1-1281 1-1599 1-1897 1-1985 1-2071 1-2184 1-2224 1-2317 1-2340 1-2531 1-2662 1-3178 1-3213 1-3296 1-3368 1-3615 0-3722 0-3734 0-3775 VECTOR 0000 0- 401 0-1941 0-2818 0-3048 0-3125 0-3286 0-3347 0-3399 0-3500 0-3534 0-3573 1-2826 1-3642 WASTE 0000 0- 256 0-1004 0-1313 0-1577 0-1681 0-1748 0-1775 0-1975 0-2003 0-2173 0-2411 0-2452 0-2637 0-3557 1- 147 1- 171 1- 469 1- 477 1- 485 1- 495 1- 503 1- 511 1- 519 1- 575 1- 986 1-1065 1-2405 1-2949 1-3019 1-3080 1-3092 1-3133 1-3193 1-3263 1-3336 1-3429 1-3451 1-3513 1-3553 1-3584 1-3733 XLITSCRRAMXO 0000 1- 338 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 217 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table A 0001 1-2003 1-2048 1-2089 1-2104 1-2131 1-2149 C 0001 1-3125 0-1828 0-3050 0-3051 0-3052 0-3053 0-3127 0-3128 0-3129 0-3130 0-3152 0-3288 0-3289 0-3290 0-3291 0-3349 0-3350 0-3351 0-3352 0-3401 0-3402 0-3403 0-3404 0-3427 0-3444 1-3130 CLC 0003 1-1096 1-1127 1-1147 CST 0002 1-1098 1-1148 1-2601 1-2603 1-2652 1-2654 1-3437 1-3458 1-3494 1-3522 1-3523 1-3524 1-3525 1-3563 1-3593 1-3594 1-3595 1-3596 1-3742 1-3743 1-3744 1-3745 0-1167 0-1177 0-1665 0-1882 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1-3332 1-3333 1-3334 1-3336 1-3342 1-3343 1-3344 1-3345 1-3346 1-3347 1-3348 1-3349 1-3352 1-3354 1-3361 1-3362 1-3363 1-3405 1-3406 1-3407 1-3408 1-3411 1-3412 1-3418 1-3419 1-3420 1-3421 1-3422 1-3423 1-3429 1-3439 1-3447 1-3448 1-3451 1-3463 1-3464 1-3471 1-3472 1-3473 1-3474 1-3475 1-3476 1-3498 1-3507 1-3508 1-3509 1-3510 1-3513 1-3526 1-3527 1-3528 1-3531 1-3532 1-3539 1-3540 1-3541 1-3542 1-3543 1-3544 1-3553 1-3567 1-3576 1-3577 1-3578 1-3579 1-3580 1-3581 1-3584 1-3597 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 225 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1-3598 1-3599 1-3611 1-3612 1-3643 1-3644 1-3645 1-3646 1-3647 1-3648 1-3649 1-3650 1-3651 1-3652 1-3653 1-3654 1-3655 1-3656 1-3657 1-3658 1-3662 1-3663 1-3664 1-3665 1-3666 1-3667 1-3668 1-3669 1-3670 1-3671 1-3672 1-3673 1-3675 1-3678 1-3697 1-3703 1-3705 1-3710 1-3727 1-3729 1-3733 1-3746 1-3748 0-3723 0-3725 0-3727 0-3771 0-3772 PTST 0004 0-1122 0-1220 0-1575 0-1601 0-1679 0-1720 0-1739 0-1747 0-1766 0-1774 0-1798 0-1806 0-1838 0-1914 0-1922 1-2882 1-2982 1-3172 1-3201 SBFT 001E 0-2879 0-2950 0-2972 1-2211 1-2332 1-2502 1-3276 SBHC 0017 0-1944 0-2877 0-2946 0-2987 0-3503 0-3537 0-3561 0-3614 0-3638 0-3639 0-3640 1-2497 1-2953 1-3069 1-3125 1-3271 SBHD 001B 0-2888 0-2948 0-2990 0-3524 0-3624 0-3625 0-3626 1-2500 1-2955 1-3127 1-3274 SBLC 0019 0-1964 0-2878 0-2947 0-2989 0-3523 0-3563 0-3616 0-3644 1-2498 1-2954 1-3126 1-3272 SBLD 001D 0-2889 0-2949 0-2991 0-3525 0-3630 1-2501 1-2956 1-3128 1-3275 SBST 0014 0-1007 0-1141 0-1190 0-1191 0-1197 0-1206 0-1728 0-1755 0-1786 0-1818 0-1945 0-1946 0-1947 0-1948 0-1949 0-1950 0-1951 0-1952 0-1953 0-1954 0-1955 0-1956 0-1957 0-1958 0-2078 0-2088 0-2110 0-2111 0-2828 0-2829 0-2830 0-2831 0-2832 0-2833 0-2834 0-2835 0-2870 0-2874 0-2875 0-2986 0-3058 0-3059 0-3060 0-3061 0-3062 0-3063 0-3064 0-3065 0-3135 0-3136 0-3137 0-3138 0-3139 0-3140 0-3141 0-3142 0-3296 0-3297 0-3298 0-3299 0-3300 0-3301 0-3302 0-3303 0-3357 0-3358 0-3359 0-3360 0-3361 0-3362 0-3363 0-3364 0-3409 0-3410 0-3411 0-3412 0-3413 0-3414 0-3415 0-3416 0-3504 0-3505 0-3506 0-3507 0-3508 0-3509 0-3510 0-3511 0-3512 0-3513 0-3514 0-3515 0-3516 0-3517 0-3536 0-3538 0-3539 0-3540 0-3541 0-3542 0-3543 0-3544 0-3545 0-3546 0-3547 0-3548 0-3549 0-3550 0-3551 0-3577 0-3578 0-3579 0-3580 0-3581 0-3582 0-3583 0-3584 0-3585 0-3586 0-3587 0-3588 0-3589 0-3590 0-3599 1-2238 1-2247 1-2258 1-2279 1-2290 1-2300 1-2310 1-2492 1-2496 1-2499 1-3071 1-3073 1-3097 1-3099 1-3256 1-3266 1-3270 1-3273 1-3698 SCR0 000B 0-1005 0-1046 0-1047 0-1084 0-1087 0-1117 0-1118 0-1130 0-1159 0-1187 0-1198 0-1226 0-1227 0-1228 0-1229 0-1233 0-1234 0-1240 0-1241 0-1312 0-1320 0-1330 0-1332 0-1333 0-1336 0-1337 0-1339 0-1350 0-1366 0-1374 0-1375 0-1376 0-1377 0-1386 0-1422 0-1424 0-1426 0-1428 0-1497 0-1498 0-1502 0-1503 0-1521 0-1537 0-1538 0-1546 0-1578 0-1608 0-1649 0-1653 0-1654 0-1655 0-1660 0-1665 0-1666 0-1682 0-1729 0-1756 0-1787 0-1819 0-1860 0-1862 0-1864 0-1866 0-1868 0-1915 0-1925 0-2085 0-2092 0-2121 0-2126 0-2130 0-2135 0-2137 0-2138 0-2156 0-2157 0-2158 0-2159 0-2161 0-2166 0-2169 0-2272 0-2280 0-2335 0-2453 0-2459 0-2460 0-2462 0-2464 0-2465 0-2466 0-2525 0-2530 0-2531 0-2534 0-2535 0-2546 0-2567 0-2568 0-2601 0-2650 0-2651 0-2658 0-2659 0-2660 0-2661 0-2671 0-2672 0-2674 0-2676 0-2678 0-2683 0-2684 0-2707 0-2708 0-2716 0-2718 0-2720 0-2722 0-2724 0-2725 0-2730 0-2740 0-2741 0-2751 0-2795 0-2796 0-2799 0-2801 0-2805 0-2807 0-2945 0-2955 0-2957 0-2959 0-2961 0-2963 0-2965 0-2967 0-2969 0-2973 0-2974 0-2975 0-2976 0-2979 0-3003 0-3011 0-3018 0-3026 0-3032 0-3035 0-3667 0-3677 0-3680 1- 129 1- 133 1- 176 1- 178 1- 180 1- 182 1- 184 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 430 1- 431 1- 432 1- 433 1- 434 1- 435 1- 436 1- 437 1- 438 1- 439 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 226 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1- 440 1- 441 1- 442 1- 443 1- 444 1- 445 1- 462 1- 470 1- 478 1- 486 1- 496 1- 504 1- 512 1- 520 1- 568 1- 576 1- 641 1- 659 1- 686 1- 687 1- 689 1- 690 1- 695 1- 696 1- 698 1- 699 1- 705 1- 714 1- 761 1- 934 1- 943 1- 944 1- 945 1- 987 1-2212 1-2213 1-2214 1-2215 1-2219 1-2223 1-2239 1-2240 1-2248 1-2249 1-2259 1-2260 1-2280 1-2281 1-2291 1-2292 1-2301 1-2302 1-2311 1-2313 1-2334 1-2339 1-2359 1-2439 1-2488 1-2490 1-2506 1-2524 1-2593 1-2644 1-2875 1-2918 1-2927 1-2950 1-2983 1-2984 1-3156 1-3174 1-3175 1-3195 1-3320 1-3358 1-3430 1-3452 1-3485 1-3514 1-3554 1-3585 1-3734 0-3724 SCR1 000B 0-1053 0-1054 0-1177 0-1182 0-1258 0-1263 0-1268 0-1273 0-1284 0-1289 0-1294 0-1676 0-1687 0-1691 0-1841 0-1842 0-1871 0-1872 0-1874 0-1882 0-1883 0-1887 0-2034 0-2229 0-2230 0-2237 0-2242 0-2251 0-2299 0-2316 0-2318 0-3004 0-3012 0-3019 0-3027 0-3034 1- 571 1- 572 1- 579 1- 580 1- 642 1- 650 1- 656 1- 766 1- 989 1-1101 1-1345 1-1354 1-1355 1-1478 1-1484 1-1486 1-1619 1-1628 1-1629 1-1773 1-1780 1-1782 1-2002 1-2017 1-2018 1-2047 1-2059 1-2061 1-2088 1-2094 1-2096 1-2103 1-2109 1-2111 1-2136 1-2138 1-2154 1-2156 1-2181 1-2220 1-2335 1-2338 1-2512 1-2878 1-2886 1-2888 1-3164 1-3173 1-3206 1-3210 1-3245 1-3308 1-3314 1-3335 1-3338 1-3339 1-3340 1-3350 1-3351 1-3701 SCR10 000B 0-2871 0-2885 0-2886 0-2890 0-2892 0-2902 0-2908 0-2916 0-2920 0-2982 1- 841 1-1019 1-1380 1-1381 1-1382 1-1383 1-1384 1-1385 1-1386 1-1387 1-1388 1-1389 1-1390 1-1391 1-1392 1-1393 1-1394 1-1395 1-1401 1-1402 1-1403 1-1404 1-1405 1-1406 1-1407 1-1408 1-1409 1-1410 1-1411 1-1412 1-1413 1-1414 1-1415 1-1416 1-1422 1-1423 1-1424 1-1425 1-1426 1-1427 1-1428 1-1429 1-1430 1-1431 1-1432 1-1433 1-1434 1-1435 1-1436 1-1437 1-1443 1-1444 1-1445 1-1446 1-1447 1-1448 1-1449 1-1450 1-1451 1-1452 1-1453 1-1454 1-1455 1-1456 1-1457 1-1458 1-1518 1-1519 1-1520 1-1521 1-1522 1-1523 1-1524 1-1525 1-1526 1-1527 1-1528 1-1529 1-1530 1-1531 1-1532 1-1533 1-1539 1-1540 1-1541 1-1542 1-1543 1-1544 1-1545 1-1546 1-1547 1-1548 1-1549 1-1550 1-1551 1-1552 1-1553 1-1554 1-1560 1-1561 1-1562 1-1563 1-1564 1-1565 1-1566 1-1567 1-1568 1-1569 1-1570 1-1571 1-1572 1-1573 1-1574 1-1575 1-1581 1-1582 1-1583 1-1584 1-1585 1-1586 1-1587 1-1588 1-1589 1-1590 1-1591 1-1592 1-1593 1-1594 1-1595 1-1596 1-1654 1-1655 1-1656 1-1657 1-1658 1-1659 1-1660 1-1661 1-1662 1-1663 1-1664 1-1665 1-1666 1-1667 1-1668 1-1669 1-1675 1-1676 1-1677 1-1678 1-1679 1-1680 1-1681 1-1682 1-1683 1-1684 1-1685 1-1686 1-1687 1-1688 1-1689 1-1690 1-1696 1-1697 1-1698 1-1699 1-1700 1-1701 1-1702 1-1703 1-1704 1-1705 1-1706 1-1707 1-1708 1-1709 1-1710 1-1711 1-1717 1-1718 1-1719 1-1720 1-1721 1-1722 1-1723 1-1724 1-1725 1-1726 1-1727 1-1728 1-1729 1-1730 1-1731 1-1732 1-1814 1-1815 1-1816 1-1817 1-1818 1-1819 1-1820 1-1821 1-1822 1-1823 1-1824 1-1825 1-1826 1-1827 1-1828 1-1829 1-1835 1-1836 1-1837 1-1838 1-1839 1-1840 1-1841 1-1842 1-1843 1-1844 1-1845 1-1846 1-1847 1-1848 1-1849 1-1850 1-1856 1-1857 1-1858 1-1859 1-1860 1-1861 1-1862 1-1863 1-1864 1-1865 1-1866 1-1867 1-1868 1-1869 1-1870 1-1871 1-1877 1-1878 1-1879 1-1880 1-1881 1-1882 1-1883 1-1884 1-1885 1-1886 1-1887 1-1888 1-1889 1-1890 1-1891 1-1892 1-1932 1-1933 1-1983 1-1984 1-2003 1-2048 1-2089 1-2104 1-2131 1-2149 1-2568 1-2578 1-2588 1-2603 1-2619 1-2629 1-2639 1-2654 1-3440 1-3499 1-3568 1-3747 SCR11 000B 0-3558 0-3605 1- 846 1-1021 1-2569 1-2579 1-2589 1-2601 1-2604 1-2605 1-2620 1-2630 1-2640 1-2652 1-2655 1-2656 1-3437 1-3458 1-3494 1-3522 1-3563 1-3593 1-3742 SCR12 000B 1- 851 1-1023 1-2567 1-2574 1-2575 1-2577 1-2582 1-2583 1-2584 1-2596 1-2600 1-2618 1-2625 1-2626 1-2628 1-2633 1-2634 1-2635 1-2647 1-2651 1-3438 1-3459 1-3495 1-3523 1-3564 1-3594 1-3743 SCR13 000B 1- 856 1-1025 1-2580 1-2631 1-3496 1-3524 1-3565 1-3595 1-3744 SCR14 000B 1- 861 1-1027 1-3497 1-3525 1-3566 1-3596 1-3745 SCR15 000B 1- 866 1-1029 1-3427 1-3482 1-3551 1-3607 1-3614 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 227 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table SCR16 000B 1- 871 1-1031 SCR17 000B 1- 876 1-1033 SCR18 000B 1- 881 1-1035 SCR19 000B 1- 886 1-1037 SCR1A 000B 1- 891 1-1039 SCR1B 000B 1- 896 1-1041 SCR1C 000B 1- 901 1-1043 SCR1D 000B 1- 906 1-1045 SCR1E 000B 1- 911 1-1047 SCR1F 000B 0-1016 1- 916 1-1049 SCR2 000B 0-1057 0-1058 0-1347 0-1349 0-1888 0-2035 0-2190 0-2195 0-2301 0-2313 0-2314 0-2317 0-2319 0-2356 0-2358 0-2359 0-2380 0-2383 0-2384 0-2387 0-2388 0-2392 0-2627 0-2630 0-2631 0-2635 0-2802 0-2808 0-3005 0-3013 0-3020 0-3028 1- 649 1- 658 1- 771 1- 991 1-1147 1-1926 1-1930 1-1931 1-1979 1-1981 1-2518 1-2883 1-3094 1-3102 1-3158 1-3159 1-3202 1-3246 1-3260 1-3602 1-3693 1-3725 SCR3 000B 0-1069 0-1070 0-1071 0-1222 0-1323 0-1369 0-1399 0-1472 0-1473 0-1694 0-1722 0-1741 0-1749 0-1768 0-1776 0-1779 0-1799 0-1807 0-1811 0-1898 0-1901 0-1902 0-2009 0-2079 0-2082 0-2100 0-2104 0-2139 0-2140 0-2174 0-2176 0-2192 0-2200 0-2281 0-2284 0-2298 0-2306 0-3006 0-3014 0-3021 0-3029 1- 776 1- 993 1-1130 1-1150 1-1346 1-1347 1-1348 1-1351 1-1352 1-1359 1-1360 1-1361 1-1362 1-1363 1-1364 1-1365 1-1366 1-1367 1-1368 1-1369 1-1370 1-1371 1-1372 1-1373 1-1374 1-1468 1-1470 1-1472 1-1474 1-1476 1-1477 1-1479 1-1480 1-1483 1-1488 1-1491 1-1492 1-1497 1-1498 1-1499 1-1500 1-1501 1-1502 1-1503 1-1504 1-1505 1-1506 1-1507 1-1508 1-1509 1-1510 1-1511 1-1512 1-1618 1-1620 1-1621 1-1625 1-1626 1-1633 1-1634 1-1635 1-1636 1-1637 1-1638 1-1639 1-1640 1-1641 1-1642 1-1643 1-1644 1-1645 1-1646 1-1647 1-1648 1-1763 1-1765 1-1767 1-1769 1-1771 1-1772 1-1774 1-1775 1-1779 1-1784 1-1787 1-1788 1-1793 1-1794 1-1795 1-1796 1-1797 1-1798 1-1799 1-1800 1-1801 1-1802 1-1803 1-1804 1-1805 1-1806 1-1807 1-1808 1-2001 1-2006 1-2014 1-2015 1-2036 1-2038 1-2040 1-2042 1-2044 1-2045 1-2046 1-2051 1-2058 1-2063 1-2070 1-2087 1-2090 1-2093 1-2097 1-2102 1-2105 1-2108 1-2112 1-2129 1-2132 1-2135 1-2139 1-2147 1-2150 1-2153 1-2157 1-2171 1-2173 1-2175 1-2177 1-2179 1-2180 1-2182 1-2183 1-2946 1-2947 SCR4 000B 0-1100 0-1125 0-1126 0-1316 0-1322 0-1535 0-2036 0-2189 0-2191 0-2297 0-2300 1- 781 1- 995 1-1069 1-1070 1-1075 1-1097 1-1098 1-1129 1-1135 1-1149 1-1155 1-1168 1-1179 1-1273 1-1278 1-1299 1-2508 1-2958 1-3257 1-3264 1-3279 SCR5 000B 0-1101 0-1987 0-1991 0-2049 0-2184 0-2292 1- 786 1- 997 1-1216 1-1220 1-1234 1-1238 1-1251 1-1255 1-1268 1-1272 1-1300 1-2510 1-2960 1-3281 SCR6 000B 0-1162 0-1163 0-1166 0-1174 0-1178 0-1181 0-1201 0-1202 0-2213 0-2363 0-2364 0-2414 0-2726 1- 791 1- 999 1-2514 1-2962 1-3283 SCR7 000B 0-1133 0-2127 0-2206 0-2249 0-2909 0-2912 0-2918 1- 796 1-1001 1-2516 1-2964 1-3285 1-3337 SCR8 000B 0-1088 0-1299 0-1300 0-1612 0-1614 0-2047 0-2048 0-2089 0-2107 0-2348 0-2349 0-2587 0-2590 0-2591 0-2605 0-2607 0-2696 0-2735 0-2748 0-2760 0-2767 0-2861 0-2862 0-2863 0-2934 0-3088 0-3090 0-3093 0-3098 0-3188 0-3193 0-3252 0-3254 0-3452 0-3486 0-3487 1- 801 1-1003 1-3119 1-3135 1-3142 1-3291 SCR9 000B 0-1585 0-1586 0-2311 0-2330 0-2331 0-2338 0-2343 0-2344 0-2345 0-3664 1- 806 1-1005 1-3122 1-3293 SCRA 000B 0-1167 1- 811 1-1007 1-3072 1-3074 1-3075 1-3098 1-3287 SCRB 000B 0-1158 0-2077 0-2864 0-2953 0-2992 1- 816 1-1009 SCRC 000B 0-3103 0-3105 0-3107 0-3109 0-3111 0-3115 0-3116 0-3198 0-3200 0-3202 0-3204 0-3206 0-3207 0-3210 0-3211 0-3256 0-3457 0-3458 0-3460 0-3462 0-3464 0-3469 0-3470 0-3575 0-3576 0-3597 0-3602 0-3608 0-3613 0-3617 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 228 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-3619 0-3620 0-3633 1- 821 1-1011 SCRD 000B 0-1137 0-2046 0-2896 0-2905 0-2933 1- 826 1-1013 SCRE 000B 0-2860 0-2936 0-2938 0-2944 1- 831 1-1015 SCRF 000B 0-1140 0-2011 0-2045 1- 836 1-1017 1-2361 1-2529 1-2892 1-2893 1-2990 1-2991 XLIT 000C 1- 394 1- 395 1- 396 1- 397 1- 398 1- 399 1- 400 1- 401 1- 402 1- 403 1- 404 1- 405 1- 406 1- 407 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 229 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table ADD 0003 0-1054 0-1058 0-1070 0-1087 0-1100 0-1125 0-1126 0-1174 0-1181 0-1258 0-1263 0-1268 0-1273 0-1284 0-1289 0-1294 0-1316 0-1322 0-1330 0-1332 0-1333 0-1336 0-1337 0-1339 0-1367 0-1386 0-1499 0-1503 0-1521 0-1537 0-1606 0-1649 0-1650 0-1653 0-1654 0-1666 0-1725 0-1743 0-1752 0-1770 0-1778 0-1783 0-1802 0-1810 0-1814 0-1815 0-1830 0-1831 0-1841 0-1842 0-1868 0-1871 0-1872 0-1883 0-1890 0-1901 0-1902 0-2036 0-2045 0-2046 0-2077 0-2084 0-2106 0-2156 0-2157 0-2158 0-2159 0-2189 0-2191 0-2229 0-2230 0-2237 0-2242 0-2297 0-2300 0-2335 0-2427 0-2428 0-2456 0-2460 0-2527 0-2531 0-2535 0-2568 0-2601 0-2641 0-2655 0-2659 0-2708 0-2730 0-2740 0-2751 0-2761 0-2763 0-2768 0-2770 0-2864 0-2868 0-2885 0-2886 0-2933 0-2936 0-2979 0-3078 0-3081 0-3082 0-3150 0-3152 0-3172 0-3174 0-3207 0-3210 0-3256 0-3270 0-3272 0-3276 0-3278 0-3314 0-3328 0-3329 0-3385 0-3388 0-3424 0-3427 0-3444 0-3445 0-3479 0-3480 0-3575 0-3602 0-3608 0-3617 0-3618 0-3632 0-3677 1- 176 1- 178 1- 180 1- 182 1- 430 1- 431 1- 432 1- 433 1- 434 1- 435 1- 436 1- 437 1- 438 1- 439 1- 440 1- 441 1- 442 1- 443 1- 444 1- 445 1- 571 1- 579 1- 649 1- 650 1- 690 1- 699 1- 708 1- 717 1- 934 1- 944 1-1069 1-1070 1-1075 1-1097 1-1098 1-1101 1-1129 1-1135 1-1139 1-1148 1-1149 1-1155 1-1158 1-1220 1-1238 1-1255 1-1272 1-1278 1-1351 1-1352 1-1354 1-1483 1-1484 1-1491 1-1492 1-1625 1-1626 1-1628 1-1779 1-1780 1-1787 1-1788 1-1932 1-1979 1-1983 1-2014 1-2015 1-2017 1-2058 1-2059 1-2070 1-2093 1-2094 1-2097 1-2108 1-2109 1-2112 1-2135 1-2136 1-2139 1-2153 1-2154 1-2157 1-2219 1-2220 1-2334 1-2338 1-2524 1-2529 1-2574 1-2575 1-2580 1-2596 1-2601 1-2603 1-2604 1-2625 1-2626 1-2631 1-2647 1-2652 1-2654 1-2655 1-2886 1-2892 1-2920 1-2931 1-2966 1-2967 1-2968 1-2969 1-2973 1-2990 1-3158 1-3206 1-3323 1-3337 1-3338 1-3361 1-3437 1-3438 1-3439 1-3458 1-3459 1-3494 1-3495 1-3496 1-3497 1-3498 1-3522 1-3523 1-3524 1-3525 1-3526 1-3563 1-3564 1-3565 1-3566 1-3567 1-3593 1-3594 1-3595 1-3596 1-3597 1-3742 1-3743 1-3744 1-3745 1-3746 AND 0006 0-1005 0-1071 0-1084 0-1121 0-1162 0-1163 0-1171 0-1178 0-1187 0-1198 0-1202 0-1226 0-1227 0-1228 0-1229 0-1233 0-1234 0-1240 0-1241 0-1312 0-1314 0-1350 0-1358 0-1373 0-1375 0-1377 0-1384 0-1385 0-1391 0-1392 0-1395 0-1413 0-1433 0-1443 0-1447 0-1453 0-1464 0-1467 0-1477 0-1478 0-1479 0-1480 0-1481 0-1483 0-1490 0-1492 0-1502 0-1507 0-1512 0-1520 0-1538 0-1546 0-1574 0-1578 0-1581 0-1599 0-1602 0-1608 0-1641 0-1645 0-1646 0-1685 0-1839 0-1847 0-1870 0-1900 0-1907 0-1925 0-1934 0-1976 0-1978 0-1979 0-1983 0-1986 0-1987 0-1991 0-2017 0-2019 0-2047 0-2119 0-2136 0-2137 0-2164 0-2165 0-2174 0-2177 0-2213 0-2249 0-2260 0-2262 0-2279 0-2281 0-2285 0-2312 0-2313 0-2314 0-2315 0-2319 0-2363 0-2383 0-2384 0-2398 0-2412 0-2414 0-2415 0-2419 0-2459 0-2462 0-2467 0-2524 0-2530 0-2533 0-2536 0-2540 0-2566 0-2569 0-2572 0-2592 0-2614 0-2627 0-2638 0-2640 0-2647 0-2650 0-2658 0-2663 0-2680 0-2709 0-2726 0-2729 0-2739 0-2741 0-2744 0-2745 0-2756 0-2757 0-2791 0-2792 0-2799 0-2801 0-2805 0-2807 0-2871 0-2881 0-2882 0-2895 0-2896 0-2899 0-2905 0-2906 0-2921 0-2953 0-2954 0-2956 0-2958 0-2960 0-2973 0-2982 0-3031 0-3033 0-3084 0-3112 0-3169 0-3171 0-3209 0-3211 0-3247 0-3248 0-3265 0-3266 0-3326 0-3389 0-3428 0-3432 0-3466 0-3476 0-3558 0-3576 0-3597 0-3605 1- 133 1- 184 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 406 1- 406 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 230 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 641 1- 657 1- 689 1- 698 1- 707 1- 716 1-1216 1-1234 1-1251 1-1268 1-1273 1-1346 1-1348 1-1355 1-1468 1-1477 1-1480 1-1486 1-1488 1-1618 1-1621 1-1629 1-1763 1-1772 1-1775 1-1782 1-1784 1-1981 1-2001 1-2006 1-2018 1-2036 1-2045 1-2046 1-2051 1-2061 1-2063 1-2087 1-2090 1-2096 1-2102 1-2105 1-2111 1-2129 1-2132 1-2138 1-2147 1-2150 1-2156 1-2183 1-2212 1-2213 1-2222 1-2239 1-2248 1-2259 1-2280 1-2291 1-2301 1-2311 1-2333 1-2366 1-2367 1-2368 1-2369 1-2370 1-2371 1-2372 1-2373 1-2408 1-2465 1-2480 1-2482 1-2490 1-2583 1-2605 1-2634 1-2883 1-2932 1-2945 1-2946 1-2983 1-2985 1-3074 1-3075 1-3084 1-3090 1-3174 1-3202 1-3257 1-3264 1-3289 1-3306 1-3324 1-3332 1-3333 1-3340 1-3362 1-3412 1-3463 1-3527 1-3531 1-3598 1-3602 1-3607 1-3693 IOR 0005 0-1102 0-1106 0-1110 0-1118 0-1130 0-1132 0-1133 0-1137 0-1159 0-1166 0-1201 0-1317 0-1320 0-1359 0-1368 0-1388 0-1408 0-1409 0-1412 0-1432 0-1436 0-1437 0-1442 0-1446 0-1450 0-1451 0-1455 0-1469 0-1470 0-1484 0-1493 0-1504 0-1508 0-1554 0-1572 0-1584 0-1585 0-1612 0-1651 0-1655 0-1676 0-1678 0-1682 0-1684 0-1687 0-1688 0-1693 0-1722 0-1724 0-1729 0-1741 0-1749 0-1751 0-1756 0-1768 0-1776 0-1779 0-1782 0-1787 0-1799 0-1807 0-1811 0-1819 0-1832 0-1846 0-1850 0-1851 0-1855 0-1856 0-1874 0-1906 0-1910 0-1911 0-1915 0-1918 0-1928 0-1943 0-1982 0-1994 0-2004 0-2007 0-2021 0-2079 0-2082 0-2089 0-2104 0-2121 0-2123 0-2127 0-2133 0-2139 0-2161 0-2166 0-2176 0-2181 0-2206 0-2238 0-2272 0-2284 0-2289 0-2311 0-2317 0-2340 0-2343 0-2348 0-2356 0-2358 0-2364 0-2379 0-2380 0-2388 0-2391 0-2397 0-2453 0-2498 0-2525 0-2586 0-2587 0-2626 0-2631 0-2634 0-2651 0-2734 0-2749 0-2795 0-2796 0-2861 0-2890 0-2892 0-2902 0-2908 0-2909 0-2934 0-2955 0-2957 0-2961 0-2975 0-2992 0-3035 0-3087 0-3088 0-3091 0-3094 0-3098 0-3099 0-3187 0-3188 0-3193 0-3194 0-3252 0-3255 0-3431 0-3448 0-3452 0-3453 0-3484 0-3486 0-3502 0-3560 0-3600 0-3607 0-3613 0-3619 1- 129 1- 394 1- 394 1- 394 1- 395 1- 395 1- 395 1- 396 1- 396 1- 396 1- 397 1- 397 1- 397 1- 398 1- 398 1- 398 1- 399 1- 399 1- 399 1- 400 1- 400 1- 400 1- 401 1- 401 1- 401 1- 402 1- 402 1- 402 1- 403 1- 403 1- 403 1- 404 1- 404 1- 404 1- 405 1- 405 1- 405 1- 406 1- 406 1- 406 1- 407 1- 407 1- 407 1- 462 1- 470 1- 478 1- 486 1- 496 1- 504 1- 512 1- 520 1-2214 1-2223 1-2407 1-2467 1-2488 1-2512 1-2593 1-2644 1-2656 1-3022 1-3026 1-3030 1-3034 1-3037 1-3039 1-3041 1-3043 1-3046 1-3047 1-3048 1-3049 1-3050 1-3052 1-3054 1-3056 1-3072 1-3098 1-3173 1-3175 1-3245 1-3246 1-3285 1-3314 1-3316 1-3339 1-3350 1-3351 1-3354 1-3678 1-3710 1-3725 NOP 1000 ONES 0007 0-1014 0-2666 0-2712 1- 132 1- 148 1- 152 1- 156 1- 160 1-2874 OR 0005 RSUB 0001 0-1128 0-1898 0-2464 0-2534 0-2567 0-2660 0-2707 1-1168 1-2929 1-3131 SUB 0002 0-1117 0-1167 0-1177 0-1665 0-1882 0-2251 1-1179 XOR 0004 0-1259 0-1269 0-1304 0-1366 0-1498 0-1535 0-1557 0-2195 0-2330 0-2338 0-2344 0-2359 0-2546 0-2590 0-2605 0-2667 0-2696 0-2713 0-2735 0-2748 0-2760 0-2767 0-2863 0-2900 0-3127 0-3128 0-3129 0-3130 0-3158 0-3161 0-3349 0-3350 0-3351 0-3352 0-3382 1- 137 1- 394 1- 394 1- 394 1- 394 1- 394 1- 395 1- 395 1- 395 1- 395 1- 395 1- 396 1- 396 1- 396 1- 396 1- 396 1- 397 1- 397 1- 397 1- 397 1- 397 1- 398 1- 398 1- 398 1- 398 1- 398 1- 399 1- 399 1- 399 1- 399 1- 399 1- 400 1- 400 1- 400 1- 400 1- 400 1- 401 1- 401 1- 401 1- 401 1- 401 1- 402 1- 402 1- 402 1- 402 1- 402 1- 403 1- 403 1- 403 1- 403 1- 403 1- 404 1- 404 1- 404 1- 404 1- 404 1- 405 1- 405 1- 405 1- 405 1- 405 1- 406 1- 406 1- 406 1- 406 1- 406 1- 407 1- 407 1- 407 1- 407 1- 407 1- 568 1- 576 1- 642 1- 659 1- 687 1- 696 1- 705 1- 714 1- 761 1- 766 1- 771 1- 776 1- 781 1- 786 1- 791 1- 796 1- 801 1- 806 1- 811 1- 816 1- 821 1- 826 1- 831 1- 836 1- 841 1- 846 1- 851 1- 856 1- 861 1- 866 1- 871 1- 876 1- 881 1- 886 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 231 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1- 891 1- 896 1- 901 1- 906 1- 911 1- 916 1- 942 1- 945 1- 987 1- 989 1- 991 1- 993 1- 995 1- 997 1- 999 1-1001 1-1003 1-1005 1-1007 1-1009 1-1011 1-1013 1-1015 1-1017 1-1019 1-1021 1-1023 1-1025 1-1027 1-1029 1-1031 1-1033 1-1035 1-1037 1-1039 1-1041 1-1043 1-1045 1-1047 1-1049 1-1130 1-1150 1-1654 1-1655 1-1656 1-1657 1-1658 1-1659 1-1660 1-1661 1-1662 1-1663 1-1664 1-1665 1-1666 1-1667 1-1668 1-1669 1-1675 1-1676 1-1677 1-1678 1-1679 1-1680 1-1681 1-1682 1-1683 1-1684 1-1685 1-1686 1-1687 1-1688 1-1689 1-1690 1-1696 1-1697 1-1698 1-1699 1-1700 1-1701 1-1702 1-1703 1-1704 1-1705 1-1706 1-1707 1-1708 1-1709 1-1710 1-1711 1-1717 1-1718 1-1719 1-1720 1-1721 1-1722 1-1723 1-1724 1-1725 1-1726 1-1727 1-1728 1-1729 1-1730 1-1731 1-1732 1-1814 1-1815 1-1816 1-1817 1-1818 1-1819 1-1820 1-1821 1-1822 1-1823 1-1824 1-1825 1-1826 1-1827 1-1828 1-1829 1-1835 1-1836 1-1837 1-1838 1-1839 1-1840 1-1841 1-1842 1-1843 1-1844 1-1845 1-1846 1-1847 1-1848 1-1849 1-1850 1-1856 1-1857 1-1858 1-1859 1-1860 1-1861 1-1862 1-1863 1-1864 1-1865 1-1866 1-1867 1-1868 1-1869 1-1870 1-1871 1-1877 1-1878 1-1879 1-1880 1-1881 1-1882 1-1883 1-1884 1-1885 1-1886 1-1887 1-1888 1-1889 1-1890 1-1891 1-1892 1-1933 1-1984 1-2003 1-2048 1-2171 1-2180 1-2240 1-2249 1-2260 1-2281 1-2292 1-2302 1-2313 1-2335 1-2394 1-2420 1-2454 1-2473 1-2506 1-2508 1-2510 1-2514 1-2516 1-2518 1-2525 1-2578 1-2579 1-2584 1-2629 1-2630 1-2635 1-2875 1-2918 1-2927 1-2950 1-2958 1-2960 1-2962 1-2964 1-2971 1-2975 1-2977 1-2984 1-2988 1-3021 1-3025 1-3029 1-3033 1-3038 1-3040 1-3042 1-3044 1-3051 1-3053 1-3055 1-3057 1-3094 1-3102 1-3119 1-3120 1-3122 1-3135 1-3142 1-3156 1-3195 1-3279 1-3281 1-3283 1-3287 1-3291 1-3293 1-3320 1-3358 1-3430 1-3440 1-3452 1-3485 1-3499 1-3514 1-3554 1-3568 1-3585 1-3614 1-3701 1-3734 1-3747 ZERO 0000 0-1011 0-1013 0-1017 0-1019 0-1020 0-1026 0-1027 0-1028 0-1029 0-1034 0-1035 0-1036 0-1040 0-1051 0-1073 0-1074 0-1075 0-1076 0-1078 0-1080 0-1081 0-1208 0-1482 0-1491 0-1550 0-1553 0-1858 0-1919 0-1966 0-2180 0-2194 0-2205 0-2258 0-2259 0-2269 0-2341 0-2353 0-2455 0-2463 0-2654 0-2662 0-3101 0-3196 0-3455 0-3488 0-3659 0-3660 0-3669 0-3670 0-3671 0-3672 0-3673 0-3674 0-3675 0-3676 1- 126 1- 128 1- 150 1- 153 1- 158 1- 161 1- 172 1- 456 1-2935 1-3069 0-3726 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 232 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table X 0001 0-1312 0-1320 0-1350 0-1368 0-1375 0-1377 0-1391 0-1469 0-1470 0-1478 0-1480 0-2007 0-2019 0-2119 0-2137 0-2906 0-2973 0-3031 1- 641 1- 657 1-1468 1-1477 1-1763 1-1772 1-2036 1-2045 1-2171 1-2183 1-2213 1-2222 1-3339 1-3350 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 233 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table LIT 0001 0-1005 0-1070 0-1071 0-1084 0-1087 0-1100 0-1118 0-1125 0-1126 0-1130 0-1133 0-1137 0-1159 0-1162 0-1163 0-1166 0-1174 0-1178 0-1181 0-1187 0-1198 0-1201 0-1202 0-1226 0-1227 0-1228 0-1229 0-1233 0-1234 0-1240 0-1241 0-1258 0-1263 0-1268 0-1273 0-1284 0-1289 0-1294 0-1312 0-1316 0-1320 0-1322 0-1330 0-1332 0-1333 0-1336 0-1337 0-1339 0-1350 0-1375 0-1377 0-1386 0-1502 0-1503 0-1521 0-1535 0-1538 0-1546 0-1578 0-1608 0-1655 0-1666 0-1676 0-1682 0-1687 0-1722 0-1729 0-1741 0-1749 0-1756 0-1768 0-1776 0-1779 0-1787 0-1799 0-1807 0-1811 0-1819 0-1868 0-1874 0-1883 0-1915 0-1925 0-1987 0-1991 0-2036 0-2045 0-2046 0-2047 0-2077 0-2079 0-2082 0-2089 0-2104 0-2121 0-2127 0-2137 0-2139 0-2161 0-2166 0-2174 0-2176 0-2189 0-2191 0-2195 0-2206 0-2213 0-2242 0-2249 0-2272 0-2281 0-2284 0-2297 0-2300 0-2313 0-2314 0-2317 0-2319 0-2335 0-2363 0-2364 0-2380 0-2383 0-2384 0-2388 0-2414 0-2453 0-2459 0-2460 0-2462 0-2525 0-2530 0-2531 0-2535 0-2568 0-2601 0-2627 0-2631 0-2650 0-2651 0-2658 0-2659 0-2708 0-2726 0-2730 0-2741 0-2751 0-2795 0-2796 0-2799 0-2801 0-2805 0-2807 0-2861 0-2863 0-2864 0-2871 0-2885 0-2886 0-2890 0-2892 0-2896 0-2902 0-2905 0-2908 0-2909 0-2933 0-2934 0-2936 0-2953 0-2973 0-2975 0-2979 0-2982 0-2992 0-3207 0-3211 0-3256 0-3558 0-3575 0-3576 0-3597 0-3602 0-3605 0-3608 0-3613 0-3617 0-3619 0-3677 1- 129 1- 133 1- 176 1- 178 1- 180 1- 182 1- 184 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 462 1- 470 1- 478 1- 486 1- 496 1- 504 1- 512 1- 520 1- 571 1- 579 1- 581 1- 641 1- 649 1- 650 1- 689 1- 690 1- 698 1- 699 1- 945 1-1075 1-1148 1-1216 1-1220 1-1234 1-1238 1-1251 1-1255 1-1268 1-1272 1-1273 1-1278 1-1346 1-1348 1-1351 1-1352 1-1354 1-1355 1-1468 1-1477 1-1480 1-1483 1-1484 1-1486 1-1488 1-1491 1-1492 1-1618 1-1621 1-1625 1-1626 1-1628 1-1629 1-1763 1-1772 1-1775 1-1779 1-1780 1-1782 1-1784 1-1787 1-1788 1-1932 1-1933 1-1979 1-1981 1-1983 1-1984 1-2001 1-2006 1-2014 1-2015 1-2017 1-2018 1-2036 1-2045 1-2046 1-2051 1-2058 1-2059 1-2061 1-2063 1-2070 1-2087 1-2090 1-2093 1-2094 1-2096 1-2097 1-2102 1-2105 1-2108 1-2109 1-2111 1-2112 1-2129 1-2132 1-2135 1-2136 1-2138 1-2139 1-2147 1-2150 1-2153 1-2154 1-2156 1-2157 1-2171 1-2180 1-2183 1-2212 1-2213 1-2220 1-2239 1-2248 1-2259 1-2280 1-2291 1-2301 1-2311 1-2334 1-2338 1-2490 1-2512 1-2529 1-2574 1-2575 1-2578 1-2579 1-2580 1-2583 1-2584 1-2593 1-2596 1-2604 1-2605 1-2625 1-2626 1-2629 1-2630 1-2631 1-2634 1-2635 1-2644 1-2647 1-2655 1-2656 1-2875 1-2883 1-2886 1-2892 1-2918 1-2927 1-2946 1-2950 1-2983 1-2990 1-3072 1-3074 1-3075 1-3094 1-3098 1-3102 1-3156 1-3158 1-3173 1-3174 1-3175 1-3195 1-3202 1-3206 1-3246 1-3257 1-3264 1-3285 1-3320 1-3337 1-3340 1-3350 1-3358 1-3430 1-3452 1-3485 1-3514 1-3554 1-3585 1-3602 1-3607 1-3614 1-3693 1-3725 1-3734 NOP 0001 RAM 0000 0-1054 0-1058 0-1102 0-1106 0-1110 0-1114 0-1117 0-1121 0-1128 0-1132 0-1167 0-1171 0-1175 0-1177 0-1186 0-1205 0-1221 0-1259 0-1269 0-1304 0-1314 0-1317 0-1321 0-1346 0-1348 0-1358 0-1359 0-1366 0-1367 0-1368 0-1373 0-1384 0-1385 0-1388 0-1391 0-1392 0-1395 0-1406 0-1408 0-1409 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 234 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 0-1412 0-1413 0-1415 0-1423 0-1427 0-1432 0-1433 0-1436 0-1437 0-1442 0-1443 0-1446 0-1447 0-1450 0-1451 0-1453 0-1455 0-1460 0-1462 0-1463 0-1464 0-1467 0-1469 0-1470 0-1477 0-1478 0-1479 0-1480 0-1481 0-1483 0-1484 0-1490 0-1492 0-1493 0-1498 0-1499 0-1504 0-1507 0-1508 0-1511 0-1512 0-1520 0-1536 0-1537 0-1542 0-1554 0-1557 0-1558 0-1572 0-1574 0-1581 0-1584 0-1585 0-1599 0-1602 0-1606 0-1612 0-1641 0-1645 0-1646 0-1649 0-1650 0-1651 0-1653 0-1654 0-1665 0-1678 0-1684 0-1685 0-1688 0-1690 0-1693 0-1724 0-1725 0-1743 0-1751 0-1752 0-1760 0-1770 0-1778 0-1782 0-1783 0-1791 0-1802 0-1810 0-1814 0-1815 0-1823 0-1826 0-1827 0-1829 0-1830 0-1831 0-1832 0-1839 0-1841 0-1842 0-1846 0-1847 0-1850 0-1851 0-1855 0-1856 0-1859 0-1861 0-1863 0-1865 0-1867 0-1870 0-1871 0-1872 0-1882 0-1885 0-1886 0-1889 0-1890 0-1897 0-1898 0-1900 0-1901 0-1902 0-1906 0-1907 0-1910 0-1911 0-1918 0-1928 0-1934 0-1943 0-1976 0-1978 0-1979 0-1982 0-1983 0-1986 0-1994 0-2004 0-2007 0-2017 0-2019 0-2021 0-2084 0-2099 0-2106 0-2119 0-2122 0-2123 0-2133 0-2136 0-2144 0-2145 0-2146 0-2147 0-2151 0-2152 0-2153 0-2154 0-2156 0-2157 0-2158 0-2159 0-2162 0-2163 0-2164 0-2165 0-2177 0-2181 0-2207 0-2208 0-2209 0-2210 0-2211 0-2212 0-2224 0-2226 0-2228 0-2229 0-2230 0-2232 0-2234 0-2236 0-2237 0-2238 0-2248 0-2251 0-2254 0-2255 0-2260 0-2261 0-2262 0-2275 0-2277 0-2278 0-2279 0-2285 0-2289 0-2311 0-2312 0-2315 0-2330 0-2338 0-2340 0-2343 0-2344 0-2348 0-2356 0-2358 0-2359 0-2379 0-2391 0-2397 0-2398 0-2412 0-2415 0-2419 0-2427 0-2428 0-2456 0-2464 0-2467 0-2498 0-2524 0-2527 0-2533 0-2534 0-2536 0-2540 0-2546 0-2566 0-2567 0-2569 0-2572 0-2586 0-2587 0-2590 0-2592 0-2605 0-2614 0-2626 0-2634 0-2638 0-2640 0-2641 0-2647 0-2655 0-2660 0-2663 0-2667 0-2670 0-2673 0-2675 0-2677 0-2679 0-2680 0-2696 0-2707 0-2709 0-2713 0-2715 0-2717 0-2719 0-2721 0-2723 0-2729 0-2734 0-2735 0-2739 0-2740 0-2744 0-2745 0-2748 0-2749 0-2756 0-2757 0-2760 0-2761 0-2763 0-2767 0-2768 0-2770 0-2791 0-2792 0-2800 0-2806 0-2868 0-2881 0-2882 0-2895 0-2899 0-2900 0-2906 0-2919 0-2921 0-2954 0-2955 0-2956 0-2957 0-2958 0-2960 0-2961 0-2962 0-2964 0-2966 0-2968 0-3031 0-3033 0-3035 0-3036 0-3038 0-3039 0-3040 0-3050 0-3051 0-3052 0-3053 0-3074 0-3076 0-3078 0-3081 0-3082 0-3084 0-3087 0-3088 0-3091 0-3094 0-3098 0-3099 0-3102 0-3104 0-3106 0-3108 0-3110 0-3112 0-3127 0-3128 0-3129 0-3130 0-3148 0-3150 0-3152 0-3158 0-3161 0-3169 0-3171 0-3172 0-3174 0-3187 0-3188 0-3193 0-3194 0-3197 0-3199 0-3201 0-3203 0-3205 0-3209 0-3210 0-3247 0-3248 0-3252 0-3255 0-3265 0-3266 0-3270 0-3272 0-3276 0-3278 0-3288 0-3289 0-3290 0-3291 0-3310 0-3312 0-3314 0-3326 0-3328 0-3329 0-3349 0-3350 0-3351 0-3352 0-3371 0-3382 0-3385 0-3388 0-3389 0-3401 0-3402 0-3403 0-3404 0-3422 0-3423 0-3424 0-3427 0-3428 0-3431 0-3432 0-3444 0-3445 0-3448 0-3452 0-3453 0-3456 0-3459 0-3461 0-3463 0-3465 0-3466 0-3476 0-3479 0-3480 0-3484 0-3486 0-3491 0-3502 0-3560 0-3600 0-3607 0-3618 0-3632 1- 137 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 394 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 395 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 396 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 397 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 398 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 399 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 400 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 401 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 402 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 403 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 404 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 405 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 406 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 407 1- 430 1- 431 1- 432 1- 433 1- 434 1- 435 1- 436 1- 437 1- 438 1- 439 1- 440 1- 441 1- 442 1- 443 1- 444 1- 445 1- 568 1- 576 1- 642 1- 657 1- 659 1- 687 1- 696 1- 704 1- 705 1- 707 1- 708 1- 713 1- 714 1- 716 1- 717 1- 761 1- 766 1- 771 1- 776 1- 781 1- 786 1BTI PPU5 ASSEMBLER 18-Jul-91 17:49 Page 235 PPU/REV 26 microcode *** second half of prom *** File# 0 cross-reference table 1- 791 1- 796 1- 801 1- 806 1- 811 1- 816 1- 821 1- 826 1- 831 1- 836 1- 841 1- 846 1- 851 1- 856 1- 861 1- 866 1- 871 1- 876 1- 881 1- 886 1- 891 1- 896 1- 901 1- 906 1- 911 1- 916 1- 934 1- 942 1- 944 1- 953 1- 954 1- 955 1- 956 1- 957 1- 958 1- 959 1- 960 1- 961 1- 962 1- 963 1- 964 1- 965 1- 966 1- 967 1- 968 1- 969 1- 970 1- 971 1- 972 1- 973 1- 974 1- 975 1- 976 1- 977 1- 978 1- 979 1- 980 1- 981 1- 982 1- 983 1- 984 1- 987 1- 989 1- 991 1- 993 1- 995 1- 997 1- 999 1-1001 1-1003 1-1005 1-1007 1-1009 1-1011 1-1013 1-1015 1-1017 1-1019 1-1021 1-1023 1-1025 1-1027 1-1029 1-1031 1-1033 1-1035 1-1037 1-1039 1-1041 1-1043 1-1045 1-1047 1-1049 1-1069 1-1070 1-1097 1-1098 1-1101 1-1129 1-1130 1-1134 1-1135 1-1137 1-1139 1-1149 1-1150 1-1154 1-1155 1-1157 1-1158 1-1168 1-1179 1-1654 1-1655 1-1656 1-1657 1-1658 1-1659 1-1660 1-1661 1-1662 1-1663 1-1664 1-1665 1-1666 1-1667 1-1668 1-1669 1-1675 1-1676 1-1677 1-1678 1-1679 1-1680 1-1681 1-1682 1-1683 1-1684 1-1685 1-1686 1-1687 1-1688 1-1689 1-1690 1-1696 1-1697 1-1698 1-1699 1-1700 1-1701 1-1702 1-1703 1-1704 1-1705 1-1706 1-1707 1-1708 1-1709 1-1710 1-1711 1-1717 1-1718 1-1719 1-1720 1-1721 1-1722 1-1723 1-1724 1-1725 1-1726 1-1727 1-1728 1-1729 1-1730 1-1731 1-1732 1-1814 1-1815 1-1816 1-1817 1-1818 1-1819 1-1820 1-1821 1-1822 1-1823 1-1824 1-1825 1-1826 1-1827 1-1828 1-1829 1-1835 1-1836 1-1837 1-1838 1-1839 1-1840 1-1841 1-1842 1-1843 1-1844 1-1845 1-1846 1-1847 1-1848 1-1849 1-1850 1-1