1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 1 File# 0 1 nolist macros 2 nolist macinstr 4 set RevString,16 5 expand on 7 expand on 8 include Ucode.HrdSSU:SSU16.Text1 2 expand off 3 4 5 6 * ......... BBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 7 * ................. BBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 8 * ..........##......... BBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 9 * ............##........... BBBBBB BBBBBB TTTTTT TTTTTT TTTTTT IIIIII 10 * .............##............ BBBBBB BBBBBB TTTTT TTTTTT TTTTT IIIIII 11 * .............##............ BBBBBB BBBBBBB TTTT TTTTTT TTTT IIIIII 12 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 13 * ..............##............. BBBBBBBBBBBBBBBBB TTTTTT IIIIII 14 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 15 * .............##.............. BBBBBB BBBBBB TTTTTT IIIIII 16 * ...........##.............. BBBBBB BBBBBB TTTTTT IIIIII 17 * ..........##............... BBBBBB BBBBBB TTTTTT IIIIII 18 * ........##............... BBBBBB BBBBBBB TTTTTT IIIIII 19 * .....##.............. BBBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 20 * ................. BBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 21 * ......... BBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 22 * 23 * 24 * *** Copyright 1981, 1982, 1983, 1984, 1985, 1986, 1987, 1988, 25 * 1989, 1991, 1992 BTI Computer Systems *** 26 * 27 * This document and the program it describes are the exclusive property 28 * of and proprietary to BTI Computer Systems. No use, reproduction or 29 * disclosure of this document or its contents, either in full or in part, 30 * by any means whatsoever regardless of purpose may be made without the 31 * prior written consent of BTI Computer Systems. 32 * 33 * BTI Computer Systems 34 * Sunnyvale, California 94086 35 36 37 38 39 * SSSSS SSSSS UU UU CCCCC OOOOO DDDDDD EEEEEEE 40 * SSSSSSS SSSSSSS UU UU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 41 * SS SS SS SS UU UU UU UU CC OO OO DD DD EE 42 * SS SS UU UU UU UU CC OO OO DD DD EE 43 * SS SS UU UU UU UU CC OO OO DD DD EE 44 * SS SS UU UU UU UU CC OO OO DD DD EEEEEEE 45 * SSSSSS SSSSSS UU UU UU UU ---- CC OO OO DD DD EEEEEEE 46 * SSSSSS SSSSSS UU UU UUUUUUU CC OO OO DD DD EE 47 * SS SS UU UU UUUUUUU CC OO OO DD DD EE 48 * SS SS UU UU UU UU CC OO OO DD DD EE 49 * SS SS UU UU UU CC OO OO DD DD EE 50 * SS SS SS SS UU UU UU CC OO OO DD DD EE 51 * SSSSSSS SSSSSSS UUUUUUU UUUU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 52 * SSSSS SSSSS UUUUU UU CCCCC OOOOO DDDDDD EEEEEEE 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 2 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Logo 54 55 56 57 58 59 60 * ......... BBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 61 * ................. BBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 62 * ..........##......... BBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTTTTTTTTTTTTTT IIIIIIIIIIII 63 * ............##........... BBBBBB BBBBBB TTTTTT TTTTTT TTTTTT IIIIII 64 * .............##............ BBBBBB BBBBBB TTTTT TTTTTT TTTTT IIIIII 65 * .............##............ BBBBBB BBBBBBB TTTT TTTTTT TTTT IIIIII 66 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 67 * ..............##............. BBBBBBBBBBBBBBBBB TTTTTT IIIIII 68 * ..............##............. BBBBBBBBBBBBBBBBBBB TTTTTT IIIIII 69 * .............##.............. BBBBBB BBBBBB TTTTTT IIIIII 70 * ...........##.............. BBBBBB BBBBBB TTTTTT IIIIII 71 * ..........##............... BBBBBB BBBBBB TTTTTT IIIIII 72 * ........##............... BBBBBB BBBBBBB TTTTTT IIIIII 73 * .....##.............. BBBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 74 * ................. BBBBBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 75 * ......... BBBBBBBBBBBBBBBBBBBB TTTTTTTTTTTT IIIIIIIIIIII 76 * 77 * 78 * *** Copyright 1981, 1982, 1983, 1984, 1985, 1986, 1987, 1988, 79 * 1989, 1991, 1992 BTI Computer Systems *** 80 * 81 * This document and the program it describes are the exclusive property 82 * of and proprietary to BTI Computer Systems. No use, reproduction or 83 * disclosure of this document or its contents, either in full or in part, 84 * by any means whatsoever regardless of purpose may be made without the 85 * prior written consent of BTI Computer Systems. 86 * 87 * BTI Computer Systems 88 * Sunnyvale, California 94086 89 90 91 92 93 94 * SSSSS SSSSS UU UU CCCCC OOOOO DDDDDD EEEEEEE 95 * SSSSSSS SSSSSSS UU UU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 96 * SS SS SS SS UU UU UU UU CC OO OO DD DD EE 97 * SS SS UU UU UU UU CC OO OO DD DD EE 98 * SS SS UU UU UU UU CC OO OO DD DD EE 99 * SS SS UU UU UU UU CC OO OO DD DD EEEEEEE 100 * SSSSSS SSSSSS UU UU UU UU ---- CC OO OO DD DD EEEEEEE 101 * SSSSSS SSSSSS UU UU UUUUUUU CC OO OO DD DD EE 102 * SS SS UU UU UUUUUUU CC OO OO DD DD EE 103 * SS SS UU UU UU UU CC OO OO DD DD EE 104 * SS SS UU UU UU CC OO OO DD DD EE 105 * SS SS SS SS UU UU UU CC OO OO DD DD EE 106 * SSSSSSS SSSSSSS UUUUUUU UUUU CCCCCCC OOOOOOO DDDDDDD EEEEEEE 107 * SSSSS SSSSS UUUUU UU CCCCC OOOOO DDDDDD EEEEEEE 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 3 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Revision Log 110 111 **************************************************************************************************************** 112 * * 113 * LOG OF CHANGES * 114 * * 115 * Rev 1-4 -- Forgotten in the dark ages * 116 * * 117 * Rev 5 -- The first released version. Poorly structured, no RFP. * 118 * * 119 * Rev 6 -- Completely rewritten by Dunn and Libby. Includes encrypted RFP. * 120 * Not released. * 121 * * 122 * Rev 7 -- Fixed various bugs from Rev 6. First released version with * 123 * encrypted RFP. Reports microcode revision as Rev 6. * 124 * * 125 * Rev 8 -- Added code to display microcode halts on Control Panel. Increased * 126 * maximum number of processes. Changed RFP to report address * 127 * and data on Scan commands. * 128 * * 129 * Rev 9 -- Fixed bug that caused SSU to report incorrect error code in WRU 1. * 130 * * 131 * Rev 10 -- Fixed bugs in RFP causing hangups on noisy phone lines (increased * 132 * break time, modified timeouts, added delay before nack). * 133 * * 134 * Rev 11 -- Fixed bugs that kept Remote RFP access from working. * 135 * * 136 * Rev 12 ---- released January 1983 * 137 * * 138 * -- Fixed bug in ACPFW handling. * 139 * -- Added MB1, MB2 to WRU responses. * 140 * -- Shortened break time to 200ms. * 141 * -- Fixed bug that caused hot spare SSU to hang after an NVM write. * 142 * -- Fixed bugs in boot prom read and masked scan. * 143 * -- Changed RFP Send Nack routine to clear uart input data buffer. * 144 * * 145 * Rev 13 ---- released February 1985 * 146 * * 147 * -- New assembler fixed bug in DelayC macro that causes the * 148 * IO field to not always be assembled (used 2 places with * 149 * RNVM in the IO field). * 150 * -- The WRUs of a hot spare SSU were not properly initialized * 151 * -- The wait after MCLR is released was increased from .25 and .75 * 152 * seconds to 5 seconds. This allows CPU4 and SMU enough time * 153 * to do their self test and load their control store. * 154 * -- New Scan command implemented for the RFP * 155 * -- Break and Dwell implemented for Port 0 (send from OS to Port 0) * 156 * -- Add the code to maintain, when requested, the SSU clock in an * 157 * OS supplied physical memory location. * 158 * * 159 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 4 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Revision Log 161 162 **************************************************************************************************************** 163 * * 164 * Rev 14 ---- released December 1986 * 165 * * 166 * -- Fixed bug: bug kept operating system from turning on sonalert * 167 * with a store to 140C. * 168 * -- Fixed bug: CP.Scan.6 was checking physical address against * 169 * ending virtual address to determine ending condition. Now * 170 * it properly checks the current virtual address against the * 171 * ending virtual address to determine the end of the scan. * 172 * -- Fixed bug: in Ck.Add.Rel subroutine, the address would only be * 173 * relocated again if the 16 LS bits of the virtual address * 174 * rolled over from 0FFFF to 00000. This bug was fixed so * 175 * that only the LS 10 bits of the virtual address need to * 176 * roll over, since this is the page boundary of the CPU. * 177 * -- Fixed bug: near CP.Init the loop increment was 1 when it * 178 * should have been -1. This is the loop that is supposed * 179 * to zero ACC0, ACC1, and ACC2. * 180 * -- Fixed bug: the clock store function would not write the 12 * 181 * most significant bits of the clock to memory except when * 182 * PAUSE is clear and the least significant 32 bits count from * 183 * FFFFFFFF to 00000000. This bug has been fixed so the the * 184 * 12 most significant bits of the clock are also written * 185 * whenever PAUSE is released (cleared) or when the clock * 186 * store function is enabled. (The actual write occurs on * 187 * the millisecond tick when the least significant 32 bits * 188 * are updated.) * 189 * -- Fixed bug: If the clock store function detected a bus error, * 190 * it called the Bus.Error subroutine which calls Set.Alarm * 191 * which calls Timer.Wait. This is an error since the clock * 192 * store function runs at dispatcher level and Timer.Wait * 193 * must only be called by a process. This error would most * 194 * likely cause a "SSU HALT03" (formerly, "Timer in use when * 195 * Timer.Wait called") instead of causing the SSU to assert * 196 * bus error and put "ERRx SLOTn" in the display like it * 197 * should. This bug was fixed by bracketing the call to * 198 * Bus.Error with calls to CreateProc and DestroyProc so * 199 * that the call to Bus.Error runs as a process. * 200 * -- Added feature: if there is an address relocation error, the * 201 * command processor now returns the 24 least significant * 202 * bits of the address that caused the relocation error in * 203 * the first three bytes of the response. * 204 * -- Added feature: changed RETURNS.A and RETURNS.B macros so that * 205 * if a RETURNA or a RETURNB is called with a return index of * 206 * zero, then a SSU.HALT will be taken. This is a bug trap * 207 * to cause a SSU.HALT if the return index gets zeroed * 208 * accidentally by some kind of bug. Previously, a RETURNA * 209 * with the return index set to zero would erroneously drop * 210 * you back at address Wait (the start of the idle loop). * 211 * -- Added feature: added code in Timer.Wait to make sure * 212 * dispatcher level processes are not calling this subroutine * 213 * and if a dispatcher level process is the caller to do * 214 * a SSU.HALT. (Note that a side effect of this is that * 215 * most of the SSU.HALT numbers change.) * 216 * * 217 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 5 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Revision Log 219 220 **************************************************************************************************************** 221 * * 222 * -- New hardware: The 7055 non-volatile memory chips have been * 223 * discontinued by the manufacturer (Nitron), so the NVM * 224 * circuitry has been changed to use a 2816 electrically * 225 * erasable PROM (EEPROM). Major differences between the * 226 * EEPROM and NVM (from a microcode standpoint) are that * 227 * the EEPROM is 2K deep versus the NVM's 128 locations * 228 * so the EEPROM must use the page address register. The * 229 * EEPROM only requires one RNVM opcode versus the NVM's * 230 * need for 16 RNVM opcodes. The time after a WNVM * 231 * opcode before the EEPROM becomes ready again is only * 232 * 12 msec versus the NVM's 145 msec time. For circuit * 233 * and wiring differences, you should refer to the ECN * 234 * and schematic. The microcode no longer does a read of * 235 * the last NVM location when the NVM becomes ready * 236 * again. * 237 * -- Microcode cleanup: Added some CHECKSKIP and CHECKSKIP.IO * 238 * statements in front of some NZT instructions that * 239 * didn't have them. Also, made the DELAY and DELAYC * 240 * macros use the ALIGN and CHECKALIGN macros to get * 241 * everything onto the same page. Also made sure that * 242 * there are no nzt or xec transfers to labels outside * 243 * the aligned part by moving some labels to before the * 244 * CHECKALIGN statement. Also changed some 2 line and * 245 * instruction combinations like * 246 * " nop opcode RETURNB" into a single line and * 247 * instruction like " RETURNB opcode". * 248 * * 249 * * 250 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 6 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Revision Log 252 253 **************************************************************************************************************** 254 * * 255 * Rev 15 ---- released 17 May, 1989 * 256 * * 257 * -- Typos: fixed a few minor typos in some comments. * 258 * -- Changed labels: changed the periods in most non-macro * 259 * labels to underline characters so they will be more * 260 * compatible with the disassembler. If you try to type * 261 * a period into the disassembler, it thinks you want to * 262 * redisplay the current line. * 263 * -- Fixed bug: Changed Write_NVM routine so it resets the page * 264 * address back to Base_Page before setting NVM_Rdy_Mask * 265 * and clearing NVM_F_Ready instead of after. The bug in * 266 * rev 14 resulted in these two variables being * 267 * referenced in the wrong page of RAM which resulted in * 268 * the system never getting the NVM is ready interrupt * 269 * when writing to NVM addresses in pages 1,2,3,5,6, or * 270 * 7 (the interrupt works correctly if you write to page * 271 * 0 or 4 (bus addresses #18XX or #1CXX)). * 272 * -- Fixed bug: The following control panel messages have been * 273 * fixed so that they turn on the alarm light and beep * 274 * the sonar for 1 second: "CPUxERRnn", "NO MEMORY", * 275 * "HALTx ahhhh", "STPx ahhhh", "SSU ERRxx", "SSU * 276 * HALTxx". * 277 * -- Microcode cleanup: Combined calls to Display_Off and * 278 * Set_Alarm into a call to DispAlarm in BSE_Error routine. * 279 * -- Added feature: Changed SaveCPUHalt subroutine so that if * 280 * the error word sent to the SSU for a halt, stop, or * 281 * cpu error is all zeros, then the first byte will be * 282 * changed to FF to distinguish it from a no error entry * 283 * which is all zeros. * 284 * -- Added feature: The sonar and alarm light will now be turned * 285 * off whenever "FP RUNNING" is displayed. * 286 * -- Bug fix: On RFP and LFP dialup, the password fetch routine * 287 * did not properly set the NVM base page before reading * 288 * the flag byte. Consequently, the second password of * 289 * the pair was always used (due to non-zero data in the * 290 * higher NVM banks). * 291 * -- Bug Fix: The Write.NVM routine checked improperly to see * 292 * if the write was initiated by the front panel. It * 293 * always entered the wait routine to wait for NVM not * 294 * busy (immediate exit). * 295 * -- Bug Fix: The Bus_Error routine set pause and BSE on the * 296 * bus, but failed to update Ram_WBCR. This meant that * 297 * the TICK routine continued to try storing the clock * 298 * to memory (with repetitive bus errors). Since each * 299 * bus error creates a process, this overflowed the * 300 * process stack and gave an SSU HALT01. * 301 * -- Microcode cleanup: Combined DCB bytes that had been on * 302 * NOPs with the following or preceeding opcodes, in * 303 * some cases, expanding a macro. Saves space and time. * 304 * * 305 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 7 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Revision Log 307 308 **************************************************************************************************************** 309 * * 310 * Rev 16 ---- released 10 Mar, 1992 * 311 * * 312 * -- Typos: fixed a few typos in some comments. * 313 * -- Commentary: added comments where needed. * 314 * -- Fixed bug: during boot and selftest operations, the selftest * 315 * responses were tested too early, and there was no checking * 316 * for bus errors during certain operations. * 317 * -- Fixed bug: RDU class 4 commands were not properly checked for * 318 * valid sub-classes. A write was impossible to invoke. * 319 * -- Fixed bug: RDU operations were not properly setting the * 320 * RO page modified flag due to a missing instruction. * 321 * -- Fixed bug: When sending multiple blocks of characters to the * 322 * RDU, a 4 character response indicating -MORE- was possible * 323 * even though the buffer was actually empty. * 324 * -- Microcode cleanup: Initialization process setup is now cleaner * 325 * -- Microcode cleanup: Altered Call macro so that some returns can * 326 * now go directly to a desired location, rather than returning * 327 * to a jmp. * 328 * -- Microcode cleanup: Combined DCB bytes that had been on * 329 * NOPs with the following or preceeding opcodes, in * 330 * some cases, expanding a macro. Saves space and time. * 331 * -- Listing cleanup: Split several files to reduce their size. * 332 * -- Added feature: The initial Baud rate for the remote and local * 333 * front panels now is selected based on the length of the * 334 * received BREAK. Also, a break received in the middle of * 335 * a session can reset the baud rate based on the length of * 336 * the break and will flush the input buffer. * 337 * -- Added feature: Input and output processes for the remote and * 338 * local front panels modified to allow for multiple commands * 339 * in the pipeline. This involves major changes in all * 340 * areas of the RDU communications code (file *.text7) * 341 * * 342 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 8 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Definitions 345 346 **************************************************************************************************************** 347 * * 348 * System Services Unit * 349 * * 350 * Read/Write requests from system bus * 351 * ----------------------------------- * 352 * * 353 * ADDRESS FUNCTION * 354 * ------- -------- * 355 * * 356 * 000C00-000FFF R/W SSU Ram (1 byte wide in bits 24:31) * 357 * * 358 * 001000-0011FF R Bootstrap PROM (32 bits wide) * 359 * * 360 * 001401 R/W most significant 12 bits of clock * 361 * 001402 R/W least significant 32 bits of clock * 362 * 001403 W increment clock * 363 * 001404 W decrement clock * 364 * 001405 W CPU Halt/Stop message -- "HLTn ahhhh" or "STPn ahhhh" * 365 * in the display. * 366 * bit[8] = 0 for halt, 1 for stop * 367 * bit[10:15] = 6 bit ASCII character for display ("a") * 368 * bit[16:31] = 4 hex digits for display ("hhhh") * 369 * A write to this location causes PAUSE to be * 370 * asserted, a GO to be sent to the sending CPU (in * 371 * slot "n"), and the control panel display * 372 * mentioned above. * 373 * 001406 W CPUn ERRhh (CPU Error) message * 374 * A write here causes PAUSE to be asserted, the * 375 * control panel message to be displayed, and the * 376 * data word to be stored in the SSU's CPU Error * 377 * Buffer for slot "n" (which is the slot number * 378 * of the CPU doing this write). ("hh" in the * 379 * display is the 8 most significant bits of the * 380 * data word displayed in hex.) * 381 * 001408 W send character out to UART * 382 * Bit[22] = 1 if character is a dwell count * 383 * Bit[23] = 1 if character is a break count * 384 * Bit[24:31] = character or break/dwell count * 385 * R sign bit set if OK to send out a character * 386 * 001409 R/W 16 bit time to interrupt in bits[16:31] * 387 * 00140A R/W characters 0,1,2,3 of (OS) control panel display * 388 * 00140B R/W characters 4,5,6,7 of (OS) control panel display * 389 * 00140C R/W characters 8,9 of (OS) control panel display * 390 * These are all 6 bit ASCII characters. The most * 391 * significant bit of each byte is the decimal * 392 * point for that character. When reading, bit 1 * 393 * of character 8 is the sonalert bit, and bit 1 * 394 * of character 9 is the alarm light bit. When * 395 * writing, address 140C bit 26 and bit 27 are the * 396 * sonalert and alarm light bits, respectively. * 397 * 00140D R character in from UART - Sign bit on says new char, * 398 * bit 23 on if char was really break, character * 399 * undefined if read before. * 400 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 9 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Definitions 402 403 **************************************************************************************************************** 404 * * 405 * ADDRESS FUNCTION * 406 * ------- -------- * 407 * * 408 * 00140E R read misc. status bits * 409 * #00000001 local front panel connected * 410 * #00000002 this SSU is supplying bus clock * 411 * #00000004 NVM not busy * 412 * 00140F R/W interrupt mask * 413 * Bit[24] = UART received character input * 414 * Bit[25] = UART ready to output * 415 * Bit[27] = 1 to enable automatic Clock Store function * 416 * Bit[28] = SSU ready to supply error code * 417 * Bit[29] = Non-volatile memory ready for write * 418 * Bit[30] = Control panel switch change * 419 * Bit[31] = Timer timeout * 420 * 001410 R front panel switches at boot time * 421 * Bit[0] = 1 when not booted from switches * 422 * Bit[24:31] = switch setting at boot time * 423 * (same format as address 1411) * 424 * W a write here will cause a "BOOT" operation * 425 * Bit[28:31] = boot number * 426 * 001411 R/W current front panel switches * 427 * BIT[24] = Run(1)/Halt(0) switch * 428 * BIT[25] = Sense(1)/Boot(0) switch * 429 * BIT[26] = Remote Maintainance switch (on=1, off=0) * 430 * BIT[27] = Power (0 if power switch is on, 1 if off) * 431 * BIT[28] = Sense switch 1 * 432 * BIT[29] = Sense switch 2 * 433 * BIT[30] = Sense switch 3 * 434 * BIT[31] = Sense switch 4 * 435 * 001412 R read and clear error log information * 436 * Bit[29] = Write to port 0 when there was no room. * 437 * Bit[30] = Write to NVM when NVM was not ready. * 438 * Bit[31] = Read from NVM when NVM was not ready. * 439 * 001413 R/W characters 0,1,2,3 of (SSU'S) control panel display * 440 * 001414 R/W characters 4,5,6,7 of (SSU'S) control panel display * 441 * 001415 R/W characters 8,9 of (SSU'S) control panel display * 442 * These are the same format as addresses 140A:140C * 443 * above, except that the sonalert and alarm light * 444 * bits are not used. * 445 * * 446 * 001416 R/W real time clock (32 MS bits) * 447 * 001417 R/W clock store address * 448 * DATA[4:7] = slot number of memory * 449 * DATA[8:31] = memory address of double word * 450 * to store clock into every millisecond. * 451 * * 452 * 001800-001FFF R/W NVM (1 byte wide in bits 24:31) * 453 * * 454 **************************************************************************************************************** 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 10 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Definitions 456 457 **************************************************************************************************************** 458 * * 459 * SSU ERR mn * 460 * ---------- * 461 * * 462 * If the SELF TEST of the SSU fails the SSU puts "SSU ERR mn" * 463 * in the "blue lights". * 464 * * 465 * m - Main Error type * 466 * n - Error subtype * 467 * * 468 **************************************************************************************************************** 469 470 * Error code definitions 0031 471 SSUErr_Clock equ '1' Real Time Clock is not ticking 0032 472 SSUErr_Ram equ '2' Ram error 473 0033 474 SSUErr_Bus equ '3' Bus error 0031 475 BusErr_Reset equ '1' Cannot reset bus logic 0032 476 BusErr_WBTOR equ '2' WBTOR and or status not working 0033 477 BusErr_CBN equ '3' Call back error 0034 478 BusErr_Data equ '4' Data path error 0035 479 BusErr_GPar equ '5' Parity error when good parity expected 0036 480 BusErr_BPar equ '6' Parity error when bad parity forced in one bit 481 0034 482 SSUErr_CP equ '4' Cannot write/read Control Panel switches 0035 483 SSUErr_Boot equ '5' Bootstrap prom will not verify 0036 484 SSUErr_BCR equ '6' Cannot write/read Bus Control Register 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 11 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Definitions 486 487 **************************************************************************************************************** 488 * * 489 * ERRX SLOTN * 490 * ---- ----- * 491 * * 492 * When the SSU detects that a BUS ERROR has occurred it * 493 * displays "ERRx SLOTn" in the "blue lights". * 494 * * 495 * The "x" is the error code defined below. * 496 * The "n" is the slot that appears to be responsible for the error. * 497 * * 498 **************************************************************************************************************** 499 0001 500 BE_PARITY Equ 1 BUS ERROR 1 = BUS PARITY ERROR 0002 501 BE_FLAGS Equ 2 BUS ERROR 2 = FLAGS WRONG OR DBW BIT WRONG 0003 502 BE_COMMAND Equ 3 BUS ERROR 3 = BAD COMMAND CODE 0004 503 BE_ADDRESS Equ 4 BUS ERROR 4 = ILLEGAL ADDRESS 0005 504 BE_RTOTIME Equ 5 BUS ERROR 5 = RTO TIMEOUT 0006 505 BE_RESPTIME Equ 6 BUS ERROR 6 = RESPONSE TIMEOUT 0009 506 BE_DATACK Equ 9 BUS ERROR 9 = DATA WRONG DURING BOOT 507 508 509 **************************************************************************************************************** 510 * * 511 * SSU initialization error codes * 512 * * 513 * These are errors the SSU can get when doing initialization or Boot * 514 * * 515 **************************************************************************************************************** 516 0001 517 IE_Init_Bse equ 1 someone is asserting BSE after the initial BCR stuff 518 0011 519 IE_Poll_Bse equ #11 some bus error during Poller -- see WRUs for more detail 0012 520 IE_Poll_NoMem equ #12 No Memory found during Poller 521 0021 522 IE_St_Bse equ #21 some bus error during SendSelfTest -- see WRUs for more detail 0022 523 IE_St_StErr equ #22 someone didn't pass their self test 524 0031 525 IE_ICPU_Bse equ #31 some bus error during ICPU -- see WRUs for more detail 0032 526 IE_ICPU_NoCPU equ #32 No CPU found during ICPU 527 0041 528 IE_Sb_Bse equ #41 some bus error during Store_Boot -- see WRUs for more detail 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 12 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 531 532 **************************************************************************************************************** 533 **************************************************************************************************************** 534 **************************************************************************************************************** 535 * MACROS MACROS MACROS MACROS MACROS * 536 **************************************************************************************************************** 537 **************************************************************************************************************** 538 **************************************************************************************************************** 539 540 541 542 **************************************************************************************************************** 543 * * 544 * ALIGN , * 545 * ---------------------------- * 546 * * 547 * Make sure * and *+-1 are on the same page. * 548 * is the maximum displacememt on a page * 549 * and will usually be: #FF (256 for internal registers) * 550 * or: #1F (32 for I/O ports). * 551 * If there is not enough room on the current page, the ALIGN macro * 552 * will insert a JMP instruction to the next page and then ORG there. * 553 * * 554 * At the end of the block, at '*+-1' (just before the last * 555 * instruction), you must invoke the macro CHECKALIGN. * 556 * * 557 * It should be noted that the CHECKALIGN macro may or may not put a * 558 * JMP instruction into the instruction stream. This means that if * 559 * you want the '*+' instruction to have a label that you can * 560 * get to with an NZT or an XEC from within the aligned block, then you * 561 * must put the label on the CHECKALIGN instruction line. It also * 562 * means that if you are using an XEC instruction to execute the * 563 * '*+' instruction, then it must be okay for it to be a JMP * 564 * instruction. * 565 * * 566 * The ALIGN Macro may be nested. * 567 * * 568 **************************************************************************************************************** 569 570 571 >>>>>>>>>>>>>>>>>>>>> 572 > 573 > Macro ,,Parameter 574 > Name ALIGN 575 > If ((* BOR $Parameter(1)) GE (*+$Parameter(2)-1)), Goto .Align.1 576 > Local JMP.Label,JMP.Size,Counter,Good.Hole,Good.Hole.Sz 577 >JMP.Size Equ (* BOR $Parameter(1))-*+1 578 > If JMP.Size LT 20, Goto .Small.Hole 579 > If ($Parameter(1) EQ #FF), Goto .Large.Hole 580 >.Small.Hole 581 >A.Waste:$JMP.Size ReEqu * 582 >Align.Wasted ReEqu Align.Wasted+JMP.Size 583 > JMP JMP.Label 584 > ORG ((*-1) BOR $Parameter(1))+1 585 >JMP.Label Equ * 586 >.Align.1 587 >Align.Lev ReEqu Align.Lev+1 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 13 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 588 >A.Label:$Align.Lev ReEqu * 589 >A.Page:$Align.Lev ReEqu $Parameter(1) 590 >A.Count:$Align.Lev ReEqu $Parameter(2) 591 > Exit 592 > 593 > 594 > 595 > 596 >.Large.Hole 597 >Good.Hole Equ 0 598 >Good.Hole.Sz Equ #100 599 >Counter Equ 1 600 > 601 >.Hole.Loop If Counter GT Holes, Goto .Check.Hole 602 > If Hole.Sz:$Counter LE $Parameter(2), Goto .Next.Hole 603 > If Hole.Sz:$Counter GE Good.Hole.Sz, Goto .Next.Hole 604 >Good.Hole ReEqu Counter 605 >Good.Hole.Sz ReEqu Hole.Sz:$Counter 606 >.Next.Hole 607 >Counter ReEqu Counter+1 608 > Goto .Hole.Loop 609 > 610 >.Check.Hole If Good.Hole EQ 0, Goto .No.Hole 611 >Hole.Sz:$Good.Hole ReEqu Hole.Sz:$Good.Hole-$Parameter(2)-2 612 >Align.Wasted ReEqu Align.Wasted-$Parameter(2)-2 613 > JMP Hole.St:$Good.Hole 614 >Hole.Temp.PC ReEqu * 615 > Org Hole.St:$Good.Hole 616 >Hole.St:$Good.Hole ReEqu Hole.St:$Good.Hole+$Parameter(2)+2 617 >Hole.Flag ReEqu 1 618 > Goto .Align.1 619 > 620 >.No.Hole 621 >Holes ReEqu Holes+1 622 >Hole.St:$Holes Equ *+1 623 >Hole.Sz:$Holes Equ JMP.Size-2 624 > Goto .Small.Hole 625 > 626 > Emac 627 > 628 >>>>>>>>>>>>>>>>>>>>> 629 630 631 0000 632 Align.Lev Equ 0 0000 633 Align.Wasted Equ 0 0000 634 Holes Equ 0 0000 635 Hole.Flag Equ 0 0000 636 Hole.Temp.PC Equ 0 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 14 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 638 639 640 **************************************************************************************************************** 641 * * 642 * CHECKSKIP * 643 * CHECKSKIP.IO * 644 * ------------ * 645 * * 646 * Make sure * and *+2 are on the same page. To be used before a "NZT *+2". * 647 * * 648 **************************************************************************************************************** 649 650 651 >>>>>>>>>>>>>>>>>>>>> 652 > 653 > Macro ,,Parameter 654 > Name CHECKSKIP, Local Page.Size 655 >Page.Size ReEqu #FF 656 > Goto .Check.Skip.1 657 > Name CHECKSKIP.IO, Local Page.Size 658 >Page.Size ReEqu #1F 659 >.Check.Skip.1 If ((* BAND Page.Size) LT (Page.Size-1)), Exit 660 >A.Waste0002 ReEqu * 661 >Align.Wasted ReEqu Align.Wasted+2 662 > JMP (* BOR Page.Size)+1 663 > ORG ((*-1) BOR Page.Size)+1 664 > Exit 665 > Emac 666 > 667 >>>>>>>>>>>>>>>>>>>>> 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 15 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 669 670 **************************************************************************************************************** 671 * * 672 * CHECKALIGN * 673 * ---------- * 674 * * 675 * Check to see that the current ALIGN is correct. * 676 * * 677 **************************************************************************************************************** 678 679 680 >>>>>>>>>>>>>>>>>>>>> 681 > 682 > Macro ,,NoParameters 683 > Name CHECKALIGN 684 > Local Align.Test 685 >Align.Test ReEqu ((A.Page:$Align.Lev BOR *) NE (A.Page:$Align.Lev BOR A.Label:$Align.Lev)) 686 > If Align.Test, We've an Alignment Error 687 > If ((A.Count:$Align.Lev+A.Label:$Align.Lev-1) LT *), We've an Alignment Miscount 688 >Align.Lev ReEqu Align.Lev-1 689 > If (Align.Lev GE 0), Goto .Align.Exit 690 > If (Align.Lev LT 0), We've improperly Nested ALIGN/CHECKALIGN 691 >Align.Lev ReEqu 0 692 >.Align.Exit If Hole.Flag EQ 0, Exit 693 > JMP Hole.Temp.PC 694 > ORG Hole.Temp.PC 695 >Hole.Flag ReEqu 0 696 > Exit 697 > Emac 698 > 699 >>>>>>>>>>>>>>>>>>>>> 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 16 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 701 702 **************************************************************************************************************** 703 * * 704 * LOAD , * 705 * -------------------------------- * 706 * * 707 * Note: This macro does not work with RBU * 708 **************************************************************************************************************** 709 710 711 >>>>>>>>>>>>>>>>>>>>> 712 > 713 > Macro ,,Parameter 714 > Name LOAD 715 > Reset Register,$Parameter(2) 716 > List Macros 717 > XMIT $Parameter(1),IVR 718 > NOP RRAM 719 > Nolist Macros 720 > IF '$Register(1,1)' EQ 'R', Goto .LoadBTest 721 > IF '$Register(1,1)' NE 'r', Goto .LoadReg 722 >.LoadBTest IF '$Register(2,1)' EQ 'B', Goto .Load0Test 723 > IF '$Register(2,1)' NE 'b', Goto .LoadReg 724 >.Load0Test IF '$Register(3,1)' NE '0', Goto .LoadReg 725 > Exit 726 >.LoadReg 727 > List Macros 728 > MOVE RB0,$Register 729 > Nolist Macros 730 > Exit 731 > Emac 732 > 733 >>>>>>>>>>>>>>>>>>>>> 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 17 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 735 736 **************************************************************************************************************** 737 * * 738 * STORE , * 739 * * 740 * StoreI , * 741 * --------------------------------- * 742 * * 743 * Note: This macro does not work with RBU or IVR * 744 **************************************************************************************************************** 745 746 747 >>>>>>>>>>>>>>>>>>>>> 748 > 749 > Macro ,,Parameter 750 > Name STORE 751 > Reset Register,$Parameter(1) 752 > IF '$Register(1,1)' EQ 'R', Goto .StoreBTest 753 > IF '$Register(1,1)' NE 'r', Goto .StoreReg 754 >.StoreBTest IF '$Register(2,1)' EQ 'B', Goto .Store0Test 755 > IF '$Register(2,1)' NE 'b', Goto .StoreReg 756 >.Store0Test IF '$Register(3,1)' NE '0', Goto .StoreReg 757 > Goto .StoreRB0 758 >.StoreReg 759 > List Macros 760 > MOVE $Register,RB0 761 > Nolist Macros 762 > Goto .StoreRB0 763 > 764 > NAME StoreI 765 > Local Value 766 >Value Equ $Parameter(1) 767 >.MakePosLoop IF Value GE 0, Goto .Positive 768 >Value Reequ Value+256 769 > Goto .MakePosLoop 770 > 771 >.Positive IF Value LE #1F, Goto .SmallValue 772 > List Macros 773 > XMIT $Parameter(1),AUX 774 > MOVE AUX,RB0 775 > Nolist Macros 776 > Goto .StoreRB0 777 >.SmallValue 778 > List Macros 779 > XMIT $Parameter(1),RB0 780 > Nolist Macros 781 > 782 >.StoreRB0 783 > List Macros 784 > XMIT $Parameter(2),IVR 785 > NOP WRAM 786 > Nolist Macros 787 > Exit 788 > Emac 789 > 790 >>>>>>>>>>>>>>>>>>>>> 1BTI SSU 7 Assembler Rev 2.3 19-Mar-92 19:02 Page 18 SSU Rev 16 Microcode Ucode.HrdSSU:SSU16.Text1 File# 1 Macro definitions 792 793 **************************************************************************************************************** 794 * * 795 * DIS,, * 796 * ----------------------------------- * 797 * * 798 * Display at on front panel. * 799 * * 800 **************************************************************************************************************** 801 802 803 >>>>>>>>>>>>>>>>>>>>> 804 > Macro ,Modifier,Parameter 805 > Name DIS 806 > Local Index,Position,Pos.String 807 >Index ReEqu 1 808 >Position ReEqu $Modifier(2) 809 > XMIT ('$Parameter(Index,1)' BAND #3F),AUX 810 > Goto .DIS.First 811 >.DIS.Loop XMIT ('$Parameter(Index,1)' BAND #3F),AUX WCPD$Pos.String(4,1) 812 >.DIS.First MOVE AUX,RB0 813 > Reset Pos.String,$Position 814 >Index ReEqu Index+1 815 >Position ReEqu Position-1 816 > If Index LT $Modifier(1)+1, Goto .DIS.Loop 817 > NOP WCPD$Pos.String(4,1) 818 > Exit 819 > Emac 820 >>>>>>>>>>>>>>>>>>>>> 821 822 **************************************************************************************************************** 823 * * 824 * DELAY